1.我现在432p401r功耗太高,外设都已拆除,我用code1 代码功耗又800ua 用code2 功耗只有6ua，但是最终我是要用code1这部分
个人感觉是power这一块没有配置好，但是不知道怎么样去设置。
/////////////////////////////////////////code 1/ //////////////////////////////////////////////
Error_Block eb;
Error_init(&eb);
/* Call board init functions */
Board_initGeneral();
Board_initGPIO();
#ifndef SOFT_I2C_BUS
Board_initI2C();
#endif
// Board_initSPI();
//Board_initADC();
// Board_initUSB(Board_USBDEVICE);
#ifdef SUPPORT_WATCHDOG
Board_initWatchdog();
#endif
// Configure clocks
//Sys_init_clocks(MCU_MCLK);
#ifndef USE_NEW_SYS_CONFIG
delay_ms(200);// wait for internal flash is stable
// System parameters config.
Sys_config();
//Init Rtc
Rtc_init();
#endif
//Init ADC.
//Adc_init();
//Init I2C.
//I2c_init();
//Init SPI.
//Spi_init();
//Init buzzer.
//Sys_buzzer_init();
//System task create.
//Sys_task_create();
#if 0 //ndef USE_NEW_SYS_CONFIG
//Network task create.
Nwk_task_create();
#endif
//Usb task create.
//Usb_task_create();
/* Start BIOS */
BIOS_start();
///////////////////////////////code2////////////////////////////
WDTCTL = WDTPW | WDTHOLD;
/* Configuring P1.0 as output and P1.1 (switch) as input with pull-up resistor*/
/* Rest of pins are configured as output low */
/* Notice intentional '=' assignment since all P1 pins are being deliberately configured */
P1DIR = ~(uint8_t) BIT1;
P1OUT = BIT1;
P1REN = BIT1; // Enable pull-up resistor (P1.1 output high)
P1SEL0 = 0;
P1SEL1 = 0;
P1IFG = 0; // Clear all P1 interrupt flags
P1IE = BIT1; // Enable interrupt for P1.1
P1IES = BIT1; // Interrupt on high-to-low transition
// Enable Port 1 interrupt on the NVIC
NVIC->ISER[1] = 1 << ((PORT1_IRQn) & 31);
// Terminate all remaining pins on the device
P2DIR |= 0xFF; P2OUT = 0;
P3DIR |= 0xFF; P3OUT = 0;
P4DIR |= 0xFF; P4OUT = 0;
P5DIR |= 0xFF; P5OUT = 0;
P6DIR |= 0xFF; P6OUT = 0;
P7DIR |= 0xFF; P7OUT = 0;
P8DIR |= 0xFF; P8OUT = 0;
P9DIR |= 0xFF; P9OUT = 0;
P10DIR |= 0xFF; P10OUT = 0;
P1DIR |= 0xFF; P2OUT = 0;
P2DIR |= 0xFF; P2OUT = 0;
/* Configure Port J */
PJDIR |= (BIT2 | BIT3); PJOUT &= ~(BIT2 | BIT3);
/* PJ.0 & PJ.1 configured for XT1 */
PJSEL0 |= BIT0 | BIT1;
PJSEL1 &= ~(BIT0 | BIT1);
/* Starting LFXT in non-bypass mode without a timeout. */
CS->KEY = CS_KEY_VAL ;
CS->CTL1 &= ~(CS_CTL1_SELA_MASK | CS_CTL1_SELB);
CS->CTL1 |= CS_CTL1_SELA__LFXTCLK; // Source LFXTCLK to ACLK & BCLK
CS->CTL2 &= ~(CS_CTL2_LFXTDRIVE_MASK); // Configure to lowest drive-strength
CS->CTL2 |= CS_CTL2_LFXT_EN;
while (CS->IFG & CS_IFG_LFXTIFG)
CS->CLRIFG |= CS_IFG_LFXTIFG;
CS->KEY = 0;
/* Turn off PSS high-side supervisors */
PSS->KEY = PSS_KEY_KEY_VAL;
PSS->CTL0 |= PSS_CTL0_SVSMHOFF;
PSS->KEY = 0;
/* Enable PCM rude mode, which allows to device to enter LPM3 without waiting for peripherals */
PCM->CTL1 = PCM_CTL0_KEY_VAL | PCM_CTL1_FORCE_LPM_ENTRY;
/* Enable all SRAM bank retentions prior to going to LPM3 */
SYSCTL->SRAM_BANKRET |= SYSCTL_SRAM_BANKRET_BNK7_RET;
__enable_interrupt();
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; // Do not wake up on exit from ISR
/* Setting the sleep deep bit */
SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);
/* Go to LPM3 */
__sleep();
