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C5517 MCBSP做I2S接口使用

Dear TI:

目前我们想使用MCBSP接口作为两组I2S来使用,MCBSP_CLKX/MCBSP_FSX/MCBSP_DX为一组I2S做master使用,MCBSP_CLKS/MCBSP_FSR/MCBSP_DR为一组I2S做slave使用,两组I2S格式都为16bit/双通道/采样率48K,请问我该如何设置??

  • 可以参考下面的应用报告。
    www.ti.com/.../spra595.pdf
  • Dear Shine:
    我看每个寄存器都区分U和L,一般是使用哪种呢?
  • “我看每个寄存器都区分U和L” U和L是什么意思?
  • linhai zhang 说:
    我看每个寄存器都区分U和L,一般是使用哪种呢?

    因为相应的寄存器需要32bit来描述及配置。而C55x是16bit的CPU,所以分为高16bit(U)和低16bit(L).

  • Dear Tony:
    理解了,谢谢!
    想我想用CLKOUT输出一个12Mhz的频率供其他模块使用,我使用的是库版本是c55_csl_3.08,请问我该如何设置呢?看规格书上是要设置CLKOUTCR这个寄存器,但是在库中找不到对应的接口,请帮忙指导一下!

    Thanks
  • 直接写寄存器就好了。
  • Dear Tony:
    在使用DMA传输DRRL/DXRL数据的时候存在一些问题
    e2e.ti.com/.../2014444
    按照上面提问的解析我设置的DMA地址如下,例程中的地址也是这样的,可是在传输数据的时候仿真发现只能传输一次数据,可是我们需要的是轮询传输,请指导一下如何设置;
    CSL_DMA3_REGS->DMACH0DSAL = 0x6010;//设置DXRL地址
    CSL_DMA3_REGS->DMACH1DSAL = 0x6000;//设置DRRL地址

    Thanks!
  • linhai zhang 说:
    可是在传输数据的时候仿真发现只能传输一次数据,可是我们需要的是轮询传输,

     需要你把代码发上来看一下,C55的DMA用起来稍有一点特殊。

  • Dear Tony:

    代码设置如下:

    CSL_Status CSL_McBSPTest(void)
    {
    
    #if (defined(CHIP_C5517))
    	//Uint16 i;
    	//unsigned char error=0;
    	CSL_Status status; //This is for the CSL status return
    
    	/* Open MCBSP Port 0, this will return a MCBSP handle that will */
    	/* be used in calls to other CSl functions.                     */
    	hMcbsp = MCBSP_open(CSL_MCBSP_INST_0, &McbspObj,&status);
    	if ( (hMcbsp == NULL) || (status != CSL_SOK) )
    	{
    	printf("MCBSP_open() Failed \n");
    	}
    	else
    	{
    	printf("MCBSP_open() Success \n");
    	}
    
    	CSL_FINS(hMcbsp->sysRegs->EBSR,SYS_EBSR_SP0MODE,CSL_SYS_EBSR_SP0MODE_MODE3);
    
    #ifdef USE_MCBSP_TARGET
     // To configure the McBSP target through GPIO on S1
     //   ====================================================================================================================
     //   MCBSP Target Mode     | GPIO Data | Data          |  Frame Sync |   Clock                 | External Clock         |
     //                         | [9:6]     | Loop back     | Loop back   |  Loop back              | Connection             |
     //   ====================================================================================================================
     //   MCBSP_TGT_NO_LB       |  0000     |  No loop back |  --         |  --                     |  --                    |
     //   MCBSP_TGT_LB_MODE0    |  0001     |  dx -> dr     |  fsr -> fsx |  clkr -> clkx           |  --                    |
     //   MCBSP_TGT_LB_MODE1    |  0011     |  dx -> dr     |  fsx -> fsr |  clkr -> clkx           |  --                    |
     //   MCBSP_TGT_LB_MODE2    |  0101     |  dx -> dr     |  fsr -> fsx |  clkx -> clkr           |  clkx -> clks          |
     //   MCBSP_TGT_LB_MODE3    |  0111     |  dx -> dr     |  fsx -> fsr |  clkx -> clkr           |  clkx -> clks          |
     //   MCBSP_TGT_LB_MODE4    |  1001     |  dx -> dr     |  fsr -> fsx |  External Clock -> clkx |  --                    |
     //   MCBSP_TGT_LB_MODE5    |  1011     |  dx -> dr     |  fsx -> fsr |  External Clock -> clkx |  --                    |
     //   MCBSP_TGT_LB_MODE6    |  1101     |  dx -> dr     |  fsr -> fsx |  External Clock -> clkr |  External Clock -> clks|
     //   MCBSP_TGT_LB_MODE7    |  1111     |  dx -> dr     |  fsx -> fsr |  External Clock -> clkr |  External Clock -> clks|
     //   ====================================================================================================================
    MCBSP_target_config(MCBSP_TGT_LB_MODE3);
    #endif
    
    #if 0
    	/* Initialize Dma */
    	status = DMA_init(); //前面I2S的时候已经初始化过DAM
    	if (status != CSL_SOK)
    	{
    	printf("DMA_init Failed!\n");
    	}
    #endif
    
    #if 1
        /* Configure the DMA channel for mcbsp transmit */
    #if ((defined(CHIP_C5505_C5515)) || (defined(CHIP_C5504_C5514)) || defined(CHIP_C5517) || (defined(CHIP_C5535) || defined(CHIP_C5545)))
    	dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
    #endif
    	dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
    	dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
    	dmaConfig.trigger  = CSL_DMA_EVENT_TRIGGER;
    	dmaConfig.dmaEvt   = CSL_DMA_EVT_MCBSP_TX;
    	dmaConfig.dmaInt   = CSL_DMA_INTERRUPT_DISABLE;
    	dmaConfig.chanDir  = CSL_DMA_WRITE;
    	dmaConfig.trfType  = CSL_DMA_TRANSFER_IO_MEMORY;
    	dmaConfig.dataLen  = (CSL_I2S_DMA_BUF_LEN*4*4);
    	dmaConfig.srcAddr  = (Uint32)i2sDmaREFBuff;//i2sDmaMICBuff;//
    	dmaConfig.destAddr = (Uint32)&(hMcbsp->Regs->DXRL);
    
    	dmaMcBSPMICTxHandle = CSL_configDmaForMcbsp(&dmaObj, CSL_DMA_CHAN12);
    	if(dmaMcBSPMICTxHandle == NULL)
    	{
    		printf("DMA Config for mcbsp DMA Write Failed!\n!");
    		//return(CSL_MCBSP_TEST_FAILED);
    	}
    
    #endif
    
    #if 1
        // Configure the DMA channel for mcbsp receive
    #if ((defined(CHIP_C5505_C5515)) || (defined(CHIP_C5504_C5514)) || (defined(CHIP_C5517)) || (defined(CHIP_C5535) || defined(CHIP_C5545)))
    	dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
    #endif
    	dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
    	dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
        dmaConfig.trigger  = CSL_DMA_EVENT_TRIGGER;
        dmaConfig.dmaEvt   = CSL_DMA_EVT_MCBSP_RX;
    	dmaConfig.dmaInt   = CSL_DMA_INTERRUPT_DISABLE;
    	dmaConfig.chanDir  = CSL_DMA_READ;
    	dmaConfig.trfType  = CSL_DMA_TRANSFER_IO_MEMORY;
    	dmaConfig.dataLen  = (CSL_I2S_DMA_BUF_LEN*4*4);
    	dmaConfig.srcAddr  = (Uint32)&(hMcbsp->Regs->DRRL);
    	dmaConfig.destAddr = (Uint32)i2sDmaREFBuff;
    
    	dmaMcBSPREFRxHandle = CSL_configDmaForMcbsp(&dmaObj,CSL_DMA_CHAN13);
    	if(dmaMcBSPREFRxHandle == NULL)
    	{
    		printf("DMA Config for mcbsp DMA Read Failed!\n!");
    		return(CSL_MCBSP_TEST_FAILED);
    	}
    #endif
    	CSL_DMA3_REGS->DMACH0DSAL = 0x6010;
    	//CSL_DMA3_REGS->DMACH0DSAU = 0x0000;
    
    	CSL_DMA3_REGS->DMACH1DSAL = 0x6000;
    	//CSL_DMA3_REGS->DMACH1DSAU = 0x0000;
    
      /* Write configuration structure values to MCBSP control register*/
    
    #ifdef USE_MCBSP_TARGET
     /** Input clock in Hz -- As our test cases will always run on QT we are always assigning the PHOENIX_QTCLK to this structure member*/
    	McBSPconfig.clkInput = PHOENIX_QTCLK;
    #else
    	McBSPconfig.clkInput = 200000000;
    #endif
    	/* Operating mode */
    	McBSPconfig.mcbsp_opmode = (CSL_McbspOpMode)CSL_MCBSP_OPMODE_NORMAL;
    	//McBSPconfig.mcbsp_opmode = CSL_MCBSP_OPMODE_128CHANNEL;
    	/**Word length selection
    	Valid values - 8,12,16,20,24,32bits*/
    	McBSPconfig.wordLength = CSL_MCBSP_WORD16;
    	/**Frame length selection
    	Valid values - (1-128)*/
    	McBSPconfig.frameLength = CSL_MCBSP_FRMAELENGHT(1);
    	/** single phase frame/double phase frame*/
    	McBSPconfig.phase = CSL_MCBSP_DUALPHASE;
    	/** data delay*/
    	McBSPconfig.datadelay = CSL_MCBSP_DATADELAY0BIT;
    	/** frame ignore flag */
    	McBSPconfig.frameignore = CSL_MCBSP_FRMAEIGNOREFALSE; //?
    	/**Loopback mode enable/disable*/
    	McBSPconfig.loopBackmode = CSL_MCBSP_INTERNALLOOPBACK_DISABLE;
    	/**Companding*/
    	McBSPconfig.companding = CSL_MCBSP_COFF_MSBFIRST;
    	/**Rjust mode*/
    	McBSPconfig.rjust_mode = CSL_MCBSP_RJUST_RJZFMSB;
    	/**Abis mode*/
    	McBSPconfig.abismode = CSL_MCBSP_ABIS_DISABLE;
    	/**DXENA enable/disable*/
    	McBSPconfig.dxena = CSL_MCBSP_DXENA_DISABLE;
    	/**CLKSTP */
    	McBSPconfig.clkstp = CSL_MCBSP_SPCRL_CLKSTP_DISABLE;
    	/**CLKXP,CLKRP */
    	McBSPconfig.sample_polarity = CSL_MCBSP_DATASAMPLE_FALLING;
    	/**FRAMESYNC */
    	McBSPconfig.fs_polarity = CSL_MCBSP_FS_ACTIVEHIGH;
    	/** Clock Source */
    	McBSPconfig.clocksource = CSL_MCBSP_CLOCKSOURCE_SYSCLK;
    	/** Interrupt Source */
    	McBSPconfig.intr_event = CSL_MCBSP_INTR_RDY;  //?
    	/*sample rate(samples per sec) */
    	McBSPconfig.sample_rate = 48000;
    	/*FSX pin source */
    	McBSPconfig.fsxpin_status = CSL_MCBSP_FSX_SRGOP;
    
    	MCBSP_reset(hMcbsp);
    	Mcbsp_Configure(hMcbsp, &McBSPconfig);
    #if 1//MCBSP_SET //重新设置mcbsp兼容I2S传输,48K、双通道、16bit
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_FSXM,ONE); //out
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_FSRM,ZERO);
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXM,ONE);
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKRM,ZERO);
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXP,RISINGEDGE);
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXP,FALLINGEDGE);
    
    	CSL_FINST(hMcbsp->Regs->XCRU,MCBSP_XCRU_XPHASE,DUALPHASE);
    	CSL_FINS(hMcbsp->Regs->XCRL,MCBSP_XCRL_XFRLEN1,McBSPconfig.wordLength);  //16bit
    	CSL_FINS(hMcbsp->Regs->XCRU,MCBSP_XCRU_XFRLEN2,McBSPconfig.wordLength);  //16bit
    	CSL_FINS(hMcbsp->Regs->XCRL,MCBSP_XCRL_XFRLEN1,McBSPconfig.frameLength);
    	CSL_FINS(hMcbsp->Regs->XCRU,MCBSP_XCRU_XFRLEN2,McBSPconfig.frameLength);
    
    	CSL_FINST(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_FSGM,ONE);
    	CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_FPER,31);//McBSPconfig.wordLength
    	CSL_FINS(hMcbsp->Regs->SRGRL,MCBSP_SRGRL_FWID,15);
    	//((clkInput/(sample_rate*wordLength*2)) - 1)
    	CSL_FINS(hMcbsp->Regs->SRGRL,MCBSP_SRGRL_CLKGDV,132);
    
    	/*Not handled in CSl CLKSP and GSYNC of SRGRU */
    	CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_CLKSP,0);
    	CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_GSYNC,0);
    
    	/*Not handled bits in PCR by CSL */
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXM,ONE);
    	CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKRM,ZERO);
    	CSL_FINST(hMcbsp->Regs->SPCRL,MCBSP_SPCRL_DXENA,ON);
    #endif
    
    #if 1
    	status = DMA_start(dmaMcBSPREFRxHandle);
    	if(status != CSL_SOK)
    	{
    	  printf("McBSP Dma Read start Failed!!\n");
    	  return(status);
    	}
    #endif
    #if 1
    	status = DMA_start(dmaMcBSPMICTxHandle);
    	if(status != CSL_SOK)
    	{
    	  printf("McBSP Dma Read start Failed!!\n");
    	  return(status);
    	}
    #endif
    
    	/* In the test case, the TX and RX should start before the srg starts. This is to avoid missing the first channel on mcbsp */
    	/* Enable MCBSP transmit and receive */
    	MCBSP_start(hMcbsp, MCBSP_RCV_START | MCBSP_XMIT_START, 0 );
    
    	/* Start Sample Rate Generator and Frame Sync */
    	MCBSP_start(hMcbsp,MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 0x300 );
    
      	/*Poll for the interrupt of tx_dma and rx_dma completions*/
    	//while( 0x3000 != CSL_SYSCTRL_REGS->DMAIFR );
    
    	CSL_SYSCTRL_REGS->DMAIFR = 0x3000;
    
    #if 0
    	//Compare the data here
        printf("\r\n Checking the data integrity\r\n");
        /* Check data to make sure transfer was successful */
        for(i=0; i<CSL_MCBSP_BUF_SIZE;i++) {
    		if (gmcbspDmaWriteBuf[i] != gmcbspDmaReadBuf[i]) {
    		   ++error;
    		   break;
    		}
      }
    
      /* We are done with MCBSP, so close it */
      //MCBSP_close(hMcbsp);
    
      if(error)
      {
    	return(CSL_MCBSP_TEST_FAILED);
      }
      else
      {
    	return(CSL_MCBSP_TEST_PASSED);
      }
    #endif
      	  return(CSL_MCBSP_TEST_PASSED);
    #endif
    }

    CSL_Status CSL_McBSPTest(void){
    #if (defined(CHIP_C5517)) //Uint16 i; //unsigned char error=0; CSL_Status status; //This is for the CSL status return
    /* Open MCBSP Port 0, this will return a MCBSP handle that will */ /* be used in calls to other CSl functions.                     */ hMcbsp = MCBSP_open(CSL_MCBSP_INST_0, &McbspObj,&status); if ( (hMcbsp == NULL) || (status != CSL_SOK) ) { printf("MCBSP_open() Failed \n"); } else { printf("MCBSP_open() Success \n"); }
    CSL_FINS(hMcbsp->sysRegs->EBSR,SYS_EBSR_SP0MODE,CSL_SYS_EBSR_SP0MODE_MODE3);
    #ifdef USE_MCBSP_TARGET // To configure the McBSP target through GPIO on S1 //   ==================================================================================================================== //   MCBSP Target Mode     | GPIO Data | Data          |  Frame Sync |   Clock                 | External Clock         | //                         | [9:6]     | Loop back     | Loop back   |  Loop back              | Connection             | //   ==================================================================================================================== //   MCBSP_TGT_NO_LB       |  0000     |  No loop back |  --         |  --                     |  --                    | //   MCBSP_TGT_LB_MODE0    |  0001     |  dx -> dr     |  fsr -> fsx |  clkr -> clkx           |  --                    | //   MCBSP_TGT_LB_MODE1    |  0011     |  dx -> dr     |  fsx -> fsr |  clkr -> clkx           |  --                    | //   MCBSP_TGT_LB_MODE2    |  0101     |  dx -> dr     |  fsr -> fsx |  clkx -> clkr           |  clkx -> clks          | //   MCBSP_TGT_LB_MODE3    |  0111     |  dx -> dr     |  fsx -> fsr |  clkx -> clkr           |  clkx -> clks          | //   MCBSP_TGT_LB_MODE4    |  1001     |  dx -> dr     |  fsr -> fsx |  External Clock -> clkx |  --                    | //   MCBSP_TGT_LB_MODE5    |  1011     |  dx -> dr     |  fsx -> fsr |  External Clock -> clkx |  --                    | //   MCBSP_TGT_LB_MODE6    |  1101     |  dx -> dr     |  fsr -> fsx |  External Clock -> clkr |  External Clock -> clks| //   MCBSP_TGT_LB_MODE7    |  1111     |  dx -> dr     |  fsx -> fsr |  External Clock -> clkr |  External Clock -> clks| //   ====================================================================================================================MCBSP_target_config(MCBSP_TGT_LB_MODE3);#endif
    #if 0 /* Initialize Dma */ status = DMA_init(); //前面I2S的时候已经初始化过DAM if (status != CSL_SOK) { printf("DMA_init Failed!\n"); }#endif
    #if 1    /* Configure the DMA channel for mcbsp transmit */#if ((defined(CHIP_C5505_C5515)) || (defined(CHIP_C5504_C5514)) || defined(CHIP_C5517) || (defined(CHIP_C5535) || defined(CHIP_C5545))) dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;#endif dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE; dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD; dmaConfig.trigger  = CSL_DMA_EVENT_TRIGGER; dmaConfig.dmaEvt   = CSL_DMA_EVT_MCBSP_TX; dmaConfig.dmaInt   = CSL_DMA_INTERRUPT_DISABLE; dmaConfig.chanDir  = CSL_DMA_WRITE; dmaConfig.trfType  = CSL_DMA_TRANSFER_IO_MEMORY; dmaConfig.dataLen  = (CSL_I2S_DMA_BUF_LEN*4*4); dmaConfig.srcAddr  = (Uint32)i2sDmaREFBuff;//i2sDmaMICBuff;// dmaConfig.destAddr = (Uint32)&(hMcbsp->Regs->DXRL);
    dmaMcBSPMICTxHandle = CSL_configDmaForMcbsp(&dmaObj, CSL_DMA_CHAN12); if(dmaMcBSPMICTxHandle == NULL) { printf("DMA Config for mcbsp DMA Write Failed!\n!"); //return(CSL_MCBSP_TEST_FAILED); }
    #endif
    #if 1    // Configure the DMA channel for mcbsp receive#if ((defined(CHIP_C5505_C5515)) || (defined(CHIP_C5504_C5514)) || (defined(CHIP_C5517)) || (defined(CHIP_C5535) || defined(CHIP_C5545))) dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;#endif dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE; dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;    dmaConfig.trigger  = CSL_DMA_EVENT_TRIGGER;    dmaConfig.dmaEvt   = CSL_DMA_EVT_MCBSP_RX; dmaConfig.dmaInt   = CSL_DMA_INTERRUPT_DISABLE; dmaConfig.chanDir  = CSL_DMA_READ; dmaConfig.trfType  = CSL_DMA_TRANSFER_IO_MEMORY; dmaConfig.dataLen  = (CSL_I2S_DMA_BUF_LEN*4*4); dmaConfig.srcAddr  = (Uint32)&(hMcbsp->Regs->DRRL); dmaConfig.destAddr = (Uint32)i2sDmaREFBuff;
    dmaMcBSPREFRxHandle = CSL_configDmaForMcbsp(&dmaObj,CSL_DMA_CHAN13); if(dmaMcBSPREFRxHandle == NULL) { printf("DMA Config for mcbsp DMA Read Failed!\n!"); return(CSL_MCBSP_TEST_FAILED); }#endif CSL_DMA3_REGS->DMACH0DSAL = 0x6010; //CSL_DMA3_REGS->DMACH0DSAU = 0x0000;
    CSL_DMA3_REGS->DMACH1DSAL = 0x6000; //CSL_DMA3_REGS->DMACH1DSAU = 0x0000;
      /* Write configuration structure values to MCBSP control register*/
    #ifdef USE_MCBSP_TARGET /** Input clock in Hz -- As our test cases will always run on QT we are always assigning the PHOENIX_QTCLK to this structure member*/ McBSPconfig.clkInput = PHOENIX_QTCLK;#else McBSPconfig.clkInput = 200000000;#endif /* Operating mode */ McBSPconfig.mcbsp_opmode = (CSL_McbspOpMode)CSL_MCBSP_OPMODE_NORMAL; //McBSPconfig.mcbsp_opmode = CSL_MCBSP_OPMODE_128CHANNEL; /**Word length selection Valid values - 8,12,16,20,24,32bits*/ McBSPconfig.wordLength = CSL_MCBSP_WORD16; /**Frame length selection Valid values - (1-128)*/ McBSPconfig.frameLength = CSL_MCBSP_FRMAELENGHT(1); /** single phase frame/double phase frame*/ McBSPconfig.phase = CSL_MCBSP_DUALPHASE; /** data delay*/ McBSPconfig.datadelay = CSL_MCBSP_DATADELAY0BIT; /** frame ignore flag */ McBSPconfig.frameignore = CSL_MCBSP_FRMAEIGNOREFALSE; //? /**Loopback mode enable/disable*/ McBSPconfig.loopBackmode = CSL_MCBSP_INTERNALLOOPBACK_DISABLE; /**Companding*/ McBSPconfig.companding = CSL_MCBSP_COFF_MSBFIRST; /**Rjust mode*/ McBSPconfig.rjust_mode = CSL_MCBSP_RJUST_RJZFMSB; /**Abis mode*/ McBSPconfig.abismode = CSL_MCBSP_ABIS_DISABLE; /**DXENA enable/disable*/ McBSPconfig.dxena = CSL_MCBSP_DXENA_DISABLE; /**CLKSTP */ McBSPconfig.clkstp = CSL_MCBSP_SPCRL_CLKSTP_DISABLE; /**CLKXP,CLKRP */ McBSPconfig.sample_polarity = CSL_MCBSP_DATASAMPLE_FALLING; /**FRAMESYNC */ McBSPconfig.fs_polarity = CSL_MCBSP_FS_ACTIVEHIGH; /** Clock Source */ McBSPconfig.clocksource = CSL_MCBSP_CLOCKSOURCE_SYSCLK; /** Interrupt Source */ McBSPconfig.intr_event = CSL_MCBSP_INTR_RDY;  //? /*sample rate(samples per sec) */ McBSPconfig.sample_rate = 48000; /*FSX pin source */ McBSPconfig.fsxpin_status = CSL_MCBSP_FSX_SRGOP;
    MCBSP_reset(hMcbsp); Mcbsp_Configure(hMcbsp, &McBSPconfig);#if 1//MCBSP_SET //重新设置mcbsp兼容I2S传输,48K、双通道、16bit CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_FSXM,ONE); //out CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_FSRM,ZERO); CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXM,ONE); CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKRM,ZERO); CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXP,RISINGEDGE); CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXP,FALLINGEDGE);
    CSL_FINST(hMcbsp->Regs->XCRU,MCBSP_XCRU_XPHASE,DUALPHASE); CSL_FINS(hMcbsp->Regs->XCRL,MCBSP_XCRL_XFRLEN1,McBSPconfig.wordLength);  //16bit CSL_FINS(hMcbsp->Regs->XCRU,MCBSP_XCRU_XFRLEN2,McBSPconfig.wordLength);  //16bit CSL_FINS(hMcbsp->Regs->XCRL,MCBSP_XCRL_XFRLEN1,McBSPconfig.frameLength); CSL_FINS(hMcbsp->Regs->XCRU,MCBSP_XCRU_XFRLEN2,McBSPconfig.frameLength);
    CSL_FINST(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_FSGM,ONE); CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_FPER,31);//McBSPconfig.wordLength CSL_FINS(hMcbsp->Regs->SRGRL,MCBSP_SRGRL_FWID,15); //((clkInput/(sample_rate*wordLength*2)) - 1) CSL_FINS(hMcbsp->Regs->SRGRL,MCBSP_SRGRL_CLKGDV,132);
    /*Not handled in CSl CLKSP and GSYNC of SRGRU */ CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_CLKSP,0); CSL_FINS(hMcbsp->Regs->SRGRU,MCBSP_SRGRU_GSYNC,0);
    /*Not handled bits in PCR by CSL */ CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKXM,ONE); CSL_FINST(hMcbsp->Regs->PCRL,MCBSP_PCRL_CLKRM,ZERO); CSL_FINST(hMcbsp->Regs->SPCRL,MCBSP_SPCRL_DXENA,ON);#endif
    #if 1 status = DMA_start(dmaMcBSPREFRxHandle); if(status != CSL_SOK) {   printf("McBSP Dma Read start Failed!!\n");   return(status); }#endif#if 1 status = DMA_start(dmaMcBSPMICTxHandle); if(status != CSL_SOK) {   printf("McBSP Dma Read start Failed!!\n");   return(status); }#endif
    /* In the test case, the TX and RX should start before the srg starts. This is to avoid missing the first channel on mcbsp */ /* Enable MCBSP transmit and receive */ MCBSP_start(hMcbsp, MCBSP_RCV_START | MCBSP_XMIT_START, 0 );
    /* Start Sample Rate Generator and Frame Sync */ MCBSP_start(hMcbsp,MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 0x300 );
      /*Poll for the interrupt of tx_dma and rx_dma completions*/ //while( 0x3000 != CSL_SYSCTRL_REGS->DMAIFR );
    CSL_SYSCTRL_REGS->DMAIFR = 0x3000;
    #if 0 //Compare the data here    printf("\r\n Checking the data integrity\r\n");    /* Check data to make sure transfer was successful */    for(i=0; i<CSL_MCBSP_BUF_SIZE;i++) { if (gmcbspDmaWriteBuf[i] != gmcbspDmaReadBuf[i]) {    ++error;    break; }  }
      /* We are done with MCBSP, so close it */  //MCBSP_close(hMcbsp);
      if(error)  { return(CSL_MCBSP_TEST_FAILED);  }  else  { return(CSL_MCBSP_TEST_PASSED);  }#endif    return(CSL_MCBSP_TEST_PASSED);#endif}

  • Dear Tony:

    DMA3直接地址编码地址如下:

    CSL_DMA3_REGS->DMACH0DSAL = 0x6010;

    CSL_DMA3_REGS->DMACH1DSAL = 0x6000;

    仿真查看寄存器如下(单步执行的时候只有下图红圈内的值在变化):

    请帮忙指导如何设置MCBSP的DRRL和DXRL 两组DAM同时轮询传输数据