问题描述:系统上电打开了看门狗定时器1(看门狗定时时间为0.1S)代码中有使能TM4C1294KCPDT的Hibernate模块,在一批次产品中,有部分产品会出现CPU反复重启。后面经过分析发现出问题CPU的HibernateEnableExpClk中使能时钟不成功,导致一直等待从而看门狗超时,所以必须加长看门狗的时间到接近2S,有问题的才可以启动;但是正常批次的产品看门狗时间定在0.1S可以正常启动,请问这是什么原因导致的呢?相关代码如下
//*****************************************************************************
//
//! Enables the Hibernation module for operation.
//!
//! \param ui32HibClk is the rate of the clock supplied to the Hibernation
//! module.
//!
//! This function enables the Hibernation module for operation. This function
//! should be called before any of the Hibernation module features are used.
//!
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! \return None.
//
//*****************************************************************************
void
HibernateEnableExpClk(uint32_t ui32HibClk)
{
int i;
//
// Turn on the clock enable bit.
//
HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;
while(!(HWREG(HIB_CTL) & HIB_CTL_CLK32EN))
{
i++;
if(i>=10000)
{
Consol_Printf("Clock Set Failed..\n");
}
}
//
// Wait for write complete following register load (above).
//
_HibernateWriteComplete();
}
//*****************************************************************************
//
//! \internal
//!
//! Polls until the write complete (WRC) bit in the hibernate control register
//! is set.
//!
//! \param None.
//!
//! The Hibernation module provides an indication when any write is completed.
//! This mechanism is used to pace writes to the module. This function merely
//! polls this bit and returns as soon as it is set. At this point, it is safe
//! to perform another write to the module.
//!
//! \return None.
//
//*****************************************************************************
#include "bsp_consol.h"
static void
_HibernateWriteComplete(void)
{
static int i = 0;
//
// Spin until the write complete bit is set.
//
while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
{
}
}