JTAG ID= 0x0b9a702f. This is a K2L device, version variant = 0
DEVSTAT= 0x0e000ee1. little endian, no boot or I2C slave boot, boot master is ARM core, PLL configuration implies the input clock for core is 122.88MHz
SmartReflex VID= 46, required core voltage= 0.995V.
Die ID= 0x0400500a, 0x0c00ea81, 0x00000000, 0x5f260020
DSP speed grade = 1200MHz, ARM speed grade= 1200MHz
Enable IRQ and FIQ.
Enable Exception handling...
Initialize main core clock = 100.00MHz/1x12 = 1200MHz
Initialize ARM clock = 100.00MHz/1x12 = 1200MHz
DDR3A initialization
Initialize DDR data rate = 100.000/1*16/4*4= 1600.0 MTS, bus width = 64 bits.
DDR PHY status PGSR0=0xb0000fff.
Queue Push/Pop test on descriptors with internal linking RAM
Queue 2006 push test through Queue Manage Registers
consumes   8348 cycles to push          512 descriptors, average  16 cycles
consumes   3764 cycles to push          256 descriptors, average  14 cycles
consumes   1866 cycles to push          128 descriptors, average  14 cycles
consumes    974 cycles to push           64 descriptors, average  15 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    305 cycles to push           16 descriptors, average  19 cycles
consumes    225 cycles to push            8 descriptors, average  28 cycles
consumes    162 cycles to push            4 descriptors, average  40 cycles
consumes    137 cycles to push            2 descriptors, average  68 cycles
consumes    114 cycles to push            1 descriptors, average 114 cycles
Queue 2006 push test through Queue Manage VBUSM Data Space
consumes   8425 cycles to push          512 descriptors, average  16 cycles
consumes   3757 cycles to push          256 descriptors, average  14 cycles
consumes   1817 cycles to push          128 descriptors, average  14 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    305 cycles to push           16 descriptors, average  19 cycles
consumes    228 cycles to push            8 descriptors, average  28 cycles
consumes    162 cycles to push            4 descriptors, average  40 cycles
consumes    126 cycles to push            2 descriptors, average  63 cycles
consumes    114 cycles to push            1 descriptors, average 114 cycles
Queue 2006 pop test through Queue Manage Registers
consumes  60238 cycles to pop           512 descriptors, average 117 cycles
consumes  30173 cycles to pop           256 descriptors, average 117 cycles
consumes  15141 cycles to pop           128 descriptors, average 118 cycles
consumes   7632 cycles to pop            64 descriptors, average 119 cycles
consumes   3849 cycles to pop            32 descriptors, average 120 cycles
consumes   1969 cycles to pop            16 descriptors, average 123 cycles
consumes   1044 cycles to pop             8 descriptors, average 130 cycles
consumes    570 cycles to pop             4 descriptors, average 142 cycles
consumes    328 cycles to pop             2 descriptors, average 164 cycles
consumes    215 cycles to pop             1 descriptors, average 215 cycles
Queue 2006 pop test through Queue Manage VBUSM Data Space
consumes  63413 cycles to pop           512 descriptors, average 123 cycles
consumes  31748 cycles to pop           256 descriptors, average 124 cycles
consumes  15891 cycles to pop           128 descriptors, average 124 cycles
consumes   8022 cycles to pop            64 descriptors, average 125 cycles
consumes   4053 cycles to pop            32 descriptors, average 126 cycles
consumes   2071 cycles to pop            16 descriptors, average 129 cycles
consumes   1102 cycles to pop             8 descriptors, average 137 cycles
consumes    594 cycles to pop             4 descriptors, average 148 cycles
consumes    346 cycles to pop             2 descriptors, average 173 cycles
consumes    222 cycles to pop             1 descriptors, average 222 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57308 cycles to pop           512 descriptors, average 111 cycles
consumes  28668 cycles to pop           256 descriptors, average 111 cycles
consumes  14385 cycles to pop           128 descriptors, average 112 cycles
consumes   7225 cycles to pop            64 descriptors, average 112 cycles
consumes   3673 cycles to pop            32 descriptors, average 114 cycles
consumes   1878 cycles to pop            16 descriptors, average 117 cycles
consumes    999 cycles to pop             8 descriptors, average 124 cycles
consumes    541 cycles to pop             4 descriptors, average 135 cycles
consumes    316 cycles to pop             2 descriptors, average 158 cycles
consumes    209 cycles to pop             1 descriptors, average 209 cycles
Queue 2006 push to pop delay test through Queue Manage Registers
consumes  93970 cycles to push and pop  512 descriptors, average 183 cycles
consumes  46998 cycles to push and pop  256 descriptors, average 183 cycles
consumes  23546 cycles to push and pop  128 descriptors, average 183 cycles
consumes  11819 cycles to push and pop   64 descriptors, average 184 cycles
consumes   5960 cycles to push and pop   32 descriptors, average 186 cycles
consumes   3032 cycles to push and pop   16 descriptors, average 189 cycles
consumes   1568 cycles to push and pop    8 descriptors, average 196 cycles
consumes    836 cycles to push and pop    4 descriptors, average 209 cycles
consumes    475 cycles to push and pop    2 descriptors, average 237 cycles
consumes    287 cycles to push and pop    1 descriptors, average 287 cycles
Queue 2006 push to pop delay test through Queue Manage VBUSM Data Space
consumes 104672 cycles to push and pop  512 descriptors, average 204 cycles
consumes  52336 cycles to push and pop  256 descriptors, average 204 cycles
consumes  26230 cycles to push and pop  128 descriptors, average 204 cycles
consumes  13160 cycles to push and pop   64 descriptors, average 205 cycles
consumes   6646 cycles to push and pop   32 descriptors, average 207 cycles
consumes   3368 cycles to push and pop   16 descriptors, average 210 cycles
consumes   1735 cycles to push and pop    8 descriptors, average 216 cycles
consumes    919 cycles to push and pop    4 descriptors, average 229 cycles
consumes    517 cycles to push and pop    2 descriptors, average 258 cycles
consumes    308 cycles to push and pop    1 descriptors, average 308 cycles
Queue Push/Pop test on descriptors with external linking RAM
Queue 2040 push test through Queue Manage Registers
consumes   9413 cycles to push          512 descriptors, average  18 cycles
consumes   3961 cycles to push          256 descriptors, average  15 cycles
consumes   1781 cycles to push          128 descriptors, average  13 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    305 cycles to push           16 descriptors, average  19 cycles
consumes    219 cycles to push            8 descriptors, average  27 cycles
consumes    154 cycles to push            4 descriptors, average  38 cycles
consumes    137 cycles to push            2 descriptors, average  68 cycles
consumes    114 cycles to push            1 descriptors, average 114 cycles
Queue 2040 push test through Queue Manage VBUSM Data Space
consumes   9583 cycles to push          512 descriptors, average  18 cycles
consumes   3980 cycles to push          256 descriptors, average  15 cycles
consumes   1813 cycles to push          128 descriptors, average  14 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    305 cycles to push           16 descriptors, average  19 cycles
consumes    215 cycles to push            8 descriptors, average  26 cycles
consumes    154 cycles to push            4 descriptors, average  38 cycles
consumes    137 cycles to push            2 descriptors, average  68 cycles
consumes    114 cycles to push            1 descriptors, average 114 cycles
Queue 2040 pop test through Queue Manage Registers
consumes  65651 cycles to pop           512 descriptors, average 128 cycles
consumes  32808 cycles to pop           256 descriptors, average 128 cycles
consumes  16451 cycles to pop           128 descriptors, average 128 cycles
consumes   8279 cycles to pop            64 descriptors, average 129 cycles
consumes   4176 cycles to pop            32 descriptors, average 130 cycles
consumes   2126 cycles to pop            16 descriptors, average 132 cycles
consumes   1124 cycles to pop             8 descriptors, average 140 cycles
consumes    590 cycles to pop             4 descriptors, average 147 cycles
consumes    339 cycles to pop             2 descriptors, average 169 cycles
consumes    217 cycles to pop             1 descriptors, average 217 cycles
Queue 2040 pop test through Queue Manage VBUSM Data Space
consumes  65612 cycles to pop           512 descriptors, average 128 cycles
consumes  32856 cycles to pop           256 descriptors, average 128 cycles
consumes  16463 cycles to pop           128 descriptors, average 128 cycles
consumes   8276 cycles to pop            64 descriptors, average 129 cycles
consumes   4193 cycles to pop            32 descriptors, average 131 cycles
consumes   2139 cycles to pop            16 descriptors, average 133 cycles
consumes   1124 cycles to pop             8 descriptors, average 140 cycles
consumes    609 cycles to pop             4 descriptors, average 152 cycles
consumes    345 cycles to pop             2 descriptors, average 172 cycles
consumes    224 cycles to pop             1 descriptors, average 224 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57167 cycles to pop           512 descriptors, average 111 cycles
consumes  28666 cycles to pop           256 descriptors, average 111 cycles
consumes  14379 cycles to pop           128 descriptors, average 112 cycles
consumes   7235 cycles to pop            64 descriptors, average 113 cycles
consumes   3650 cycles to pop            32 descriptors, average 114 cycles
consumes   1889 cycles to pop            16 descriptors, average 118 cycles
consumes    992 cycles to pop             8 descriptors, average 124 cycles
consumes    543 cycles to pop             4 descriptors, average 135 cycles
consumes    321 cycles to pop             2 descriptors, average 160 cycles
consumes    214 cycles to pop             1 descriptors, average 214 cycles
Queue 2040 push to pop delay test through Queue Manage Registers
consumes  93914 cycles to push and pop  512 descriptors, average 183 cycles
consumes  46965 cycles to push and pop  256 descriptors, average 183 cycles
consumes  23530 cycles to push and pop  128 descriptors, average 183 cycles
consumes  11815 cycles to push and pop   64 descriptors, average 184 cycles
consumes   5965 cycles to push and pop   32 descriptors, average 186 cycles
consumes   3032 cycles to push and pop   16 descriptors, average 189 cycles
consumes   1568 cycles to push and pop    8 descriptors, average 196 cycles
consumes    838 cycles to push and pop    4 descriptors, average 209 cycles
consumes    470 cycles to push and pop    2 descriptors, average 235 cycles
consumes    290 cycles to push and pop    1 descriptors, average 290 cycles
Queue 2040 push to pop delay test through Queue Manage VBUSM Data Space
consumes 108485 cycles to push and pop  512 descriptors, average 211 cycles
consumes  54251 cycles to push and pop  256 descriptors, average 211 cycles
consumes  27149 cycles to push and pop  128 descriptors, average 212 cycles
consumes  13622 cycles to push and pop   64 descriptors, average 212 cycles
consumes   6859 cycles to push and pop   32 descriptors, average 214 cycles
consumes   3485 cycles to push and pop   16 descriptors, average 217 cycles
consumes   1793 cycles to push and pop    8 descriptors, average 224 cycles
consumes    952 cycles to push and pop    4 descriptors, average 238 cycles
consumes    520 cycles to push and pop    2 descriptors, average 260 cycles
consumes    310 cycles to push and pop    1 descriptors, average 310 cycles

Queue pend interrupt test on descriptors with internal linking RAM
Queue 662 pending interrupt happens at 16061875
consumes    993 cycles between push queue 662 and pend interrupt
Queue pend interrupt test on descriptors with external linking RAM
Queue 662 pending interrupt happens at 16074802
consumes    576 cycles between push queue 662 and pend interrupt

descriptor Reclamation test in queue 2010
consumes   1445 cycles for one descriptor Reclamation
consumes   1392 cycles for one descriptor Reclamation
consumes   1135 cycles for one descriptor Reclamation
consumes   1133 cycles for one descriptor Reclamation
consumes   1240 cycles for one descriptor Reclamation
consumes   1460 cycles for one descriptor Reclamation
consumes    625 cycles for one descriptor Reclamation
consumes   1346 cycles for one descriptor Reclamation
consumes    713 cycles for one descriptor Reclamation
consumes   1450 cycles for one descriptor Reclamation

Queue Push/accumulation test with ACC48 firmware on INTD1
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16138909
consumes   3720 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16160768
consumes  12402 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16174128
consumes   3370 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16186618
consumes   3366 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16199551
consumes   3800 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16220142
consumes  11562 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16232903
consumes   3262 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16248346
consumes   6434 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16260584
consumes   3250 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16273279
consumes   3752 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16285726
consumes   3453 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16307416
consumes  12762 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16320105
consumes   3236 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16336953
consumes   7964 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16349115
consumes   3239 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16366858
consumes   8874 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16379402
consumes   3440 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16399480
consumes  11208 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 16412535
consumes   3399 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 16427658
consumes   6042 cycles to push and accumulate one descriptor with  low priority
test Packet DMA1 in QMSS
host Packet DMA test with 1 channels
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x c0dc280 to 0x84060000 with channel  0, consumes   859 cycles
Packet DMA achieves   13 MB/s when transfer    16 bytes from 0x c0de280 to 0x84060100 with channel  0, consumes  1455 cycles
Packet DMA achieves   35 MB/s when transfer    32 bytes from 0x c0e0280 to 0x84060200 with channel  0, consumes  1095 cycles
Packet DMA achieves   69 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84060300 with channel  0, consumes  1105 cycles
Packet DMA achieves  155 MB/s when transfer   128 bytes from 0x c0e4280 to 0x84060400 with channel  0, consumes   986 cycles
Packet DMA achieves  275 MB/s when transfer   256 bytes from 0x c0e6280 to 0x84060500 with channel  0, consumes  1115 cycles
Packet DMA achieves  563 MB/s when transfer   512 bytes from 0x c0e8280 to 0x840a0000 with channel  0, consumes  1091 cycles
Packet DMA achieves  757 MB/s when transfer  1024 bytes from 0x c0ea280 to 0x840a0800 with channel  0, consumes  1623 cycles
Packet DMA achieves  996 MB/s when transfer  2048 bytes from 0x c0ec280 to 0x840a1000 with channel  0, consumes  2465 cycles
Packet DMA achieves 1227 MB/s when transfer  4096 bytes from 0x c0ee280 to 0x84120000 with channel  0, consumes  4003 cycles
Packet DMA achieves 1398 MB/s when transfer  8192 bytes from 0x c0f0280 to 0x84124000 with channel  0, consumes  7028 cycles
Packet DMA achieves    7 MB/s when transfer     8 bytes from 0x84360000 to 0x c07c280 with channel  0, consumes  1255 cycles
Packet DMA achieves   12 MB/s when transfer    16 bytes from 0x84380000 to 0x c07c380 with channel  0, consumes  1523 cycles
Packet DMA achieves   30 MB/s when transfer    32 bytes from 0x843a0000 to 0x c07c480 with channel  0, consumes  1272 cycles
Packet DMA achieves   67 MB/s when transfer    64 bytes from 0x843c0000 to 0x c07c580 with channel  0, consumes  1142 cycles
Packet DMA achieves  120 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07c680 with channel  0, consumes  1276 cycles
Packet DMA achieves  265 MB/s when transfer   256 bytes from 0x84400000 to 0x c07c780 with channel  0, consumes  1156 cycles
Packet DMA achieves  449 MB/s when transfer   512 bytes from 0x84220000 to 0x c09c280 with channel  0, consumes  1368 cycles
Packet DMA achieves  699 MB/s when transfer  1024 bytes from 0x84240000 to 0x c09c680 with channel  0, consumes  1757 cycles
Packet DMA achieves  931 MB/s when transfer  2048 bytes from 0x84260000 to 0x c0bc280 with channel  0, consumes  2637 cycles
Packet DMA achieves 1116 MB/s when transfer  4096 bytes from 0x84280000 to 0x c0bd280 with channel  0, consumes  4402 cycles
Packet DMA achieves 1233 MB/s when transfer  8192 bytes from 0x842a0000 to 0x c0f2280 with channel  0, consumes  7972 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves   14 MB/s when transfer     8 bytes from 0x c03c090 to 0x8023cfec with channel  0, consumes   672 cycles
Packet DMA achieves   18 MB/s when transfer    16 bytes from 0x c03e0a0 to 0x8023effc with channel  0, consumes  1066 cycles
Packet DMA achieves   43 MB/s when transfer    32 bytes from 0x c0400b0 to 0x8024100c with channel  0, consumes   892 cycles
Packet DMA achieves   90 MB/s when transfer    64 bytes from 0x c0420c0 to 0x8024301c with channel  0, consumes   848 cycles
Packet DMA achieves  170 MB/s when transfer   128 bytes from 0x c0440d0 to 0x8024502c with channel  0, consumes   901 cycles
Packet DMA achieves  395 MB/s when transfer   256 bytes from 0x c0460e0 to 0x8024703c with channel  0, consumes   776 cycles
Packet DMA achieves  536 MB/s when transfer   512 bytes from 0x c0480f0 to 0x8024904c with channel  0, consumes  1146 cycles
Packet DMA achieves  798 MB/s when transfer  1024 bytes from 0x c04a100 to 0x8024b05c with channel  0, consumes  1538 cycles
Packet DMA achieves 1090 MB/s when transfer  2048 bytes from 0x c04c110 to 0x8024d06c with channel  0, consumes  2253 cycles
Packet DMA achieves 1303 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8024f07c with channel  0, consumes  3770 cycles
Packet DMA achieves 1435 MB/s when transfer  8192 bytes from 0x c050130 to 0x8025108c with channel  0, consumes  6847 cycles
Packet DMA achieves    9 MB/s when transfer     8 bytes from 0x802530a0 to 0x c05213c with channel  0, consumes  1010 cycles
Packet DMA achieves   19 MB/s when transfer    16 bytes from 0x802550b0 to 0x c05414c with channel  0, consumes   993 cycles
Packet DMA achieves   32 MB/s when transfer    32 bytes from 0x802570c0 to 0x c05615c with channel  0, consumes  1167 cycles
Packet DMA achieves   73 MB/s when transfer    64 bytes from 0x802590d0 to 0x c05816c with channel  0, consumes  1052 cycles
Packet DMA achieves  142 MB/s when transfer   128 bytes from 0x8025b0e0 to 0x c05a17c with channel  0, consumes  1077 cycles
Packet DMA achieves  248 MB/s when transfer   256 bytes from 0x8025d0f0 to 0x c05c18c with channel  0, consumes  1238 cycles
Packet DMA achieves  464 MB/s when transfer   512 bytes from 0x8025f100 to 0x c05e19c with channel  0, consumes  1323 cycles
Packet DMA achieves  639 MB/s when transfer  1024 bytes from 0x80261110 to 0x c0601ac with channel  0, consumes  1923 cycles
Packet DMA achieves  955 MB/s when transfer  2048 bytes from 0x80263120 to 0x c0621bc with channel  0, consumes  2573 cycles
Packet DMA achieves 1146 MB/s when transfer  4096 bytes from 0x80265130 to 0x c0641cc with channel  0, consumes  4289 cycles
Packet DMA achieves 1285 MB/s when transfer  8192 bytes from 0x80267140 to 0x c0661dc with channel  0, consumes  7646 cycles
host Packet DMA test with 2 channels
Packet DMA achieves   14 MB/s when transfer     8 bytes from 0x c0f6280 to 0x84060600 with channel  0, from 0x c0f6280 to 0x84060700 with channel  1, consumes  1335 cycles
Packet DMA achieves   28 MB/s when transfer    16 bytes from 0x c0fa280 to 0x84060800 with channel  0, from 0x c0fa280 to 0x84060900 with channel  1, consumes  1370 cycles
Packet DMA achieves   86 MB/s when transfer    32 bytes from 0x c0de280 to 0x84060a00 with channel  0, from 0x c0de280 to 0x84060b00 with channel  1, consumes   893 cycles
Packet DMA achieves  151 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84060c00 with channel  0, from 0x c0e2280 to 0x84060d00 with channel  1, consumes  1011 cycles
Packet DMA achieves  299 MB/s when transfer   128 bytes from 0x c0e6280 to 0x84060e00 with channel  0, from 0x c0e6280 to 0x84060f00 with channel  1, consumes  1025 cycles
Packet DMA achieves  534 MB/s when transfer   256 bytes from 0x c0ea280 to 0x84061000 with channel  0, from 0x c0ea280 to 0x84061100 with channel  1, consumes  1150 cycles
Packet DMA achieves  895 MB/s when transfer   512 bytes from 0x c0ee280 to 0x840a1800 with channel  0, from 0x c0ee280 to 0x840a2000 with channel  1, consumes  1372 cycles
Packet DMA achieves 1266 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x840a2800 with channel  0, from 0x c0f2280 to 0x840a3000 with channel  1, consumes  1941 cycles
Packet DMA achieves 1948 MB/s when transfer  2048 bytes from 0x c0f6280 to 0x840a3800 with channel  0, from 0x c0f6280 to 0x840a4000 with channel  1, consumes  2523 cycles
Packet DMA achieves 2434 MB/s when transfer  4096 bytes from 0x c0fa280 to 0x84128000 with channel  0, from 0x c0fa280 to 0x8412c000 with channel  1, consumes  4038 cycles
Packet DMA achieves 2776 MB/s when transfer  8192 bytes from 0x c0de280 to 0x84130000 with channel  0, from 0x c0de280 to 0x84134000 with channel  1, consumes  7080 cycles
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x842e0000 to 0x c07c880 with channel  0, from 0x842e0000 to 0x c07c980 with channel  1, consumes  1710 cycles
Packet DMA achieves   23 MB/s when transfer    16 bytes from 0x84320000 to 0x c07ca80 with channel  0, from 0x84320000 to 0x c07cb80 with channel  1, consumes  1622 cycles
Packet DMA achieves   76 MB/s when transfer    32 bytes from 0x84360000 to 0x c07cc80 with channel  0, from 0x84360000 to 0x c07cd80 with channel  1, consumes  1005 cycles
Packet DMA achieves  135 MB/s when transfer    64 bytes from 0x843a0000 to 0x c07ce80 with channel  0, from 0x843a0000 to 0x c07cf80 with channel  1, consumes  1137 cycles
Packet DMA achieves  273 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07d080 with channel  0, from 0x843e0000 to 0x c07d180 with channel  1, consumes  1124 cycles
Packet DMA achieves  413 MB/s when transfer   256 bytes from 0x84220000 to 0x c07d280 with channel  0, from 0x84220000 to 0x c07d380 with channel  1, consumes  1486 cycles
Packet DMA achieves  618 MB/s when transfer   512 bytes from 0x84260000 to 0x c09ca80 with channel  0, from 0x84260000 to 0x c09ce80 with channel  1, consumes  1986 cycles
Packet DMA achieves  845 MB/s when transfer  1024 bytes from 0x842a0000 to 0x c09d280 with channel  0, from 0x842a0000 to 0x c09d680 with channel  1, consumes  2907 cycles
Packet DMA achieves 1039 MB/s when transfer  2048 bytes from 0x842e0000 to 0x c0be280 with channel  0, from 0x842e0000 to 0x c0bf280 with channel  1, consumes  4729 cycles
Packet DMA achieves 1150 MB/s when transfer  4096 bytes from 0x84320000 to 0x c0c0280 with channel  0, from 0x84320000 to 0x c0c1280 with channel  1, consumes  8542 cycles
Packet DMA achieves 1212 MB/s when transfer  8192 bytes from 0x84360000 to 0x c0e0280 with channel  0, from 0x84360000 to 0x c0e2280 with channel  1, consumes 16218 cycles
monolithic Packet DMA test with 2 channels
Packet DMA achieves   18 MB/s when transfer     8 bytes from 0x c06a200 to 0x8026914c with channel  0, from 0x c06a200 to 0x8026b15c with channel  1, consumes  1054 cycles
Packet DMA achieves   34 MB/s when transfer    16 bytes from 0x c06e220 to 0x8026d16c with channel  0, from 0x c06e220 to 0x8026f17c with channel  1, consumes  1098 cycles
Packet DMA achieves   82 MB/s when transfer    32 bytes from 0x c072240 to 0x8027118c with channel  0, from 0x c072240 to 0x8027319c with channel  1, consumes   935 cycles
Packet DMA achieves  173 MB/s when transfer    64 bytes from 0x c076260 to 0x802751ac with channel  0, from 0x c076260 to 0x802771bc with channel  1, consumes   886 cycles
Packet DMA achieves  326 MB/s when transfer   128 bytes from 0x c07a280 to 0x802791cc with channel  0, from 0x c07a280 to 0x8027b1dc with channel  1, consumes   940 cycles
Packet DMA achieves  580 MB/s when transfer   256 bytes from 0x c03e0a0 to 0x8027d1ec with channel  0, from 0x c03e0a0 to 0x8027f1fc with channel  1, consumes  1058 cycles
Packet DMA achieves  962 MB/s when transfer   512 bytes from 0x c0420c0 to 0x8028120c with channel  0, from 0x c0420c0 to 0x8028321c with channel  1, consumes  1277 cycles
Packet DMA achieves 1454 MB/s when transfer  1024 bytes from 0x c0460e0 to 0x8028522c with channel  0, from 0x c0460e0 to 0x8028723c with channel  1, consumes  1690 cycles
Packet DMA achieves 1981 MB/s when transfer  2048 bytes from 0x c04a100 to 0x8028924c with channel  0, from 0x c04a100 to 0x8028b25c with channel  1, consumes  2480 cycles
Packet DMA achieves 2441 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8028d26c with channel  0, from 0x c04e120 to 0x8028f27c with channel  1, consumes  4026 cycles
Packet DMA achieves 2824 MB/s when transfer  8192 bytes from 0x c05213c to 0x8029128c with channel  0, from 0x c05213c to 0x8029329c with channel  1, consumes  6960 cycles
Packet DMA achieves   15 MB/s when transfer     8 bytes from 0x802972c0 to 0x c05414c with channel  0, from 0x802972c0 to 0x c05615c with channel  1, consumes  1202 cycles
Packet DMA achieves   31 MB/s when transfer    16 bytes from 0x8029b2e0 to 0x c05816c with channel  0, from 0x8029b2e0 to 0x c05a17c with channel  1, consumes  1238 cycles
Packet DMA achieves   66 MB/s when transfer    32 bytes from 0x8029f300 to 0x c05c18c with channel  0, from 0x8029f300 to 0x c05e19c with channel  1, consumes  1160 cycles
Packet DMA achieves  132 MB/s when transfer    64 bytes from 0x802a3320 to 0x c0601ac with channel  0, from 0x802a3320 to 0x c0621bc with channel  1, consumes  1163 cycles
Packet DMA achieves  279 MB/s when transfer   128 bytes from 0x802a7340 to 0x c0641cc with channel  0, from 0x802a7340 to 0x c0661dc with channel  1, consumes  1098 cycles
Packet DMA achieves  470 MB/s when transfer   256 bytes from 0x802ab360 to 0x c0681ec with channel  0, from 0x802ab360 to 0x c06a1fc with channel  1, consumes  1305 cycles
Packet DMA achieves  898 MB/s when transfer   512 bytes from 0x802af380 to 0x c06c20c with channel  0, from 0x802af380 to 0x c06e21c with channel  1, consumes  1367 cycles
Packet DMA achieves 1229 MB/s when transfer  1024 bytes from 0x802b33a0 to 0x c07022c with channel  0, from 0x802b33a0 to 0x c07223c with channel  1, consumes  1999 cycles
Packet DMA achieves 1829 MB/s when transfer  2048 bytes from 0x802b73c0 to 0x c07424c with channel  0, from 0x802b73c0 to 0x c07625c with channel  1, consumes  2686 cycles
Packet DMA achieves 2202 MB/s when transfer  4096 bytes from 0x802bb3e0 to 0x c07826c with channel  0, from 0x802bb3e0 to 0x c07a27c with channel  1, consumes  4463 cycles
Packet DMA achieves 2425 MB/s when transfer  8192 bytes from 0x802bf400 to 0x c03c08c with channel  0, from 0x802bf400 to 0x c03e09c with channel  1, consumes  8107 cycles
host Packet DMA test with 4 channels
Packet DMA achieves   40 MB/s when transfer     8 bytes from 0x c0ea280 to 0x84061200 with channel  0, from 0x c0ea280 to 0x84061300 with channel  1, from 0x c0ea280 to 0x84061400 with channel  2, from 0x c0ea280 to 0x84061500 with channel  3, consumes   939 cycles
Packet DMA achieves   80 MB/s when transfer    16 bytes from 0x c0f2280 to 0x84061600 with channel  0, from 0x c0f2280 to 0x84061700 with channel  1, from 0x c0f2280 to 0x84061800 with channel  2, from 0x c0f2280 to 0x84061900 with channel  3, consumes   953 cycles
Packet DMA achieves  161 MB/s when transfer    32 bytes from 0x c0fa280 to 0x84061a00 with channel  0, from 0x c0fa280 to 0x84061b00 with channel  1, from 0x c0fa280 to 0x84061c00 with channel  2, from 0x c0fa280 to 0x84061d00 with channel  3, consumes   950 cycles
Packet DMA achieves  320 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84061e00 with channel  0, from 0x c0e2280 to 0x84061f00 with channel  1, from 0x c0e2280 to 0x84062000 with channel  2, from 0x c0e2280 to 0x84062100 with channel  3, consumes   958 cycles
Packet DMA achieves  577 MB/s when transfer   128 bytes from 0x c0ea280 to 0x84062200 with channel  0, from 0x c0ea280 to 0x84062300 with channel  1, from 0x c0ea280 to 0x84062400 with channel  2, from 0x c0ea280 to 0x84062500 with channel  3, consumes  1063 cycles
Packet DMA achieves  948 MB/s when transfer   256 bytes from 0x c0f2280 to 0x84062600 with channel  0, from 0x c0f2280 to 0x84062700 with channel  1, from 0x c0f2280 to 0x84062800 with channel  2, from 0x c0f2280 to 0x84062900 with channel  3, consumes  1296 cycles
Packet DMA achieves 1680 MB/s when transfer   512 bytes from 0x c0fa280 to 0x840a4800 with channel  0, from 0x c0fa280 to 0x840a5000 with channel  1, from 0x c0fa280 to 0x840a5800 with channel  2, from 0x c0fa280 to 0x840a6000 with channel  3, consumes  1462 cycles
Packet DMA achieves 2562 MB/s when transfer  1024 bytes from 0x c0e2280 to 0x840a6800 with channel  0, from 0x c0e2280 to 0x840a7000 with channel  1, from 0x c0e2280 to 0x840a7800 with channel  2, from 0x c0e2280 to 0x840a8000 with channel  3, consumes  1918 cycles
Packet DMA achieves 3718 MB/s when transfer  2048 bytes from 0x c0ea280 to 0x840a8800 with channel  0, from 0x c0ea280 to 0x840a9000 with channel  1, from 0x c0ea280 to 0x840a9800 with channel  2, from 0x c0ea280 to 0x840aa000 with channel  3, consumes  2644 cycles
Packet DMA achieves 4645 MB/s when transfer  4096 bytes from 0x c0f2280 to 0x84138000 with channel  0, from 0x c0f2280 to 0x8413c000 with channel  1, from 0x c0f2280 to 0x84140000 with channel  2, from 0x c0f2280 to 0x84144000 with channel  3, consumes  4232 cycles
Packet DMA achieves 5400 MB/s when transfer  8192 bytes from 0x c0fa280 to 0x84148000 with channel  0, from 0x c0fa280 to 0x8414c000 with channel  1, from 0x c0fa280 to 0x84150000 with channel  2, from 0x c0fa280 to 0x84154000 with channel  3, consumes  7281 cycles
Packet DMA achieves   34 MB/s when transfer     8 bytes from 0x843e0000 to 0x c07d480 with channel  0, from 0x843e0000 to 0x c07d580 with channel  1, from 0x843e0000 to 0x c07d680 with channel  2, from 0x843e0000 to 0x c07d780 with channel  3, consumes  1098 cycles
Packet DMA achieves   72 MB/s when transfer    16 bytes from 0x84260000 to 0x c07d880 with channel  0, from 0x84260000 to 0x c07d980 with channel  1, from 0x84260000 to 0x c07da80 with channel  2, from 0x84260000 to 0x c07db80 with channel  3, consumes  1060 cycles
Packet DMA achieves  144 MB/s when transfer    32 bytes from 0x842e0000 to 0x c07dc80 with channel  0, from 0x842e0000 to 0x c07dd80 with channel  1, from 0x842e0000 to 0x c07de80 with channel  2, from 0x842e0000 to 0x c07df80 with channel  3, consumes  1066 cycles
Packet DMA achieves  261 MB/s when transfer    64 bytes from 0x84360000 to 0x c07e080 with channel  0, from 0x84360000 to 0x c07e180 with channel  1, from 0x84360000 to 0x c07e280 with channel  2, from 0x84360000 to 0x c07e380 with channel  3, consumes  1173 cycles
Packet DMA achieves  506 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07e480 with channel  0, from 0x843e0000 to 0x c07e580 with channel  1, from 0x843e0000 to 0x c07e680 with channel  2, from 0x843e0000 to 0x c07e780 with channel  3, consumes  1213 cycles
Packet DMA achieves  730 MB/s when transfer   256 bytes from 0x84260000 to 0x c07e880 with channel  0, from 0x84260000 to 0x c07e980 with channel  1, from 0x84260000 to 0x c07ea80 with channel  2, from 0x84260000 to 0x c07eb80 with channel  3, consumes  1682 cycles
Packet DMA achieves  970 MB/s when transfer   512 bytes from 0x842e0000 to 0x c09da80 with channel  0, from 0x842e0000 to 0x c09de80 with channel  1, from 0x842e0000 to 0x c09e280 with channel  2, from 0x842e0000 to 0x c09e680 with channel  3, consumes  2533 cycles
Packet DMA achieves 1136 MB/s when transfer  1024 bytes from 0x84360000 to 0x c09ea80 with channel  0, from 0x84360000 to 0x c09ee80 with channel  1, from 0x84360000 to 0x c09f280 with channel  2, from 0x84360000 to 0x c09f680 with channel  3, consumes  4324 cycles
Packet DMA achieves 1262 MB/s when transfer  2048 bytes from 0x843e0000 to 0x c0c2280 with channel  0, from 0x843e0000 to 0x c0c3280 with channel  1, from 0x843e0000 to 0x c0c4280 with channel  2, from 0x843e0000 to 0x c0c5280 with channel  3, consumes  7786 cycles
Packet DMA achieves 1438 MB/s when transfer  4096 bytes from 0x84260000 to 0x c0c6280 with channel  0, from 0x84260000 to 0x c0c7280 with channel  1, from 0x84260000 to 0x c0c8280 with channel  2, from 0x84260000 to 0x c0c9280 with channel  3, consumes 13670 cycles
Packet DMA achieves 1301 MB/s when transfer  8192 bytes from 0x842e0000 to 0x c0dc280 with channel  0, from 0x842e0000 to 0x c0de280 with channel  1, from 0x842e0000 to 0x c0e0280 with channel  2, from 0x842e0000 to 0x c0e2280 with channel  3, consumes 30217 cycles
monolithic Packet DMA test with 4 channels
Packet DMA achieves   44 MB/s when transfer     8 bytes from 0x c0460e0 to 0x802c140c with channel  0, from 0x c0460e0 to 0x802c341c with channel  1, from 0x c0460e0 to 0x802c542c with channel  2, from 0x c0460e0 to 0x802c743c with channel  3, consumes   863 cycles
Packet DMA achieves   91 MB/s when transfer    16 bytes from 0x c04e120 to 0x802c944c with channel  0, from 0x c04e120 to 0x802cb45c with channel  1, from 0x c04e120 to 0x802cd46c with channel  2, from 0x c04e120 to 0x802cf47c with channel  3, consumes   840 cycles
Packet DMA achieves  179 MB/s when transfer    32 bytes from 0x c05615c to 0x802d148c with channel  0, from 0x c05615c to 0x802d349c with channel  1, from 0x c05615c to 0x802d54ac with channel  2, from 0x c05615c to 0x802d74bc with channel  3, consumes   856 cycles
Packet DMA achieves  361 MB/s when transfer    64 bytes from 0x c05e19c to 0x802d94cc with channel  0, from 0x c05e19c to 0x802db4dc with channel  1, from 0x c05e19c to 0x802dd4ec with channel  2, from 0x c05e19c to 0x802df4fc with channel  3, consumes   850 cycles
Packet DMA achieves  711 MB/s when transfer   128 bytes from 0x c0661dc to 0x802e150c with channel  0, from 0x c0661dc to 0x802e351c with channel  1, from 0x c0661dc to 0x802e552c with channel  2, from 0x c0661dc to 0x802e753c with channel  3, consumes   863 cycles
Packet DMA achieves 1129 MB/s when transfer   256 bytes from 0x c06e21c to 0x802e954c with channel  0, from 0x c06e21c to 0x802eb55c with channel  1, from 0x c06e21c to 0x802ed56c with channel  2, from 0x c06e21c to 0x802ef57c with channel  3, consumes  1088 cycles
Packet DMA achieves 1905 MB/s when transfer   512 bytes from 0x c07625c to 0x802f158c with channel  0, from 0x c07625c to 0x802f359c with channel  1, from 0x c07625c to 0x802f55ac with channel  2, from 0x c07625c to 0x802f75bc with channel  3, consumes  1290 cycles
Packet DMA achieves 2867 MB/s when transfer  1024 bytes from 0x c03e09c to 0x802f95cc with channel  0, from 0x c03e09c to 0x802fb5dc with channel  1, from 0x c03e09c to 0x802fd5ec with channel  2, from 0x c03e09c to 0x802ff5fc with channel  3, consumes  1714 cycles
Packet DMA achieves 4055 MB/s when transfer  2048 bytes from 0x c0460e0 to 0x8030160c with channel  0, from 0x c0460e0 to 0x8030361c with channel  1, from 0x c0460e0 to 0x8030562c with channel  2, from 0x c0460e0 to 0x8030763c with channel  3, consumes  2424 cycles
Packet DMA achieves 4906 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8030964c with channel  0, from 0x c04e120 to 0x8030b65c with channel  1, from 0x c04e120 to 0x8030d66c with channel  2, from 0x c04e120 to 0x8030f67c with channel  3, consumes  4007 cycles
Packet DMA achieves 5574 MB/s when transfer  8192 bytes from 0x c05615c to 0x8031168c with channel  0, from 0x c05615c to 0x8031369c with channel  1, from 0x c05615c to 0x803156ac with channel  2, from 0x c05615c to 0x803176bc with channel  3, consumes  7054 cycles
Packet DMA achieves   39 MB/s when transfer     8 bytes from 0x8031f700 to 0x c05816c with channel  0, from 0x8031f700 to 0x c05a17c with channel  1, from 0x8031f700 to 0x c05c18c with channel  2, from 0x8031f700 to 0x c05e19c with channel  3, consumes   967 cycles
Packet DMA achieves   78 MB/s when transfer    16 bytes from 0x80327740 to 0x c0601ac with channel  0, from 0x80327740 to 0x c0641cc with channel  1, from 0x80327740 to 0x c0621bc with channel  2, from 0x80327740 to 0x c0661dc with channel  3, consumes   974 cycles
Packet DMA achieves  158 MB/s when transfer    32 bytes from 0x8032f780 to 0x c06c20c with channel  0, from 0x8032f780 to 0x c0681ec with channel  1, from 0x8032f780 to 0x c06a1fc with channel  2, from 0x8032f780 to 0x c06e21c with channel  3, consumes   970 cycles
Packet DMA achieves  292 MB/s when transfer    64 bytes from 0x803377c0 to 0x c07424c with channel  0, from 0x803377c0 to 0x c07022c with channel  1, from 0x803377c0 to 0x c07223c with channel  2, from 0x803377c0 to 0x c07625c with channel  3, consumes  1052 cycles
Packet DMA achieves  638 MB/s when transfer   128 bytes from 0x8033f800 to 0x c03c08c with channel  0, from 0x8033f800 to 0x c07826c with channel  1, from 0x8033f800 to 0x c07a27c with channel  2, from 0x8033f800 to 0x c03e09c with channel  3, consumes   963 cycles
Packet DMA achieves 1060 MB/s when transfer   256 bytes from 0x80347840 to 0x c0440cc with channel  0, from 0x80347840 to 0x c0400ac with channel  1, from 0x80347840 to 0x c0420bc with channel  2, from 0x80347840 to 0x c0460dc with channel  3, consumes  1159 cycles
Packet DMA achieves 1905 MB/s when transfer   512 bytes from 0x8034f880 to 0x c04c10c with channel  0, from 0x8034f880 to 0x c0480ec with channel  1, from 0x8034f880 to 0x c04a0fc with channel  2, from 0x8034f880 to 0x c04e11c with channel  3, consumes  1290 cycles
Packet DMA achieves 2742 MB/s when transfer  1024 bytes from 0x803578c0 to 0x c05414c with channel  0, from 0x803578c0 to 0x c05012c with channel  1, from 0x803578c0 to 0x c05615c with channel  2, from 0x803578c0 to 0x c05213c with channel  3, consumes  1792 cycles
Packet DMA achieves 3574 MB/s when transfer  2048 bytes from 0x8035f900 to 0x c05816c with channel  0, from 0x8035f900 to 0x c05a17c with channel  1, from 0x8035f900 to 0x c05e19c with channel  2, from 0x8035f900 to 0x c05c18c with channel  3, consumes  2750 cycles
Packet DMA achieves 4238 MB/s when transfer  4096 bytes from 0x80367940 to 0x c0601ac with channel  0, from 0x80367940 to 0x c0641cc with channel  1, from 0x80367940 to 0x c0661dc with channel  2, from 0x80367940 to 0x c0621bc with channel  3, consumes  4639 cycles
Packet DMA achieves 4402 MB/s when transfer  8192 bytes from 0x8036f980 to 0x c06c20c with channel  0, from 0x8036f980 to 0x c0681ec with channel  1, from 0x8036f980 to 0x c06a1fc with channel  2, from 0x8036f980 to 0x c06e21c with channel  3, consumes  8932 cycles
test Packet DMA in PA
host Packet DMA test with 1 channels
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x c0e4280 to 0x84062a00 with channel  0, consumes  1083 cycles
Packet DMA achieves   19 MB/s when transfer    16 bytes from 0x c0e6280 to 0x84062b00 with channel  0, consumes  1004 cycles
Packet DMA achieves   23 MB/s when transfer    32 bytes from 0x c0e8280 to 0x84062c00 with channel  0, consumes  1605 cycles
Packet DMA achieves   62 MB/s when transfer    64 bytes from 0x c0ea280 to 0x84062d00 with channel  0, consumes  1222 cycles
Packet DMA achieves  124 MB/s when transfer   128 bytes from 0x c0ec280 to 0x84062e00 with channel  0, consumes  1231 cycles
Packet DMA achieves  227 MB/s when transfer   256 bytes from 0x c0ee280 to 0x84062f00 with channel  0, consumes  1349 cycles
Packet DMA achieves  389 MB/s when transfer   512 bytes from 0x c0f0280 to 0x840aa800 with channel  0, consumes  1577 cycles
Packet DMA achieves  585 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x840ab000 with channel  0, consumes  2097 cycles
Packet DMA achieves  834 MB/s when transfer  2048 bytes from 0x c0f4280 to 0x840ab800 with channel  0, consumes  2945 cycles
Packet DMA achieves 1061 MB/s when transfer  4096 bytes from 0x c0f6280 to 0x84158000 with channel  0, consumes  4632 cycles
Packet DMA achieves 1202 MB/s when transfer  8192 bytes from 0x c0f8280 to 0x8415c000 with channel  0, consumes  8175 cycles
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x84300000 to 0x c07ec80 with channel  0, consumes  1089 cycles
Packet DMA achieves   11 MB/s when transfer    16 bytes from 0x84320000 to 0x c07ed80 with channel  0, consumes  1650 cycles
Packet DMA achieves   25 MB/s when transfer    32 bytes from 0x84340000 to 0x c07ee80 with channel  0, consumes  1481 cycles
Packet DMA achieves   58 MB/s when transfer    64 bytes from 0x84360000 to 0x c07ef80 with channel  0, consumes  1314 cycles
Packet DMA achieves  111 MB/s when transfer   128 bytes from 0x84380000 to 0x c07f080 with channel  0, consumes  1379 cycles
Packet DMA achieves  209 MB/s when transfer   256 bytes from 0x843a0000 to 0x c07f180 with channel  0, consumes  1469 cycles
Packet DMA achieves  377 MB/s when transfer   512 bytes from 0x843c0000 to 0x c09fa80 with channel  0, consumes  1629 cycles
Packet DMA achieves  591 MB/s when transfer  1024 bytes from 0x843e0000 to 0x c09fe80 with channel  0, consumes  2077 cycles
Packet DMA achieves  837 MB/s when transfer  2048 bytes from 0x84400000 to 0x c0ca280 with channel  0, consumes  2936 cycles
Packet DMA achieves 1064 MB/s when transfer  4096 bytes from 0x84220000 to 0x c0cb280 with channel  0, consumes  4617 cycles
Packet DMA achieves 1201 MB/s when transfer  8192 bytes from 0x84240000 to 0x c0fa280 with channel  0, consumes  8185 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x c07424c to 0x8037198c with channel  0, consumes  1177 cycles
Packet DMA achieves   16 MB/s when transfer    16 bytes from 0x c07022c to 0x8037399c with channel  0, consumes  1149 cycles
Packet DMA achieves   35 MB/s when transfer    32 bytes from 0x c07223c to 0x803759ac with channel  0, consumes  1093 cycles
Packet DMA achieves   73 MB/s when transfer    64 bytes from 0x c07625c to 0x803779bc with channel  0, consumes  1046 cycles
Packet DMA achieves  147 MB/s when transfer   128 bytes from 0x c03c08c to 0x803799cc with channel  0, consumes  1038 cycles
Packet DMA achieves  254 MB/s when transfer   256 bytes from 0x c07826c to 0x8037b9dc with channel  0, consumes  1209 cycles
Packet DMA achieves  428 MB/s when transfer   512 bytes from 0x c07a27c to 0x8037d9ec with channel  0, consumes  1435 cycles
Packet DMA achieves  623 MB/s when transfer  1024 bytes from 0x c03e09c to 0x8037f9fc with channel  0, consumes  1970 cycles
Packet DMA achieves  918 MB/s when transfer  2048 bytes from 0x c0440cc to 0x80381a0c with channel  0, consumes  2676 cycles
Packet DMA achieves 1118 MB/s when transfer  4096 bytes from 0x c0400ac to 0x80383a1c with channel  0, consumes  4394 cycles
Packet DMA achieves 1233 MB/s when transfer  8192 bytes from 0x c0420bc to 0x80385a2c with channel  0, consumes  7970 cycles
Packet DMA achieves    6 MB/s when transfer     8 bytes from 0x80387a40 to 0x c0460dc with channel  0, consumes  1542 cycles
Packet DMA achieves   19 MB/s when transfer    16 bytes from 0x80389a50 to 0x c04c10c with channel  0, consumes   969 cycles
Packet DMA achieves   33 MB/s when transfer    32 bytes from 0x8038ba60 to 0x c0480ec with channel  0, consumes  1133 cycles
Packet DMA achieves   61 MB/s when transfer    64 bytes from 0x8038da70 to 0x c04a0fc with channel  0, consumes  1240 cycles
Packet DMA achieves  121 MB/s when transfer   128 bytes from 0x8038fa80 to 0x c04e11c with channel  0, consumes  1268 cycles
Packet DMA achieves  225 MB/s when transfer   256 bytes from 0x80391a90 to 0x c05414c with channel  0, consumes  1365 cycles
Packet DMA achieves  392 MB/s when transfer   512 bytes from 0x80393aa0 to 0x c05012c with channel  0, consumes  1565 cycles
Packet DMA achieves  575 MB/s when transfer  1024 bytes from 0x80395ab0 to 0x c05615c with channel  0, consumes  2134 cycles
Packet DMA achieves  871 MB/s when transfer  2048 bytes from 0x80397ac0 to 0x c05213c with channel  0, consumes  2821 cycles
Packet DMA achieves 1090 MB/s when transfer  4096 bytes from 0x80399ad0 to 0x c05816c with channel  0, consumes  4509 cycles
Packet DMA achieves 1216 MB/s when transfer  8192 bytes from 0x8039bae0 to 0x c05a17c with channel  0, consumes  8084 cycles
Test complete
