/**
* File: csl_wiz8_sb_refclk312p5MHz_20bit_12p5Gbps_sr1
*
* Version: SnowBushRel_PHY_A_20.1_20140314 - VREG Increas, Move CND to end of config and enable Cal Rate3, set att_boost register to 0xF
*
* Brief:
*  Autogenerated SERDES CONFIG Functions.
*
*  It contains the various enumerations, structure definitions and function
*  declarations
*
*  
*  ============================================================================
*  (C) Copyright 2014, Texas Instruments, Inc.
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef CSL_WIZ8_SB_REFCLK312P5MHZ_20BIT_12P5GBPS_SR1_C
#define CSL_WIZ8_SB_REFCLK312P5MHZ_20BIT_12P5GBPS_SR1_C

#include <stdint.h>
#include <ti/csl/soc.h>
#include <ti/csl/csl.h>

void csl_wiz8_sb_refclk312p5MHz_20bit_12p5Gbps_sr1(uint32_t base_addr)
  {
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0000),15, 8, (uint32_t)0x18);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0000),31,24, (uint32_t)0x00);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060), 7, 0, (uint32_t)0x48);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),15, 8, (uint32_t)0xe4);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),23,16, (uint32_t)0x14);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),15, 8, (uint32_t)0xc7);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),23,16, (uint32_t)0xc3);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0078),15, 8, (uint32_t)0xc0);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0200),15, 8, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0204), 7, 0, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0204),31,24, (uint32_t)0x7e);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0208), 7, 0, (uint32_t)0x24);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0208),15, 8, (uint32_t)0x10);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x020c),31,24, (uint32_t)0x02);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0210),31,24, (uint32_t)0x1b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0214), 7, 0, (uint32_t)0x1c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0214),15, 8, (uint32_t)0x6a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0218), 7, 0, (uint32_t)0x84);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0218),23,16, (uint32_t)0x90);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0218),31,24, (uint32_t)0x7a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x022c),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x024c),23,16, (uint32_t)0x8f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0280), 7, 0, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0280),23,16, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0284), 7, 0, (uint32_t)0x95);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0284),23,16, (uint32_t)0x0f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0284),31,24, (uint32_t)0x3b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x028c),15, 8, (uint32_t)0x59);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0400),15, 8, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0404), 7, 0, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0404),31,24, (uint32_t)0x7e);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0408), 7, 0, (uint32_t)0x24);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0408),15, 8, (uint32_t)0x10);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x040c),31,24, (uint32_t)0x02);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0410),31,24, (uint32_t)0x1b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0414), 7, 0, (uint32_t)0x1c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0414),15, 8, (uint32_t)0x6a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0418), 7, 0, (uint32_t)0x84);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0418),23,16, (uint32_t)0x90);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0418),31,24, (uint32_t)0x7a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x042c),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x044c),23,16, (uint32_t)0x8f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0480), 7, 0, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0480),23,16, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0484), 7, 0, (uint32_t)0x95);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0484),23,16, (uint32_t)0x0f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0484),31,24, (uint32_t)0x3b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x048c),15, 8, (uint32_t)0x59);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0600),15, 8, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0604), 7, 0, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0604),31,24, (uint32_t)0x7e);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0608), 7, 0, (uint32_t)0x24);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0608),15, 8, (uint32_t)0x10);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x060c),31,24, (uint32_t)0x02);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0610),31,24, (uint32_t)0x1b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0614), 7, 0, (uint32_t)0x1c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0614),15, 8, (uint32_t)0x6a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0618), 7, 0, (uint32_t)0x84);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0618),23,16, (uint32_t)0x90);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0618),31,24, (uint32_t)0x7a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x062c),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x064c),23,16, (uint32_t)0x8f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0680), 7, 0, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0680),23,16, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0684), 7, 0, (uint32_t)0x95);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0684),23,16, (uint32_t)0x0f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0684),31,24, (uint32_t)0x3b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x068c),15, 8, (uint32_t)0x59);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0800),15, 8, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0804), 7, 0, (uint32_t)0x80);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0804),31,24, (uint32_t)0x7e);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0808), 7, 0, (uint32_t)0x24);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0808),15, 8, (uint32_t)0x10);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x080c),31,24, (uint32_t)0x02);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0810),31,24, (uint32_t)0x1b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0814), 7, 0, (uint32_t)0x1c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0814),15, 8, (uint32_t)0x6a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0818), 7, 0, (uint32_t)0x84);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0818),23,16, (uint32_t)0x90);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0818),31,24, (uint32_t)0x7a);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x082c),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x084c),23,16, (uint32_t)0x8f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0880), 7, 0, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0880),23,16, (uint32_t)0x46);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0884), 7, 0, (uint32_t)0x95);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0884),23,16, (uint32_t)0x0f);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0884),31,24, (uint32_t)0x3b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x088c),15, 8, (uint32_t)0x59);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a00),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a08),23,16, (uint32_t)0xd2);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a08),31,24, (uint32_t)0x34);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a0c),15, 8, (uint32_t)0x05);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a10),15, 8, (uint32_t)0x02);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a30),15, 8, (uint32_t)0x4d);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a30),23,16, (uint32_t)0x4d);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a84),15, 8, (uint32_t)0x06);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a90), 7, 0, (uint32_t)0x01);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a90),15, 8, (uint32_t)0x60);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a94),31,24, (uint32_t)0x10);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0aa0),31,24, (uint32_t)0x81);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0abc),31,24, (uint32_t)0xff);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0ac0), 7, 0, (uint32_t)0x8b);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0000), 7, 0, (uint32_t)0x03);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0a00), 7, 0, (uint32_t)0x5f);
  }
#endif
