JTAG ID= 0x1b98102f. This is a K2H/K2K device, version variant = 1
DEVSTAT= 0x02060ee1. little endian, no boot or I2C slave boot, boot master is ARM core, PLL configuration implies the input clock for core is 122.88MHz
SmartReflex VID= 46, required core voltage= 0.995V.
Die ID= 0x0c011004, 0x04010235, 0x00000000, 0x60ba0001
DSP speed grade = 1200MHz, ARM speed grade= 1200MHz
Enable IRQ and FIQ.
Enable Exception handling...
Initialize main core clock = 122.88MHz/4x39 = 1198MHz
Initialize ARM clock = 125.00MHz/5x48 = 1200MHz
DDR3A initialization
Initialize DDR data rate = 100.000/1*20/6*4= 1333.3 MTS, bus width = 64 bits.
Queue Push/Pop test on descriptors with internal linking RAM
Queue 2006 push test through Queue Manage Registers
consumes   8321 cycles to push          512 descriptors, average  16 cycles
consumes   3759 cycles to push          256 descriptors, average  14 cycles
consumes   1868 cycles to push          128 descriptors, average  14 cycles
consumes    975 cycles to push           64 descriptors, average  15 cycles
consumes    522 cycles to push           32 descriptors, average  16 cycles
consumes    321 cycles to push           16 descriptors, average  20 cycles
consumes    231 cycles to push            8 descriptors, average  28 cycles
consumes    169 cycles to push            4 descriptors, average  42 cycles
consumes    139 cycles to push            2 descriptors, average  69 cycles
consumes    125 cycles to push            1 descriptors, average 125 cycles
Queue 2006 push test through Queue Manage VBUSM Data Space
consumes   8437 cycles to push          512 descriptors, average  16 cycles
consumes   3750 cycles to push          256 descriptors, average  14 cycles
consumes   1818 cycles to push          128 descriptors, average  14 cycles
consumes    942 cycles to push           64 descriptors, average  14 cycles
consumes    522 cycles to push           32 descriptors, average  16 cycles
consumes    319 cycles to push           16 descriptors, average  19 cycles
consumes    232 cycles to push            8 descriptors, average  29 cycles
consumes    164 cycles to push            4 descriptors, average  41 cycles
consumes    139 cycles to push            2 descriptors, average  69 cycles
consumes    122 cycles to push            1 descriptors, average 122 cycles
Queue 2006 pop test through Queue Manage Registers
consumes  60913 cycles to pop           512 descriptors, average 118 cycles
consumes  30498 cycles to pop           256 descriptors, average 119 cycles
consumes  15302 cycles to pop           128 descriptors, average 119 cycles
consumes   7703 cycles to pop            64 descriptors, average 120 cycles
consumes   3910 cycles to pop            32 descriptors, average 122 cycles
consumes   2011 cycles to pop            16 descriptors, average 125 cycles
consumes   1061 cycles to pop             8 descriptors, average 132 cycles
consumes    589 cycles to pop             4 descriptors, average 147 cycles
consumes    353 cycles to pop             2 descriptors, average 176 cycles
consumes    227 cycles to pop             1 descriptors, average 227 cycles
Queue 2006 pop test through Queue Manage VBUSM Data Space
consumes  64199 cycles to pop           512 descriptors, average 125 cycles
consumes  32079 cycles to pop           256 descriptors, average 125 cycles
consumes  16130 cycles to pop           128 descriptors, average 126 cycles
consumes   8126 cycles to pop            64 descriptors, average 126 cycles
consumes   4102 cycles to pop            32 descriptors, average 128 cycles
consumes   2110 cycles to pop            16 descriptors, average 131 cycles
consumes   1118 cycles to pop             8 descriptors, average 139 cycles
consumes    611 cycles to pop             4 descriptors, average 152 cycles
consumes    360 cycles to pop             2 descriptors, average 180 cycles
consumes    232 cycles to pop             1 descriptors, average 232 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57868 cycles to pop           512 descriptors, average 113 cycles
consumes  28982 cycles to pop           256 descriptors, average 113 cycles
consumes  14544 cycles to pop           128 descriptors, average 113 cycles
consumes   7325 cycles to pop            64 descriptors, average 114 cycles
consumes   3720 cycles to pop            32 descriptors, average 116 cycles
consumes   1918 cycles to pop            16 descriptors, average 119 cycles
consumes   1023 cycles to pop             8 descriptors, average 127 cycles
consumes    559 cycles to pop             4 descriptors, average 139 cycles
consumes    337 cycles to pop             2 descriptors, average 168 cycles
consumes    225 cycles to pop             1 descriptors, average 225 cycles
Queue 2006 push to pop delay test through Queue Manage Registers
consumes  95344 cycles to push and pop  512 descriptors, average 186 cycles
consumes  47676 cycles to push and pop  256 descriptors, average 186 cycles
consumes  23899 cycles to push and pop  128 descriptors, average 186 cycles
consumes  11990 cycles to push and pop   64 descriptors, average 187 cycles
consumes   6061 cycles to push and pop   32 descriptors, average 189 cycles
consumes   3095 cycles to push and pop   16 descriptors, average 193 cycles
consumes   1617 cycles to push and pop    8 descriptors, average 202 cycles
consumes    860 cycles to push and pop    4 descriptors, average 215 cycles
consumes    492 cycles to push and pop    2 descriptors, average 246 cycles
consumes    304 cycles to push and pop    1 descriptors, average 304 cycles
Queue 2006 push to pop delay test through Queue Manage VBUSM Data Space
consumes 106224 cycles to push and pop  512 descriptors, average 207 cycles
consumes  53078 cycles to push and pop  256 descriptors, average 207 cycles
consumes  26634 cycles to push and pop  128 descriptors, average 208 cycles
consumes  13353 cycles to push and pop   64 descriptors, average 208 cycles
consumes   6750 cycles to push and pop   32 descriptors, average 210 cycles
consumes   3435 cycles to push and pop   16 descriptors, average 214 cycles
consumes   1789 cycles to push and pop    8 descriptors, average 223 cycles
consumes    947 cycles to push and pop    4 descriptors, average 236 cycles
consumes    536 cycles to push and pop    2 descriptors, average 268 cycles
consumes    328 cycles to push and pop    1 descriptors, average 328 cycles
Queue Push/Pop test on descriptors with external linking RAM
Queue 2040 push test through Queue Manage Registers
consumes  10101 cycles to push          512 descriptors, average  19 cycles
consumes   4164 cycles to push          256 descriptors, average  16 cycles
consumes   1813 cycles to push          128 descriptors, average  14 cycles
consumes    949 cycles to push           64 descriptors, average  14 cycles
consumes    529 cycles to push           32 descriptors, average  16 cycles
consumes    322 cycles to push           16 descriptors, average  20 cycles
consumes    238 cycles to push            8 descriptors, average  29 cycles
consumes    183 cycles to push            4 descriptors, average  45 cycles
consumes    143 cycles to push            2 descriptors, average  71 cycles
consumes    129 cycles to push            1 descriptors, average 129 cycles
Queue 2040 push test through Queue Manage VBUSM Data Space
consumes   9988 cycles to push          512 descriptors, average  19 cycles
consumes   4216 cycles to push          256 descriptors, average  16 cycles
consumes   1831 cycles to push          128 descriptors, average  14 cycles
consumes    949 cycles to push           64 descriptors, average  14 cycles
consumes    529 cycles to push           32 descriptors, average  16 cycles
consumes    322 cycles to push           16 descriptors, average  20 cycles
consumes    245 cycles to push            8 descriptors, average  30 cycles
consumes    175 cycles to push            4 descriptors, average  43 cycles
consumes    143 cycles to push            2 descriptors, average  71 cycles
consumes    129 cycles to push            1 descriptors, average 129 cycles
Queue 2040 pop test through Queue Manage Registers
consumes  66076 cycles to pop           512 descriptors, average 129 cycles
consumes  33094 cycles to pop           256 descriptors, average 129 cycles
consumes  16580 cycles to pop           128 descriptors, average 129 cycles
consumes   8347 cycles to pop            64 descriptors, average 130 cycles
consumes   4223 cycles to pop            32 descriptors, average 131 cycles
consumes   2166 cycles to pop            16 descriptors, average 135 cycles
consumes   1148 cycles to pop             8 descriptors, average 143 cycles
consumes    617 cycles to pop             4 descriptors, average 154 cycles
consumes    361 cycles to pop             2 descriptors, average 180 cycles
consumes    232 cycles to pop             1 descriptors, average 232 cycles
Queue 2040 pop test through Queue Manage VBUSM Data Space
consumes  66096 cycles to pop           512 descriptors, average 129 cycles
consumes  33091 cycles to pop           256 descriptors, average 129 cycles
consumes  16603 cycles to pop           128 descriptors, average 129 cycles
consumes   8358 cycles to pop            64 descriptors, average 130 cycles
consumes   4226 cycles to pop            32 descriptors, average 132 cycles
consumes   2169 cycles to pop            16 descriptors, average 135 cycles
consumes   1155 cycles to pop             8 descriptors, average 144 cycles
consumes    634 cycles to pop             4 descriptors, average 158 cycles
consumes    368 cycles to pop             2 descriptors, average 184 cycles
consumes    241 cycles to pop             1 descriptors, average 241 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57849 cycles to pop           512 descriptors, average 112 cycles
consumes  29007 cycles to pop           256 descriptors, average 113 cycles
consumes  14544 cycles to pop           128 descriptors, average 113 cycles
consumes   7330 cycles to pop            64 descriptors, average 114 cycles
consumes   3720 cycles to pop            32 descriptors, average 116 cycles
consumes   1920 cycles to pop            16 descriptors, average 120 cycles
consumes   1032 cycles to pop             8 descriptors, average 129 cycles
consumes    568 cycles to pop             4 descriptors, average 142 cycles
consumes    343 cycles to pop             2 descriptors, average 171 cycles
consumes    227 cycles to pop             1 descriptors, average 227 cycles
Queue 2040 push to pop delay test through Queue Manage Registers
consumes  95618 cycles to push and pop  512 descriptors, average 186 cycles
consumes  47809 cycles to push and pop  256 descriptors, average 186 cycles
consumes  23960 cycles to push and pop  128 descriptors, average 187 cycles
consumes  12040 cycles to push and pop   64 descriptors, average 188 cycles
consumes   6077 cycles to push and pop   32 descriptors, average 189 cycles
consumes   3098 cycles to push and pop   16 descriptors, average 193 cycles
consumes   1609 cycles to push and pop    8 descriptors, average 201 cycles
consumes    869 cycles to push and pop    4 descriptors, average 217 cycles
consumes    490 cycles to push and pop    2 descriptors, average 245 cycles
consumes    302 cycles to push and pop    1 descriptors, average 302 cycles
Queue 2040 push to pop delay test through Queue Manage VBUSM Data Space
consumes 109052 cycles to push and pop  512 descriptors, average 212 cycles
consumes  54489 cycles to push and pop  256 descriptors, average 212 cycles
consumes  27326 cycles to push and pop  128 descriptors, average 213 cycles
consumes  13708 cycles to push and pop   64 descriptors, average 214 cycles
consumes   6903 cycles to push and pop   32 descriptors, average 215 cycles
consumes   3510 cycles to push and pop   16 descriptors, average 219 cycles
consumes   1808 cycles to push and pop    8 descriptors, average 226 cycles
consumes    970 cycles to push and pop    4 descriptors, average 242 cycles
consumes    533 cycles to push and pop    2 descriptors, average 266 cycles
consumes    325 cycles to push and pop    1 descriptors, average 325 cycles

Queue pend interrupt test on descriptors with internal linking RAM
Queue 662 pending interrupt happens at 27058744
consumes   1044 cycles between push queue 662 and pend interrupt
Queue 8706 pending interrupt happens at 27070556
consumes    455 cycles between push queue 8854 and pend interrupt
Queue pend interrupt test on descriptors with external linking RAM
Queue 662 pending interrupt happens at 27083216
consumes    585 cycles between push queue 662 and pend interrupt
Queue 8706 pending interrupt happens at 27093484
consumes    457 cycles between push queue 8854 and pend interrupt

descriptor Reclamation test in queue 2010
consumes    960 cycles for one descriptor Reclamation
consumes   1294 cycles for one descriptor Reclamation
consumes   1527 cycles for one descriptor Reclamation
consumes    759 cycles for one descriptor Reclamation
consumes   1527 cycles for one descriptor Reclamation
consumes   1316 cycles for one descriptor Reclamation
consumes   1442 cycles for one descriptor Reclamation
consumes   1316 cycles for one descriptor Reclamation
consumes   1437 cycles for one descriptor Reclamation
consumes    896 cycles for one descriptor Reclamation

Queue Push/accumulation test with ACC48 firmware on INTD1
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27157799
consumes   3727 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27174412
consumes   7030 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27187374
consumes   3283 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27203638
consumes   6925 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27216820
consumes   3286 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27237460
consumes  11138 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27251605
consumes   4072 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27271444
consumes  10446 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27284836
consumes   3616 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27309745
consumes  15710 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27322664
consumes   3105 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27344136
consumes  12248 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27357044
consumes   3099 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27376941
consumes  10675 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27390503
consumes   3856 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27410744
consumes  11011 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27424104
consumes   3569 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27444493
consumes  11100 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 27457699
consumes   3315 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 27473709
consumes   6787 cycles to push and accumulate one descriptor with  low priority

Queue Push/accumulation test with ACC48 firmware on INTD2
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27494975
consumes   3579 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27508822
consumes   4503 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27521559
consumes   3381 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27533690
consumes   2868 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27546412
consumes   3609 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27567242
consumes  11707 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27579921
consumes   3064 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27604418
consumes  15511 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27617499
consumes   3442 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27641144
consumes  14575 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27654313
consumes   3490 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27676955
consumes  13600 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27690539
consumes   3904 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27703202
consumes   3626 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27715440
consumes   3112 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27736669
consumes  12158 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27749707
consumes   3370 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27762928
consumes   4160 cycles to push and accumulate one descriptor with  low priority
QMSS INTD2 high priority queue accumulation channel 0 interrupt happens at 27775597
consumes   3496 cycles to push and accumulate one descriptor with high priority
INTD2 low priority queues accumulation channel 0 interrupt happens at 27795851
consumes  11190 cycles to push and accumulate one descriptor with  low priority
test Packet DMA1 in QMSS
host Packet DMA test with 1 channels
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x c0dc280 to 0x880c0000 with channel  0, consumes  1120 cycles
Packet DMA achieves   12 MB/s when transfer    16 bytes from 0x c0de280 to 0x880c0100 with channel  0, consumes  1553 cycles
Packet DMA achieves   29 MB/s when transfer    32 bytes from 0x c0e0280 to 0x880c0200 with channel  0, consumes  1317 cycles
Packet DMA achieves   77 MB/s when transfer    64 bytes from 0x c0e2280 to 0x880c0300 with channel  0, consumes   984 cycles
Packet DMA achieves  117 MB/s when transfer   128 bytes from 0x c0e4280 to 0x880c0400 with channel  0, consumes  1308 cycles
Packet DMA achieves  237 MB/s when transfer   256 bytes from 0x c0e6280 to 0x880c0500 with channel  0, consumes  1292 cycles
Packet DMA achieves  405 MB/s when transfer   512 bytes from 0x c0e8280 to 0x88100000 with channel  0, consumes  1511 cycles
Packet DMA achieves  683 MB/s when transfer  1024 bytes from 0x c0ea280 to 0x88100800 with channel  0, consumes  1794 cycles
Packet DMA achieves  945 MB/s when transfer  2048 bytes from 0x c0ec280 to 0x88101000 with channel  0, consumes  2595 cycles
Packet DMA achieves 1195 MB/s when transfer  4096 bytes from 0x c0ee280 to 0x88180000 with channel  0, consumes  4105 cycles
Packet DMA achieves 1370 MB/s when transfer  8192 bytes from 0x c0f0280 to 0x88184000 with channel  0, consumes  7163 cycles
Packet DMA achieves    6 MB/s when transfer     8 bytes from 0x883c0000 to 0x c07c280 with channel  0, consumes  1407 cycles
Packet DMA achieves   10 MB/s when transfer    16 bytes from 0x883e0000 to 0x c07c380 with channel  0, consumes  1785 cycles
Packet DMA achieves   39 MB/s when transfer    32 bytes from 0x88400000 to 0x c07c480 with channel  0, consumes   961 cycles
Packet DMA achieves   71 MB/s when transfer    64 bytes from 0x88420000 to 0x c07c580 with channel  0, consumes  1065 cycles
Packet DMA achieves  113 MB/s when transfer   128 bytes from 0x88440000 to 0x c07c680 with channel  0, consumes  1351 cycles
Packet DMA achieves  219 MB/s when transfer   256 bytes from 0x88460000 to 0x c07c780 with channel  0, consumes  1399 cycles
Packet DMA achieves  397 MB/s when transfer   512 bytes from 0x88280000 to 0x c09c280 with channel  0, consumes  1543 cycles
Packet DMA achieves  680 MB/s when transfer  1024 bytes from 0x882a0000 to 0x c09c680 with channel  0, consumes  1802 cycles
Packet DMA achieves  845 MB/s when transfer  2048 bytes from 0x882c0000 to 0x c0bc280 with channel  0, consumes  2903 cycles
Packet DMA achieves 1014 MB/s when transfer  4096 bytes from 0x882e0000 to 0x c0bd280 with channel  0, consumes  4835 cycles
Packet DMA achieves 1012 MB/s when transfer  8192 bytes from 0x88300000 to 0x c0f2280 with channel  0, consumes  9692 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves    9 MB/s when transfer     8 bytes from 0x c03c090 to 0x83095ffc with channel  0, consumes   998 cycles
Packet DMA achieves   14 MB/s when transfer    16 bytes from 0x c03e0a0 to 0x8309800c with channel  0, consumes  1291 cycles
Packet DMA achieves   37 MB/s when transfer    32 bytes from 0x c0400b0 to 0x8309a01c with channel  0, consumes  1015 cycles
Packet DMA achieves   79 MB/s when transfer    64 bytes from 0x c0420c0 to 0x8309c02c with channel  0, consumes   967 cycles
Packet DMA achieves  146 MB/s when transfer   128 bytes from 0x c0440d0 to 0x8309e03c with channel  0, consumes  1045 cycles
Packet DMA achieves  270 MB/s when transfer   256 bytes from 0x c0460e0 to 0x830a004c with channel  0, consumes  1134 cycles
Packet DMA achieves  423 MB/s when transfer   512 bytes from 0x c0480f0 to 0x830a205c with channel  0, consumes  1450 cycles
Packet DMA achieves  750 MB/s when transfer  1024 bytes from 0x c04a100 to 0x830a406c with channel  0, consumes  1635 cycles
Packet DMA achieves 1030 MB/s when transfer  2048 bytes from 0x c04c110 to 0x830a607c with channel  0, consumes  2382 cycles
Packet DMA achieves 1257 MB/s when transfer  4096 bytes from 0x c04e120 to 0x830a808c with channel  0, consumes  3902 cycles
Packet DMA achieves 1407 MB/s when transfer  8192 bytes from 0x c050130 to 0x830aa09c with channel  0, consumes  6973 cycles
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x830ac0b0 to 0x c05213c with channel  0, consumes   858 cycles
Packet DMA achieves   11 MB/s when transfer    16 bytes from 0x830ae0c0 to 0x c05414c with channel  0, consumes  1682 cycles
Packet DMA achieves   30 MB/s when transfer    32 bytes from 0x830b00d0 to 0x c05615c with channel  0, consumes  1246 cycles
Packet DMA achieves   55 MB/s when transfer    64 bytes from 0x830b20e0 to 0x c05816c with channel  0, consumes  1381 cycles
Packet DMA achieves  124 MB/s when transfer   128 bytes from 0x830b40f0 to 0x c05a17c with channel  0, consumes  1232 cycles
Packet DMA achieves  240 MB/s when transfer   256 bytes from 0x830b6100 to 0x c05c18c with channel  0, consumes  1276 cycles
Packet DMA achieves  398 MB/s when transfer   512 bytes from 0x830b8110 to 0x c05e19c with channel  0, consumes  1539 cycles
Packet DMA achieves  581 MB/s when transfer  1024 bytes from 0x830ba120 to 0x c0601ac with channel  0, consumes  2110 cycles
Packet DMA achieves  843 MB/s when transfer  2048 bytes from 0x830bc130 to 0x c0621bc with channel  0, consumes  2910 cycles
Packet DMA achieves 1036 MB/s when transfer  4096 bytes from 0x830be140 to 0x c0641cc with channel  0, consumes  4735 cycles
Packet DMA achieves 1024 MB/s when transfer  8192 bytes from 0x830c0150 to 0x c0661dc with channel  0, consumes  9582 cycles
host Packet DMA test with 2 channels
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x c0f6280 to 0x880c0600 with channel  0, from 0x c0f6280 to 0x880c0700 with channel  1, consumes  1724 cycles
Packet DMA achieves   21 MB/s when transfer    16 bytes from 0x c0fa280 to 0x880c0800 with channel  0, from 0x c0fa280 to 0x880c0900 with channel  1, consumes  1791 cycles
Packet DMA achieves   64 MB/s when transfer    32 bytes from 0x c0de280 to 0x880c0a00 with channel  0, from 0x c0de280 to 0x880c0b00 with channel  1, consumes  1198 cycles
Packet DMA achieves  113 MB/s when transfer    64 bytes from 0x c0e2280 to 0x880c0c00 with channel  0, from 0x c0e2280 to 0x880c0d00 with channel  1, consumes  1351 cycles
Packet DMA achieves  212 MB/s when transfer   128 bytes from 0x c0e6280 to 0x880c0e00 with channel  0, from 0x c0e6280 to 0x880c0f00 with channel  1, consumes  1443 cycles
Packet DMA achieves  389 MB/s when transfer   256 bytes from 0x c0ea280 to 0x880c1000 with channel  0, from 0x c0ea280 to 0x880c1100 with channel  1, consumes  1576 cycles
Packet DMA achieves  814 MB/s when transfer   512 bytes from 0x c0ee280 to 0x88101800 with channel  0, from 0x c0ee280 to 0x88102000 with channel  1, consumes  1507 cycles
Packet DMA achieves  808 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x88102800 with channel  0, from 0x c0f2280 to 0x88103000 with channel  1, consumes  3036 cycles
Packet DMA achieves 1783 MB/s when transfer  2048 bytes from 0x c0f6280 to 0x88103800 with channel  0, from 0x c0f6280 to 0x88104000 with channel  1, consumes  2752 cycles
Packet DMA achieves 2371 MB/s when transfer  4096 bytes from 0x c0fa280 to 0x88188000 with channel  0, from 0x c0fa280 to 0x8818c000 with channel  1, consumes  4138 cycles
Packet DMA achieves 2727 MB/s when transfer  8192 bytes from 0x c0de280 to 0x88190000 with channel  0, from 0x c0de280 to 0x88194000 with channel  1, consumes  7197 cycles
Packet DMA achieves    9 MB/s when transfer     8 bytes from 0x88340000 to 0x c07c880 with channel  0, from 0x88340000 to 0x c07c980 with channel  1, consumes  1955 cycles
Packet DMA achieves   35 MB/s when transfer    16 bytes from 0x88380000 to 0x c07ca80 with channel  0, from 0x88380000 to 0x c07cb80 with channel  1, consumes  1094 cycles
Packet DMA achieves   53 MB/s when transfer    32 bytes from 0x883c0000 to 0x c07cc80 with channel  0, from 0x883c0000 to 0x c07cd80 with channel  1, consumes  1425 cycles
Packet DMA achieves  120 MB/s when transfer    64 bytes from 0x88400000 to 0x c07ce80 with channel  0, from 0x88400000 to 0x c07cf80 with channel  1, consumes  1275 cycles
Packet DMA achieves  209 MB/s when transfer   128 bytes from 0x88440000 to 0x c07d080 with channel  0, from 0x88440000 to 0x c07d180 with channel  1, consumes  1464 cycles
Packet DMA achieves  374 MB/s when transfer   256 bytes from 0x88280000 to 0x c07d280 with channel  0, from 0x88280000 to 0x c07d380 with channel  1, consumes  1640 cycles
Packet DMA achieves  588 MB/s when transfer   512 bytes from 0x882c0000 to 0x c09ca80 with channel  0, from 0x882c0000 to 0x c09ce80 with channel  1, consumes  2083 cycles
Packet DMA achieves  758 MB/s when transfer  1024 bytes from 0x88300000 to 0x c09d280 with channel  0, from 0x88300000 to 0x c09d680 with channel  1, consumes  3235 cycles
Packet DMA achieves  990 MB/s when transfer  2048 bytes from 0x88340000 to 0x c0be280 with channel  0, from 0x88340000 to 0x c0bf280 with channel  1, consumes  4956 cycles
Packet DMA achieves 1120 MB/s when transfer  4096 bytes from 0x88380000 to 0x c0c0280 with channel  0, from 0x88380000 to 0x c0c1280 with channel  1, consumes  8761 cycles
Packet DMA achieves 1178 MB/s when transfer  8192 bytes from 0x883c0000 to 0x c0e0280 with channel  0, from 0x883c0000 to 0x c0e2280 with channel  1, consumes 16652 cycles
monolithic Packet DMA test with 2 channels
Packet DMA achieves   13 MB/s when transfer     8 bytes from 0x c06a200 to 0x830c215c with channel  0, from 0x c06a200 to 0x830c416c with channel  1, consumes  1421 cycles
Packet DMA achieves   27 MB/s when transfer    16 bytes from 0x c06e220 to 0x830c617c with channel  0, from 0x c06e220 to 0x830c818c with channel  1, consumes  1406 cycles
Packet DMA achieves   62 MB/s when transfer    32 bytes from 0x c072240 to 0x830ca19c with channel  0, from 0x c072240 to 0x830cc1ac with channel  1, consumes  1234 cycles
Packet DMA achieves  149 MB/s when transfer    64 bytes from 0x c076260 to 0x830ce1bc with channel  0, from 0x c076260 to 0x830d01cc with channel  1, consumes  1025 cycles
Packet DMA achieves  295 MB/s when transfer   128 bytes from 0x c07a280 to 0x830d21dc with channel  0, from 0x c07a280 to 0x830d41ec with channel  1, consumes  1039 cycles
Packet DMA achieves  516 MB/s when transfer   256 bytes from 0x c03e0a0 to 0x830d61fc with channel  0, from 0x c03e0a0 to 0x830d820c with channel  1, consumes  1188 cycles
Packet DMA achieves  854 MB/s when transfer   512 bytes from 0x c0420c0 to 0x830da21c with channel  0, from 0x c0420c0 to 0x830dc22c with channel  1, consumes  1436 cycles
Packet DMA achieves 1390 MB/s when transfer  1024 bytes from 0x c0460e0 to 0x830de23c with channel  0, from 0x c0460e0 to 0x830e024c with channel  1, consumes  1764 cycles
Packet DMA achieves 1899 MB/s when transfer  2048 bytes from 0x c04a100 to 0x830e225c with channel  0, from 0x c04a100 to 0x830e426c with channel  1, consumes  2584 cycles
Packet DMA achieves 2377 MB/s when transfer  4096 bytes from 0x c04e120 to 0x830e627c with channel  0, from 0x c04e120 to 0x830e828c with channel  1, consumes  4129 cycles
Packet DMA achieves 2772 MB/s when transfer  8192 bytes from 0x c05213c to 0x830ea29c with channel  0, from 0x c05213c to 0x830ec2ac with channel  1, consumes  7079 cycles
Packet DMA achieves   15 MB/s when transfer     8 bytes from 0x830f02d0 to 0x c05414c with channel  0, from 0x830f02d0 to 0x c05615c with channel  1, consumes  1245 cycles
Packet DMA achieves   25 MB/s when transfer    16 bytes from 0x830f42f0 to 0x c05816c with channel  0, from 0x830f42f0 to 0x c05a17c with channel  1, consumes  1528 cycles
Packet DMA achieves   60 MB/s when transfer    32 bytes from 0x830f8310 to 0x c05c18c with channel  0, from 0x830f8310 to 0x c05e19c with channel  1, consumes  1258 cycles
Packet DMA achieves  117 MB/s when transfer    64 bytes from 0x830fc330 to 0x c0601ac with channel  0, from 0x830fc330 to 0x c0621bc with channel  1, consumes  1309 cycles
Packet DMA achieves  226 MB/s when transfer   128 bytes from 0x83100350 to 0x c0641cc with channel  0, from 0x83100350 to 0x c0661dc with channel  1, consumes  1354 cycles
Packet DMA achieves  457 MB/s when transfer   256 bytes from 0x83104370 to 0x c0681ec with channel  0, from 0x83104370 to 0x c06a1fc with channel  1, consumes  1340 cycles
Packet DMA achieves  777 MB/s when transfer   512 bytes from 0x83108390 to 0x c06c20c with channel  0, from 0x83108390 to 0x c06e21c with channel  1, consumes  1578 cycles
Packet DMA achieves 1119 MB/s when transfer  1024 bytes from 0x8310c3b0 to 0x c07022c with channel  0, from 0x8310c3b0 to 0x c07223c with channel  1, consumes  2191 cycles
Packet DMA achieves 1648 MB/s when transfer  2048 bytes from 0x831103d0 to 0x c07424c with channel  0, from 0x831103d0 to 0x c07625c with channel  1, consumes  2976 cycles
Packet DMA achieves 2057 MB/s when transfer  4096 bytes from 0x831143f0 to 0x c07826c with channel  0, from 0x831143f0 to 0x c07a27c with channel  1, consumes  4770 cycles
Packet DMA achieves 2269 MB/s when transfer  8192 bytes from 0x83118410 to 0x c03c08c with channel  0, from 0x83118410 to 0x c03e09c with channel  1, consumes  8648 cycles
host Packet DMA test with 4 channels
Packet DMA achieves   26 MB/s when transfer     8 bytes from 0x c0ea280 to 0x880c1200 with channel  0, from 0x c0ea280 to 0x880c1300 with channel  1, from 0x c0ea280 to 0x880c1400 with channel  2, from 0x c0ea280 to 0x880c1500 with channel  3, consumes  1460 cycles
Packet DMA achieves   38 MB/s when transfer    16 bytes from 0x c0f2280 to 0x880c1600 with channel  0, from 0x c0f2280 to 0x880c1700 with channel  1, from 0x c0f2280 to 0x880c1800 with channel  2, from 0x c0f2280 to 0x880c1900 with channel  3, consumes  1978 cycles
Packet DMA achieves  104 MB/s when transfer    32 bytes from 0x c0fa280 to 0x880c1a00 with channel  0, from 0x c0fa280 to 0x880c1b00 with channel  1, from 0x c0fa280 to 0x880c1c00 with channel  2, from 0x c0fa280 to 0x880c1d00 with channel  3, consumes  1464 cycles
Packet DMA achieves  241 MB/s when transfer    64 bytes from 0x c0e2280 to 0x880c1e00 with channel  0, from 0x c0e2280 to 0x880c1f00 with channel  1, from 0x c0e2280 to 0x880c2000 with channel  2, from 0x c0e2280 to 0x880c2100 with channel  3, consumes  1272 cycles
Packet DMA achieves  526 MB/s when transfer   128 bytes from 0x c0ea280 to 0x880c2200 with channel  0, from 0x c0ea280 to 0x880c2300 with channel  1, from 0x c0ea280 to 0x880c2400 with channel  2, from 0x c0ea280 to 0x880c2500 with channel  3, consumes  1164 cycles
Packet DMA achieves  902 MB/s when transfer   256 bytes from 0x c0f2280 to 0x880c2600 with channel  0, from 0x c0f2280 to 0x880c2700 with channel  1, from 0x c0f2280 to 0x880c2800 with channel  2, from 0x c0f2280 to 0x880c2900 with channel  3, consumes  1359 cycles
Packet DMA achieves 1559 MB/s when transfer   512 bytes from 0x c0fa280 to 0x88104800 with channel  0, from 0x c0fa280 to 0x88105000 with channel  1, from 0x c0fa280 to 0x88105800 with channel  2, from 0x c0fa280 to 0x88106000 with channel  3, consumes  1573 cycles
Packet DMA achieves 2121 MB/s when transfer  1024 bytes from 0x c0e2280 to 0x88106800 with channel  0, from 0x c0e2280 to 0x88107000 with channel  1, from 0x c0e2280 to 0x88107800 with channel  2, from 0x c0e2280 to 0x88108000 with channel  3, consumes  2313 cycles
Packet DMA achieves 3434 MB/s when transfer  2048 bytes from 0x c0ea280 to 0x88108800 with channel  0, from 0x c0ea280 to 0x88109000 with channel  1, from 0x c0ea280 to 0x88109800 with channel  2, from 0x c0ea280 to 0x8810a000 with channel  3, consumes  2858 cycles
Packet DMA achieves 4518 MB/s when transfer  4096 bytes from 0x c0f2280 to 0x88198000 with channel  0, from 0x c0f2280 to 0x8819c000 with channel  1, from 0x c0f2280 to 0x881a0000 with channel  2, from 0x c0f2280 to 0x881a4000 with channel  3, consumes  4344 cycles
Packet DMA achieves 5330 MB/s when transfer  8192 bytes from 0x c0fa280 to 0x881a8000 with channel  0, from 0x c0fa280 to 0x881ac000 with channel  1, from 0x c0fa280 to 0x881b0000 with channel  2, from 0x c0fa280 to 0x881b4000 with channel  3, consumes  7365 cycles
Packet DMA achieves   32 MB/s when transfer     8 bytes from 0x88440000 to 0x c07d480 with channel  0, from 0x88440000 to 0x c07d580 with channel  1, from 0x88440000 to 0x c07d680 with channel  2, from 0x88440000 to 0x c07d780 with channel  3, consumes  1180 cycles
Packet DMA achieves   64 MB/s when transfer    16 bytes from 0x882c0000 to 0x c07d880 with channel  0, from 0x882c0000 to 0x c07d980 with channel  1, from 0x882c0000 to 0x c07da80 with channel  2, from 0x882c0000 to 0x c07db80 with channel  3, consumes  1189 cycles
Packet DMA achieves  129 MB/s when transfer    32 bytes from 0x88340000 to 0x c07dc80 with channel  0, from 0x88340000 to 0x c07dd80 with channel  1, from 0x88340000 to 0x c07de80 with channel  2, from 0x88340000 to 0x c07df80 with channel  3, consumes  1183 cycles
Packet DMA achieves  239 MB/s when transfer    64 bytes from 0x883c0000 to 0x c07e080 with channel  0, from 0x883c0000 to 0x c07e180 with channel  1, from 0x883c0000 to 0x c07e280 with channel  2, from 0x883c0000 to 0x c07e380 with channel  3, consumes  1280 cycles
Packet DMA achieves  454 MB/s when transfer   128 bytes from 0x88440000 to 0x c07e480 with channel  0, from 0x88440000 to 0x c07e580 with channel  1, from 0x88440000 to 0x c07e680 with channel  2, from 0x88440000 to 0x c07e780 with channel  3, consumes  1351 cycles
Packet DMA achieves  685 MB/s when transfer   256 bytes from 0x882c0000 to 0x c07e880 with channel  0, from 0x882c0000 to 0x c07e980 with channel  1, from 0x882c0000 to 0x c07ea80 with channel  2, from 0x882c0000 to 0x c07eb80 with channel  3, consumes  1789 cycles
Packet DMA achieves  965 MB/s when transfer   512 bytes from 0x88340000 to 0x c09da80 with channel  0, from 0x88340000 to 0x c09de80 with channel  1, from 0x88340000 to 0x c09e280 with channel  2, from 0x88340000 to 0x c09e680 with channel  3, consumes  2542 cycles
Packet DMA achieves 1101 MB/s when transfer  1024 bytes from 0x883c0000 to 0x c09ea80 with channel  0, from 0x883c0000 to 0x c09ee80 with channel  1, from 0x883c0000 to 0x c09f280 with channel  2, from 0x883c0000 to 0x c09f680 with channel  3, consumes  4454 cycles
Packet DMA achieves 1219 MB/s when transfer  2048 bytes from 0x88440000 to 0x c0c2280 with channel  0, from 0x88440000 to 0x c0c3280 with channel  1, from 0x88440000 to 0x c0c4280 with channel  2, from 0x88440000 to 0x c0c5280 with channel  3, consumes  8045 cycles
Packet DMA achieves 1401 MB/s when transfer  4096 bytes from 0x882c0000 to 0x c0c6280 with channel  0, from 0x882c0000 to 0x c0c7280 with channel  1, from 0x882c0000 to 0x c0c8280 with channel  2, from 0x882c0000 to 0x c0c9280 with channel  3, consumes 14008 cycles
Packet DMA achieves 1203 MB/s when transfer  8192 bytes from 0x88340000 to 0x c0dc280 with channel  0, from 0x88340000 to 0x c0e0280 with channel  1, from 0x88340000 to 0x c0de280 with channel  2, from 0x88340000 to 0x c0e2280 with channel  3, consumes 32607 cycles
monolithic Packet DMA test with 4 channels
Packet DMA achieves   41 MB/s when transfer     8 bytes from 0x c0460e0 to 0x8311a41c with channel  0, from 0x c0460e0 to 0x8311c42c with channel  1, from 0x c0460e0 to 0x8311e43c with channel  2, from 0x c0460e0 to 0x8312044c with channel  3, consumes   933 cycles
Packet DMA achieves   82 MB/s when transfer    16 bytes from 0x c04e120 to 0x8312245c with channel  0, from 0x c04e120 to 0x8312446c with channel  1, from 0x c04e120 to 0x8312647c with channel  2, from 0x c04e120 to 0x8312848c with channel  3, consumes   935 cycles
Packet DMA achieves  163 MB/s when transfer    32 bytes from 0x c05615c to 0x8312a49c with channel  0, from 0x c05615c to 0x8312c4ac with channel  1, from 0x c05615c to 0x8312e4bc with channel  2, from 0x c05615c to 0x831304cc with channel  3, consumes   937 cycles
Packet DMA achieves  328 MB/s when transfer    64 bytes from 0x c05e19c to 0x831324dc with channel  0, from 0x c05e19c to 0x831344ec with channel  1, from 0x c05e19c to 0x831364fc with channel  2, from 0x c05e19c to 0x8313850c with channel  3, consumes   934 cycles
Packet DMA achieves  629 MB/s when transfer   128 bytes from 0x c0661dc to 0x8313a51c with channel  0, from 0x c0661dc to 0x8313c52c with channel  1, from 0x c0661dc to 0x8313e53c with channel  2, from 0x c0661dc to 0x8314054c with channel  3, consumes   975 cycles
Packet DMA achieves 1059 MB/s when transfer   256 bytes from 0x c06e21c to 0x8314255c with channel  0, from 0x c06e21c to 0x8314456c with channel  1, from 0x c06e21c to 0x8314657c with channel  2, from 0x c06e21c to 0x8314858c with channel  3, consumes  1158 cycles
Packet DMA achieves 1645 MB/s when transfer   512 bytes from 0x c07625c to 0x8314a59c with channel  0, from 0x c07625c to 0x8314c5ac with channel  1, from 0x c07625c to 0x8314e5bc with channel  2, from 0x c07625c to 0x831505cc with channel  3, consumes  1491 cycles
Packet DMA achieves 2749 MB/s when transfer  1024 bytes from 0x c03e09c to 0x831525dc with channel  0, from 0x c03e09c to 0x831545ec with channel  1, from 0x c03e09c to 0x831565fc with channel  2, from 0x c03e09c to 0x8315860c with channel  3, consumes  1785 cycles
Packet DMA achieves 3719 MB/s when transfer  2048 bytes from 0x c0460e0 to 0x8315a61c with channel  0, from 0x c0460e0 to 0x8315c62c with channel  1, from 0x c0460e0 to 0x8315e63c with channel  2, from 0x c0460e0 to 0x8316064c with channel  3, consumes  2639 cycles
Packet DMA achieves 4775 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8316265c with channel  0, from 0x c04e120 to 0x8316466c with channel  1, from 0x c04e120 to 0x8316667c with channel  2, from 0x c04e120 to 0x8316868c with channel  3, consumes  4110 cycles
Packet DMA achieves 5478 MB/s when transfer  8192 bytes from 0x c05615c to 0x8316a69c with channel  0, from 0x c05615c to 0x8316c6ac with channel  1, from 0x c05615c to 0x8316e6bc with channel  2, from 0x c05615c to 0x831706cc with channel  3, consumes  7166 cycles
Packet DMA achieves   36 MB/s when transfer     8 bytes from 0x83178710 to 0x c05816c with channel  0, from 0x83178710 to 0x c05a17c with channel  1, from 0x83178710 to 0x c05c18c with channel  2, from 0x83178710 to 0x c05e19c with channel  3, consumes  1048 cycles
Packet DMA achieves   70 MB/s when transfer    16 bytes from 0x83180750 to 0x c0601ac with channel  0, from 0x83180750 to 0x c0641cc with channel  1, from 0x83180750 to 0x c0621bc with channel  2, from 0x83180750 to 0x c0661dc with channel  3, consumes  1089 cycles
Packet DMA achieves  140 MB/s when transfer    32 bytes from 0x83188790 to 0x c0681ec with channel  0, from 0x83188790 to 0x c06c20c with channel  1, from 0x83188790 to 0x c06a1fc with channel  2, from 0x83188790 to 0x c06e21c with channel  3, consumes  1088 cycles
Packet DMA achieves  288 MB/s when transfer    64 bytes from 0x831907d0 to 0x c07022c with channel  0, from 0x831907d0 to 0x c07424c with channel  1, from 0x831907d0 to 0x c07223c with channel  2, from 0x831907d0 to 0x c07625c with channel  3, consumes  1064 cycles
Packet DMA achieves  528 MB/s when transfer   128 bytes from 0x83198810 to 0x c07826c with channel  0, from 0x83198810 to 0x c03c08c with channel  1, from 0x83198810 to 0x c07a27c with channel  2, from 0x83198810 to 0x c03e09c with channel  3, consumes  1161 cycles
Packet DMA achieves  972 MB/s when transfer   256 bytes from 0x831a0850 to 0x c0400ac with channel  0, from 0x831a0850 to 0x c0420bc with channel  1, from 0x831a0850 to 0x c0440cc with channel  2, from 0x831a0850 to 0x c0460dc with channel  3, consumes  1262 cycles
Packet DMA achieves 1662 MB/s when transfer   512 bytes from 0x831a8890 to 0x c04a0fc with channel  0, from 0x831a8890 to 0x c0480ec with channel  1, from 0x831a8890 to 0x c04c10c with channel  2, from 0x831a8890 to 0x c04e11c with channel  3, consumes  1476 cycles
Packet DMA achieves 2467 MB/s when transfer  1024 bytes from 0x831b08d0 to 0x c05012c with channel  0, from 0x831b08d0 to 0x c05414c with channel  1, from 0x831b08d0 to 0x c05213c with channel  2, from 0x831b08d0 to 0x c05615c with channel  3, consumes  1989 cycles
Packet DMA achieves 3217 MB/s when transfer  2048 bytes from 0x831b8910 to 0x c05a17c with channel  0, from 0x831b8910 to 0x c05816c with channel  1, from 0x831b8910 to 0x c05c18c with channel  2, from 0x831b8910 to 0x c05e19c with channel  3, consumes  3050 cycles
Packet DMA achieves 3885 MB/s when transfer  4096 bytes from 0x831c0950 to 0x c0601ac with channel  0, from 0x831c0950 to 0x c0641cc with channel  1, from 0x831c0950 to 0x c0621bc with channel  2, from 0x831c0950 to 0x c0661dc with channel  3, consumes  5052 cycles
Packet DMA achieves 3692 MB/s when transfer  8192 bytes from 0x831c8990 to 0x c06c20c with channel  0, from 0x831c8990 to 0x c0681ec with channel  1, from 0x831c8990 to 0x c06a1fc with channel  2, from 0x831c8990 to 0x c06e21c with channel  3, consumes 10633 cycles
test Packet DMA2 in QMSS
host Packet DMA test with 1 channels
Packet DMA achieves    6 MB/s when transfer     8 bytes from 0x c0e4280 to 0x880c2a00 with channel  0, consumes  1443 cycles
Packet DMA achieves   19 MB/s when transfer    16 bytes from 0x c0e8280 to 0x880c2b00 with channel  0, consumes   980 cycles
Packet DMA achieves   31 MB/s when transfer    32 bytes from 0x c0e6280 to 0x880c2c00 with channel  0, consumes  1205 cycles
Packet DMA achieves   68 MB/s when transfer    64 bytes from 0x c0ea280 to 0x880c2d00 with channel  0, consumes  1116 cycles
Packet DMA achieves  137 MB/s when transfer   128 bytes from 0x c0ec280 to 0x880c2e00 with channel  0, consumes  1116 cycles
Packet DMA achieves  253 MB/s when transfer   256 bytes from 0x c0f0280 to 0x880c2f00 with channel  0, consumes  1211 cycles
Packet DMA achieves  416 MB/s when transfer   512 bytes from 0x c0ee280 to 0x8810a800 with channel  0, consumes  1472 cycles
Packet DMA achieves  650 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x8810b000 with channel  0, consumes  1885 cycles
Packet DMA achieves  945 MB/s when transfer  2048 bytes from 0x c0f4280 to 0x8810b800 with channel  0, consumes  2595 cycles
Packet DMA achieves 1182 MB/s when transfer  4096 bytes from 0x c0f6280 to 0x881b8000 with channel  0, consumes  4151 cycles
Packet DMA achieves 1365 MB/s when transfer  8192 bytes from 0x c0f8280 to 0x881bc000 with channel  0, consumes  7187 cycles
Packet DMA achieves    9 MB/s when transfer     8 bytes from 0x88360000 to 0x c07ec80 with channel  0, consumes   960 cycles
Packet DMA achieves   20 MB/s when transfer    16 bytes from 0x88380000 to 0x c07ed80 with channel  0, consumes   958 cycles
Packet DMA achieves   30 MB/s when transfer    32 bytes from 0x883a0000 to 0x c07ee80 with channel  0, consumes  1270 cycles
Packet DMA achieves   66 MB/s when transfer    64 bytes from 0x883c0000 to 0x c07ef80 with channel  0, consumes  1148 cycles
Packet DMA achieves  123 MB/s when transfer   128 bytes from 0x883e0000 to 0x c07f080 with channel  0, consumes  1243 cycles
Packet DMA achieves  221 MB/s when transfer   256 bytes from 0x88400000 to 0x c07f180 with channel  0, consumes  1387 cycles
Packet DMA achieves  388 MB/s when transfer   512 bytes from 0x88420000 to 0x c09fa80 with channel  0, consumes  1578 cycles
Packet DMA achieves  610 MB/s when transfer  1024 bytes from 0x88440000 to 0x c09fe80 with channel  0, consumes  2011 cycles
Packet DMA achieves  847 MB/s when transfer  2048 bytes from 0x88460000 to 0x c0ca280 with channel  0, consumes  2896 cycles
Packet DMA achieves 1013 MB/s when transfer  4096 bytes from 0x88280000 to 0x c0cb280 with channel  0, consumes  4843 cycles
Packet DMA achieves 1138 MB/s when transfer  8192 bytes from 0x882a0000 to 0x c0fa280 with channel  0, consumes  8622 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x c07022c to 0x831ca99c with channel  0, consumes   868 cycles
Packet DMA achieves   25 MB/s when transfer    16 bytes from 0x c07424c to 0x831cc9ac with channel  0, consumes   762 cycles
Packet DMA achieves   39 MB/s when transfer    32 bytes from 0x c07223c to 0x831ce9bc with channel  0, consumes   979 cycles
Packet DMA achieves   78 MB/s when transfer    64 bytes from 0x c07625c to 0x831d09cc with channel  0, consumes   983 cycles
Packet DMA achieves  145 MB/s when transfer   128 bytes from 0x c07826c to 0x831d29dc with channel  0, consumes  1053 cycles
Packet DMA achieves  277 MB/s when transfer   256 bytes from 0x c03c08c to 0x831d49ec with channel  0, consumes  1104 cycles
Packet DMA achieves  477 MB/s when transfer   512 bytes from 0x c07a27c to 0x831d69fc with channel  0, consumes  1285 cycles
Packet DMA achieves  705 MB/s when transfer  1024 bytes from 0x c03e09c to 0x831d8a0c with channel  0, consumes  1740 cycles
Packet DMA achieves 1016 MB/s when transfer  2048 bytes from 0x c0400ac to 0x831daa1c with channel  0, consumes  2413 cycles
Packet DMA achieves 1248 MB/s when transfer  4096 bytes from 0x c0420bc to 0x831dca2c with channel  0, consumes  3930 cycles
Packet DMA achieves 1405 MB/s when transfer  8192 bytes from 0x c0440cc to 0x831dea3c with channel  0, consumes  6981 cycles
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x831e0a50 to 0x c0460dc with channel  0, consumes  1128 cycles
Packet DMA achieves   16 MB/s when transfer    16 bytes from 0x831e2a60 to 0x c04a0fc with channel  0, consumes  1139 cycles
Packet DMA achieves   28 MB/s when transfer    32 bytes from 0x831e4a70 to 0x c0480ec with channel  0, consumes  1330 cycles
Packet DMA achieves   59 MB/s when transfer    64 bytes from 0x831e6a80 to 0x c04c10c with channel  0, consumes  1290 cycles
Packet DMA achieves  120 MB/s when transfer   128 bytes from 0x831e8a90 to 0x c04e11c with channel  0, consumes  1270 cycles
Packet DMA achieves  133 MB/s when transfer   256 bytes from 0x831eaaa0 to 0x c05012c with channel  0, consumes  2305 cycles
Packet DMA achieves  410 MB/s when transfer   512 bytes from 0x831ecab0 to 0x c05414c with channel  0, consumes  1494 cycles
Packet DMA achieves  607 MB/s when transfer  1024 bytes from 0x831eeac0 to 0x c05213c with channel  0, consumes  2019 cycles
Packet DMA achieves  845 MB/s when transfer  2048 bytes from 0x831f0ad0 to 0x c05615c with channel  0, consumes  2901 cycles
Packet DMA achieves 1035 MB/s when transfer  4096 bytes from 0x831f2ae0 to 0x c05a17c with channel  0, consumes  4737 cycles
Packet DMA achieves 1033 MB/s when transfer  8192 bytes from 0x831f4af0 to 0x c05816c with channel  0, consumes  9499 cycles
test Packet DMA in PA
host Packet DMA test with 1 channels
Packet DMA achieves    7 MB/s when transfer     8 bytes from 0x c0dc280 to 0x880c3000 with channel  0, consumes  1209 cycles
Packet DMA achieves   16 MB/s when transfer    16 bytes from 0x c0e0280 to 0x880c3100 with channel  0, consumes  1180 cycles
Packet DMA achieves   25 MB/s when transfer    32 bytes from 0x c0de280 to 0x880c3200 with channel  0, consumes  1494 cycles
Packet DMA achieves   52 MB/s when transfer    64 bytes from 0x c0e2280 to 0x880c3300 with channel  0, consumes  1470 cycles
Packet DMA achieves  108 MB/s when transfer   128 bytes from 0x c0e4280 to 0x880c3400 with channel  0, consumes  1409 cycles
Packet DMA achieves  201 MB/s when transfer   256 bytes from 0x c0e8280 to 0x880c3500 with channel  0, consumes  1519 cycles
Packet DMA achieves  346 MB/s when transfer   512 bytes from 0x c0e6280 to 0x8810c000 with channel  0, consumes  1769 cycles
Packet DMA achieves  553 MB/s when transfer  1024 bytes from 0x c0ea280 to 0x8810c800 with channel  0, consumes  2217 cycles
Packet DMA achieves  777 MB/s when transfer  2048 bytes from 0x c0ec280 to 0x8810d000 with channel  0, consumes  3155 cycles
Packet DMA achieves  986 MB/s when transfer  4096 bytes from 0x c0f0280 to 0x881c0000 with channel  0, consumes  4976 cycles
Packet DMA achieves 1188 MB/s when transfer  8192 bytes from 0x c0ee280 to 0x881c4000 with channel  0, consumes  8258 cycles
Packet DMA achieves    5 MB/s when transfer     8 bytes from 0x882c0000 to 0x c07f280 with channel  0, consumes  1858 cycles
Packet DMA achieves   10 MB/s when transfer    16 bytes from 0x882e0000 to 0x c07f380 with channel  0, consumes  1868 cycles
Packet DMA achieves   25 MB/s when transfer    32 bytes from 0x88300000 to 0x c07f480 with channel  0, consumes  1511 cycles
Packet DMA achieves   52 MB/s when transfer    64 bytes from 0x88320000 to 0x c07f580 with channel  0, consumes  1470 cycles
Packet DMA achieves   99 MB/s when transfer   128 bytes from 0x88340000 to 0x c07f680 with channel  0, consumes  1547 cycles
Packet DMA achieves  182 MB/s when transfer   256 bytes from 0x88360000 to 0x c07f780 with channel  0, consumes  1679 cycles
Packet DMA achieves  320 MB/s when transfer   512 bytes from 0x88380000 to 0x c0a0280 with channel  0, consumes  1914 cycles
Packet DMA achieves  484 MB/s when transfer  1024 bytes from 0x883a0000 to 0x c0a0680 with channel  0, consumes  2533 cycles
Packet DMA achieves  651 MB/s when transfer  2048 bytes from 0x883c0000 to 0x c0cc280 with channel  0, consumes  3767 cycles
Packet DMA achieves  804 MB/s when transfer  4096 bytes from 0x883e0000 to 0x c0cd280 with channel  0, consumes  6103 cycles
Packet DMA achieves  905 MB/s when transfer  8192 bytes from 0x88400000 to 0x c0f2280 with channel  0, consumes 10836 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves    6 MB/s when transfer     8 bytes from 0x c05c18c to 0x831f6afc with channel  0, consumes  1448 cycles
Packet DMA achieves   13 MB/s when transfer    16 bytes from 0x c05e19c to 0x831f8b0c with channel  0, consumes  1440 cycles
Packet DMA achieves   31 MB/s when transfer    32 bytes from 0x c0601ac to 0x831fab1c with channel  0, consumes  1207 cycles
Packet DMA achieves   53 MB/s when transfer    64 bytes from 0x c0641cc to 0x831fcb2c with channel  0, consumes  1420 cycles
Packet DMA achieves  123 MB/s when transfer   128 bytes from 0x c0621bc to 0x831feb3c with channel  0, consumes  1243 cycles
Packet DMA achieves  226 MB/s when transfer   256 bytes from 0x c0661dc to 0x83200b4c with channel  0, consumes  1357 cycles
Packet DMA achieves  351 MB/s when transfer   512 bytes from 0x c06c20c to 0x83202b5c with channel  0, consumes  1744 cycles
Packet DMA achieves  587 MB/s when transfer  1024 bytes from 0x c0681ec to 0x83204b6c with channel  0, consumes  2090 cycles
Packet DMA achieves  733 MB/s when transfer  2048 bytes from 0x c06a1fc to 0x83206b7c with channel  0, consumes  3343 cycles
Packet DMA achieves 1032 MB/s when transfer  4096 bytes from 0x c06e21c to 0x83208b8c with channel  0, consumes  4753 cycles
Packet DMA achieves 1047 MB/s when transfer  8192 bytes from 0x c07022c to 0x8320ab9c with channel  0, consumes  9366 cycles
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x8320cbb0 to 0x c07424c with channel  0, consumes  1089 cycles
Packet DMA achieves    9 MB/s when transfer    16 bytes from 0x8320ebc0 to 0x c07223c with channel  0, consumes  1982 cycles
Packet DMA achieves   27 MB/s when transfer    32 bytes from 0x83210bd0 to 0x c07625c with channel  0, consumes  1408 cycles
Packet DMA achieves   47 MB/s when transfer    64 bytes from 0x83212be0 to 0x c07826c with channel  0, consumes  1605 cycles
Packet DMA achieves   91 MB/s when transfer   128 bytes from 0x83214bf0 to 0x c03c08c with channel  0, consumes  1669 cycles
Packet DMA achieves  192 MB/s when transfer   256 bytes from 0x83216c00 to 0x c07a27c with channel  0, consumes  1592 cycles
Packet DMA achieves  318 MB/s when transfer   512 bytes from 0x83218c10 to 0x c03e09c with channel  0, consumes  1924 cycles
Packet DMA achieves  471 MB/s when transfer  1024 bytes from 0x8321ac20 to 0x c0400ac with channel  0, consumes  2600 cycles
Packet DMA achieves  545 MB/s when transfer  2048 bytes from 0x8321cc30 to 0x c0420bc with channel  0, consumes  4500 cycles
Packet DMA achieves  817 MB/s when transfer  4096 bytes from 0x8321ec40 to 0x c0440cc with channel  0, consumes  6003 cycles
Packet DMA achieves  914 MB/s when transfer  8192 bytes from 0x83220c50 to 0x c0460dc with channel  0, consumes 10734 cycles
Test complete
