JTAG ID= 0x0b9a602f. This is a K2E device, version variant = 0
DEVSTAT= 0x00000661. little endian, no boot or I2C slave boot, boot master is ARM core, PLL configuration implies the input clock for core is 100MHz
SmartReflex VID= 46, required core voltage= 0.995V.
Die ID= 0x0600c004, 0x0c00ea85, 0x00000000, 0x79900000
DSP speed grade = 800MHz, ARM speed grade= 800MHz
Enable IRQ and FIQ.
Enable Exception handling...
Initialize main core clock = 100.00MHz/1x12 = 1200MHz
DDR3A initialization
Initialize DDR data rate = 100.000/1*16/4*4= 1600.0 MTS, bus width = 64 bits.
DDR PHY status PGSR0=0xb0000fff.
Queue Push/Pop test on descriptors with internal linking RAM
Queue 2006 push test through Queue Manage Registers
consumes   8288 cycles to push          512 descriptors, average  16 cycles
consumes   3761 cycles to push          256 descriptors, average  14 cycles
consumes   1860 cycles to push          128 descriptors, average  14 cycles
consumes    968 cycles to push           64 descriptors, average  15 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    309 cycles to push           16 descriptors, average  19 cycles
consumes    216 cycles to push            8 descriptors, average  27 cycles
consumes    160 cycles to push            4 descriptors, average  40 cycles
consumes    135 cycles to push            2 descriptors, average  67 cycles
consumes    113 cycles to push            1 descriptors, average 113 cycles
Queue 2006 push test through Queue Manage VBUSM Data Space
consumes   8419 cycles to push          512 descriptors, average  16 cycles
consumes   3763 cycles to push          256 descriptors, average  14 cycles
consumes   1811 cycles to push          128 descriptors, average  14 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    309 cycles to push           16 descriptors, average  19 cycles
consumes    230 cycles to push            8 descriptors, average  28 cycles
consumes    160 cycles to push            4 descriptors, average  40 cycles
consumes    126 cycles to push            2 descriptors, average  63 cycles
consumes    116 cycles to push            1 descriptors, average 116 cycles
Queue 2006 pop test through Queue Manage Registers
consumes  60767 cycles to pop           512 descriptors, average 118 cycles
consumes  30430 cycles to pop           256 descriptors, average 118 cycles
consumes  15263 cycles to pop           128 descriptors, average 119 cycles
consumes   7685 cycles to pop            64 descriptors, average 120 cycles
consumes   3893 cycles to pop            32 descriptors, average 121 cycles
consumes   1997 cycles to pop            16 descriptors, average 124 cycles
consumes   1052 cycles to pop             8 descriptors, average 131 cycles
consumes    578 cycles to pop             4 descriptors, average 144 cycles
consumes    344 cycles to pop             2 descriptors, average 172 cycles
consumes    223 cycles to pop             1 descriptors, average 223 cycles
Queue 2006 pop test through Queue Manage VBUSM Data Space
consumes  64107 cycles to pop           512 descriptors, average 125 cycles
consumes  32038 cycles to pop           256 descriptors, average 125 cycles
consumes  16091 cycles to pop           128 descriptors, average 125 cycles
consumes   8069 cycles to pop            64 descriptors, average 126 cycles
consumes   4109 cycles to pop            32 descriptors, average 128 cycles
consumes   2093 cycles to pop            16 descriptors, average 130 cycles
consumes   1112 cycles to pop             8 descriptors, average 139 cycles
consumes    599 cycles to pop             4 descriptors, average 149 cycles
consumes    356 cycles to pop             2 descriptors, average 178 cycles
consumes    229 cycles to pop             1 descriptors, average 229 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57756 cycles to pop           512 descriptors, average 112 cycles
consumes  28951 cycles to pop           256 descriptors, average 113 cycles
consumes  14513 cycles to pop           128 descriptors, average 113 cycles
consumes   7313 cycles to pop            64 descriptors, average 114 cycles
consumes   3701 cycles to pop            32 descriptors, average 115 cycles
consumes   1901 cycles to pop            16 descriptors, average 118 cycles
consumes   1016 cycles to pop             8 descriptors, average 127 cycles
consumes    557 cycles to pop             4 descriptors, average 139 cycles
consumes    329 cycles to pop             2 descriptors, average 164 cycles
consumes    217 cycles to pop             1 descriptors, average 217 cycles
Queue 2006 push to pop delay test through Queue Manage Registers
consumes  95444 cycles to push and pop  512 descriptors, average 186 cycles
consumes  47724 cycles to push and pop  256 descriptors, average 186 cycles
consumes  23917 cycles to push and pop  128 descriptors, average 186 cycles
consumes  12016 cycles to push and pop   64 descriptors, average 187 cycles
consumes   6061 cycles to push and pop   32 descriptors, average 189 cycles
consumes   3085 cycles to push and pop   16 descriptors, average 192 cycles
consumes   1597 cycles to push and pop    8 descriptors, average 199 cycles
consumes    856 cycles to push and pop    4 descriptors, average 214 cycles
consumes    480 cycles to push and pop    2 descriptors, average 240 cycles
consumes    293 cycles to push and pop    1 descriptors, average 293 cycles
Queue 2006 push to pop delay test through Queue Manage VBUSM Data Space
consumes 106209 cycles to push and pop  512 descriptors, average 207 cycles
consumes  53097 cycles to push and pop  256 descriptors, average 207 cycles
consumes  26608 cycles to push and pop  128 descriptors, average 207 cycles
consumes  13357 cycles to push and pop   64 descriptors, average 208 cycles
consumes   6733 cycles to push and pop   32 descriptors, average 210 cycles
consumes   3421 cycles to push and pop   16 descriptors, average 213 cycles
consumes   1771 cycles to push and pop    8 descriptors, average 221 cycles
consumes    940 cycles to push and pop    4 descriptors, average 235 cycles
consumes    522 cycles to push and pop    2 descriptors, average 261 cycles
consumes    314 cycles to push and pop    1 descriptors, average 314 cycles
Queue Push/Pop test on descriptors with external linking RAM
Queue 2040 push test through Queue Manage Registers
consumes   9702 cycles to push          512 descriptors, average  18 cycles
consumes   4148 cycles to push          256 descriptors, average  16 cycles
consumes   1789 cycles to push          128 descriptors, average  13 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    309 cycles to push           16 descriptors, average  19 cycles
consumes    230 cycles to push            8 descriptors, average  28 cycles
consumes    155 cycles to push            4 descriptors, average  38 cycles
consumes    135 cycles to push            2 descriptors, average  67 cycles
consumes    113 cycles to push            1 descriptors, average 113 cycles
Queue 2040 push test through Queue Manage VBUSM Data Space
consumes   9813 cycles to push          512 descriptors, average  19 cycles
consumes   4172 cycles to push          256 descriptors, average  16 cycles
consumes   1807 cycles to push          128 descriptors, average  14 cycles
consumes    935 cycles to push           64 descriptors, average  14 cycles
consumes    515 cycles to push           32 descriptors, average  16 cycles
consumes    309 cycles to push           16 descriptors, average  19 cycles
consumes    231 cycles to push            8 descriptors, average  28 cycles
consumes    155 cycles to push            4 descriptors, average  38 cycles
consumes    126 cycles to push            2 descriptors, average  63 cycles
consumes    113 cycles to push            1 descriptors, average 113 cycles
Queue 2040 pop test through Queue Manage Registers
consumes  66019 cycles to pop           512 descriptors, average 128 cycles
consumes  33063 cycles to pop           256 descriptors, average 129 cycles
consumes  16565 cycles to pop           128 descriptors, average 129 cycles
consumes   8330 cycles to pop            64 descriptors, average 130 cycles
consumes   4205 cycles to pop            32 descriptors, average 131 cycles
consumes   2147 cycles to pop            16 descriptors, average 134 cycles
consumes   1133 cycles to pop             8 descriptors, average 141 cycles
consumes    611 cycles to pop             4 descriptors, average 152 cycles
consumes    350 cycles to pop             2 descriptors, average 175 cycles
consumes    223 cycles to pop             1 descriptors, average 223 cycles
Queue 2040 pop test through Queue Manage VBUSM Data Space
consumes  66027 cycles to pop           512 descriptors, average 128 cycles
consumes  33078 cycles to pop           256 descriptors, average 129 cycles
consumes  16571 cycles to pop           128 descriptors, average 129 cycles
consumes   8336 cycles to pop            64 descriptors, average 130 cycles
consumes   4220 cycles to pop            32 descriptors, average 131 cycles
consumes   2153 cycles to pop            16 descriptors, average 134 cycles
consumes   1139 cycles to pop             8 descriptors, average 142 cycles
consumes    620 cycles to pop             4 descriptors, average 155 cycles
consumes    356 cycles to pop             2 descriptors, average 178 cycles
consumes    229 cycles to pop             1 descriptors, average 229 cycles
Empty Queue 2037 pop test through Queue Manage Registers
consumes  57768 cycles to pop           512 descriptors, average 112 cycles
consumes  28914 cycles to pop           256 descriptors, average 112 cycles
consumes  14507 cycles to pop           128 descriptors, average 113 cycles
consumes   7307 cycles to pop            64 descriptors, average 114 cycles
consumes   3713 cycles to pop            32 descriptors, average 116 cycles
consumes   1901 cycles to pop            16 descriptors, average 118 cycles
consumes   1016 cycles to pop             8 descriptors, average 127 cycles
consumes    554 cycles to pop             4 descriptors, average 138 cycles
consumes    332 cycles to pop             2 descriptors, average 166 cycles
consumes    217 cycles to pop             1 descriptors, average 217 cycles
Queue 2040 push to pop delay test through Queue Manage Registers
consumes  95446 cycles to push and pop  512 descriptors, average 186 cycles
consumes  47726 cycles to push and pop  256 descriptors, average 186 cycles
consumes  23917 cycles to push and pop  128 descriptors, average 186 cycles
consumes  12013 cycles to push and pop   64 descriptors, average 187 cycles
consumes   6061 cycles to push and pop   32 descriptors, average 189 cycles
consumes   3085 cycles to push and pop   16 descriptors, average 192 cycles
consumes   1597 cycles to push and pop    8 descriptors, average 199 cycles
consumes    856 cycles to push and pop    4 descriptors, average 214 cycles
consumes    480 cycles to push and pop    2 descriptors, average 240 cycles
consumes    293 cycles to push and pop    1 descriptors, average 293 cycles
Queue 2040 push to pop delay test through Queue Manage VBUSM Data Space
consumes 108888 cycles to push and pop  512 descriptors, average 212 cycles
consumes  54434 cycles to push and pop  256 descriptors, average 212 cycles
consumes  27286 cycles to push and pop  128 descriptors, average 213 cycles
consumes  13684 cycles to push and pop   64 descriptors, average 213 cycles
consumes   6898 cycles to push and pop   32 descriptors, average 215 cycles
consumes   3496 cycles to push and pop   16 descriptors, average 218 cycles
consumes   1804 cycles to push and pop    8 descriptors, average 225 cycles
consumes    955 cycles to push and pop    4 descriptors, average 238 cycles
consumes    525 cycles to push and pop    2 descriptors, average 262 cycles
consumes    314 cycles to push and pop    1 descriptors, average 314 cycles

Queue pend interrupt test on descriptors with internal linking RAM
Queue 662 pending interrupt happens at 17953244
consumes   1140 cycles between push queue 662 and pend interrupt
Queue pend interrupt test on descriptors with external linking RAM
Queue 662 pending interrupt happens at 17966739
consumes    633 cycles between push queue 662 and pend interrupt

descriptor Reclamation test in queue 2010
consumes   1051 cycles for one descriptor Reclamation
consumes   1177 cycles for one descriptor Reclamation
consumes   1392 cycles for one descriptor Reclamation
consumes   1272 cycles for one descriptor Reclamation
consumes    648 cycles for one descriptor Reclamation
consumes   1272 cycles for one descriptor Reclamation
consumes   1377 cycles for one descriptor Reclamation
consumes   1377 cycles for one descriptor Reclamation
consumes    753 cycles for one descriptor Reclamation
consumes   1065 cycles for one descriptor Reclamation

Queue Push/accumulation test with ACC48 firmware on INTD1
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18029510
consumes   3690 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18057034
consumes  18004 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18070552
consumes   3471 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18095469
consumes  15655 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18108484
consumes   3048 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18132471
consumes  14971 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18145662
consumes   3474 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18163665
consumes   8965 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18176439
consumes   3240 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18195599
consumes  10165 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18208555
consumes   3306 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18227370
consumes   9883 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18240133
consumes   3378 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18254905
consumes   5659 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18268053
consumes   4012 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18288702
consumes  11731 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18301924
consumes   3748 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18314667
consumes   3847 cycles to push and accumulate one descriptor with  low priority
QMSS INTD1 high priority queue accumulation channel 0 interrupt happens at 18327316
consumes   3574 cycles to push and accumulate one descriptor with high priority
INTD1 low priority queues accumulation channel 0 interrupt happens at 18350035
consumes  13783 cycles to push and accumulate one descriptor with  low priority
test Packet DMA1 in QMSS
host Packet DMA test with 1 channels
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x c0dc280 to 0x84060000 with channel  0, consumes  1068 cycles
Packet DMA achieves   14 MB/s when transfer    16 bytes from 0x c0de280 to 0x84060100 with channel  0, consumes  1363 cycles
Packet DMA achieves   32 MB/s when transfer    32 bytes from 0x c0e0280 to 0x84060200 with channel  0, consumes  1200 cycles
Packet DMA achieves   64 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84060300 with channel  0, consumes  1189 cycles
Packet DMA achieves  138 MB/s when transfer   128 bytes from 0x c0e4280 to 0x84060400 with channel  0, consumes  1113 cycles
Packet DMA achieves  248 MB/s when transfer   256 bytes from 0x c0e6280 to 0x84060500 with channel  0, consumes  1236 cycles
Packet DMA achieves  436 MB/s when transfer   512 bytes from 0x c0e8280 to 0x840a0000 with channel  0, consumes  1409 cycles
Packet DMA achieves  674 MB/s when transfer  1024 bytes from 0x c0ea280 to 0x840a0800 with channel  0, consumes  1823 cycles
Packet DMA achieves  966 MB/s when transfer  2048 bytes from 0x c0ec280 to 0x840a1000 with channel  0, consumes  2544 cycles
Packet DMA achieves 1199 MB/s when transfer  4096 bytes from 0x c0ee280 to 0x84120000 with channel  0, consumes  4098 cycles
Packet DMA achieves 1375 MB/s when transfer  8192 bytes from 0x c0f0280 to 0x84124000 with channel  0, consumes  7149 cycles
Packet DMA achieves    7 MB/s when transfer     8 bytes from 0x84360000 to 0x c07c280 with channel  0, consumes  1357 cycles
Packet DMA achieves   11 MB/s when transfer    16 bytes from 0x84380000 to 0x c07c380 with channel  0, consumes  1658 cycles
Packet DMA achieves   25 MB/s when transfer    32 bytes from 0x843a0000 to 0x c07c480 with channel  0, consumes  1482 cycles
Packet DMA achieves   62 MB/s when transfer    64 bytes from 0x843c0000 to 0x c07c580 with channel  0, consumes  1238 cycles
Packet DMA achieves  116 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07c680 with channel  0, consumes  1313 cycles
Packet DMA achieves  213 MB/s when transfer   256 bytes from 0x84400000 to 0x c07c780 with channel  0, consumes  1437 cycles
Packet DMA achieves  391 MB/s when transfer   512 bytes from 0x84220000 to 0x c09c280 with channel  0, consumes  1570 cycles
Packet DMA achieves  660 MB/s when transfer  1024 bytes from 0x84240000 to 0x c09c680 with channel  0, consumes  1860 cycles
Packet DMA achieves  882 MB/s when transfer  2048 bytes from 0x84260000 to 0x c0bc280 with channel  0, consumes  2786 cycles
Packet DMA achieves 1089 MB/s when transfer  4096 bytes from 0x84280000 to 0x c0bd280 with channel  0, consumes  4512 cycles
Packet DMA achieves 1247 MB/s when transfer  8192 bytes from 0x842a0000 to 0x c0f2280 with channel  0, consumes  7878 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves    9 MB/s when transfer     8 bytes from 0x c03c090 to 0x8023cfec with channel  0, consumes  1000 cycles
Packet DMA achieves   19 MB/s when transfer    16 bytes from 0x c03e0a0 to 0x8023effc with channel  0, consumes   986 cycles
Packet DMA achieves   38 MB/s when transfer    32 bytes from 0x c0400b0 to 0x8024100c with channel  0, consumes  1006 cycles
Packet DMA achieves   80 MB/s when transfer    64 bytes from 0x c0420c0 to 0x8024301c with channel  0, consumes   953 cycles
Packet DMA achieves  148 MB/s when transfer   128 bytes from 0x c0440d0 to 0x8024502c with channel  0, consumes  1033 cycles
Packet DMA achieves  277 MB/s when transfer   256 bytes from 0x c0460e0 to 0x8024703c with channel  0, consumes  1108 cycles
Packet DMA achieves  483 MB/s when transfer   512 bytes from 0x c0480f0 to 0x8024904c with channel  0, consumes  1270 cycles
Packet DMA achieves  753 MB/s when transfer  1024 bytes from 0x c04a100 to 0x8024b05c with channel  0, consumes  1630 cycles
Packet DMA achieves 1041 MB/s when transfer  2048 bytes from 0x c04c110 to 0x8024d06c with channel  0, consumes  2360 cycles
Packet DMA achieves 1265 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8024f07c with channel  0, consumes  3885 cycles
Packet DMA achieves 1412 MB/s when transfer  8192 bytes from 0x c050130 to 0x8025108c with channel  0, consumes  6959 cycles
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x802530a0 to 0x c05213c with channel  0, consumes  1094 cycles
Packet DMA achieves   15 MB/s when transfer    16 bytes from 0x802550b0 to 0x c05414c with channel  0, consumes  1202 cycles
Packet DMA achieves   30 MB/s when transfer    32 bytes from 0x802570c0 to 0x c05615c with channel  0, consumes  1252 cycles
Packet DMA achieves   61 MB/s when transfer    64 bytes from 0x802590d0 to 0x c05816c with channel  0, consumes  1243 cycles
Packet DMA achieves  127 MB/s when transfer   128 bytes from 0x8025b0e0 to 0x c05a17c with channel  0, consumes  1206 cycles
Packet DMA achieves  244 MB/s when transfer   256 bytes from 0x8025d0f0 to 0x c05c18c with channel  0, consumes  1258 cycles
Packet DMA achieves  432 MB/s when transfer   512 bytes from 0x8025f100 to 0x c05e19c with channel  0, consumes  1420 cycles
Packet DMA achieves  606 MB/s when transfer  1024 bytes from 0x80261110 to 0x c0601ac with channel  0, consumes  2026 cycles
Packet DMA achieves  915 MB/s when transfer  2048 bytes from 0x80263120 to 0x c0621bc with channel  0, consumes  2683 cycles
Packet DMA achieves 1116 MB/s when transfer  4096 bytes from 0x80265130 to 0x c0641cc with channel  0, consumes  4404 cycles
Packet DMA achieves 1247 MB/s when transfer  8192 bytes from 0x80267140 to 0x c0661dc with channel  0, consumes  7877 cycles
host Packet DMA test with 2 channels
Packet DMA achieves   13 MB/s when transfer     8 bytes from 0x c0f6280 to 0x84060600 with channel  0, from 0x c0f6280 to 0x84060700 with channel  1, consumes  1449 cycles
Packet DMA achieves   25 MB/s when transfer    16 bytes from 0x c0fa280 to 0x84060800 with channel  0, from 0x c0fa280 to 0x84060900 with channel  1, consumes  1490 cycles
Packet DMA achieves   76 MB/s when transfer    32 bytes from 0x c0de280 to 0x84060a00 with channel  0, from 0x c0de280 to 0x84060b00 with channel  1, consumes  1001 cycles
Packet DMA achieves  134 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84060c00 with channel  0, from 0x c0e2280 to 0x84060d00 with channel  1, consumes  1145 cycles
Packet DMA achieves  276 MB/s when transfer   128 bytes from 0x c0e6280 to 0x84060e00 with channel  0, from 0x c0e6280 to 0x84060f00 with channel  1, consumes  1110 cycles
Packet DMA achieves  484 MB/s when transfer   256 bytes from 0x c0ea280 to 0x84061000 with channel  0, from 0x c0ea280 to 0x84061100 with channel  1, consumes  1269 cycles
Packet DMA achieves  826 MB/s when transfer   512 bytes from 0x c0ee280 to 0x840a1800 with channel  0, from 0x c0ee280 to 0x840a2000 with channel  1, consumes  1487 cycles
Packet DMA achieves 1264 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x840a2800 with channel  0, from 0x c0f2280 to 0x840a3000 with channel  1, consumes  1943 cycles
Packet DMA achieves 1868 MB/s when transfer  2048 bytes from 0x c0f6280 to 0x840a3800 with channel  0, from 0x c0f6280 to 0x840a4000 with channel  1, consumes  2631 cycles
Packet DMA achieves 2372 MB/s when transfer  4096 bytes from 0x c0fa280 to 0x84128000 with channel  0, from 0x c0fa280 to 0x8412c000 with channel  1, consumes  4143 cycles
Packet DMA achieves 2740 MB/s when transfer  8192 bytes from 0x c0de280 to 0x84130000 with channel  0, from 0x c0de280 to 0x84134000 with channel  1, consumes  7175 cycles
Packet DMA achieves   11 MB/s when transfer     8 bytes from 0x842e0000 to 0x c07c880 with channel  0, from 0x842e0000 to 0x c07c980 with channel  1, consumes  1733 cycles
Packet DMA achieves   22 MB/s when transfer    16 bytes from 0x84320000 to 0x c07ca80 with channel  0, from 0x84320000 to 0x c07cb80 with channel  1, consumes  1690 cycles
Packet DMA achieves   69 MB/s when transfer    32 bytes from 0x84360000 to 0x c07cc80 with channel  0, from 0x84360000 to 0x c07cd80 with channel  1, consumes  1105 cycles
Packet DMA achieves  124 MB/s when transfer    64 bytes from 0x843a0000 to 0x c07ce80 with channel  0, from 0x843a0000 to 0x c07cf80 with channel  1, consumes  1237 cycles
Packet DMA achieves  250 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07d080 with channel  0, from 0x843e0000 to 0x c07d180 with channel  1, consumes  1224 cycles
Packet DMA achieves  416 MB/s when transfer   256 bytes from 0x84220000 to 0x c07d280 with channel  0, from 0x84220000 to 0x c07d380 with channel  1, consumes  1476 cycles
Packet DMA achieves  610 MB/s when transfer   512 bytes from 0x84260000 to 0x c09ca80 with channel  0, from 0x84260000 to 0x c09ce80 with channel  1, consumes  2013 cycles
Packet DMA achieves  816 MB/s when transfer  1024 bytes from 0x842a0000 to 0x c09d280 with channel  0, from 0x842a0000 to 0x c09d680 with channel  1, consumes  3011 cycles
Packet DMA achieves 1049 MB/s when transfer  2048 bytes from 0x842e0000 to 0x c0be280 with channel  0, from 0x842e0000 to 0x c0bf280 with channel  1, consumes  4684 cycles
Packet DMA achieves 1149 MB/s when transfer  4096 bytes from 0x84320000 to 0x c0c0280 with channel  0, from 0x84320000 to 0x c0c1280 with channel  1, consumes  8549 cycles
Packet DMA achieves 1204 MB/s when transfer  8192 bytes from 0x84360000 to 0x c0e0280 with channel  0, from 0x84360000 to 0x c0e2280 with channel  1, consumes 16326 cycles
monolithic Packet DMA test with 2 channels
Packet DMA achieves   19 MB/s when transfer     8 bytes from 0x c06a200 to 0x8026914c with channel  0, from 0x c06a200 to 0x8026b15c with channel  1, consumes  1010 cycles
Packet DMA achieves   30 MB/s when transfer    16 bytes from 0x c06e220 to 0x8026d16c with channel  0, from 0x c06e220 to 0x8026f17c with channel  1, consumes  1248 cycles
Packet DMA achieves   68 MB/s when transfer    32 bytes from 0x c072240 to 0x8027118c with channel  0, from 0x c072240 to 0x8027319c with channel  1, consumes  1127 cycles
Packet DMA achieves  152 MB/s when transfer    64 bytes from 0x c076260 to 0x802751ac with channel  0, from 0x c076260 to 0x802771bc with channel  1, consumes  1010 cycles
Packet DMA achieves  297 MB/s when transfer   128 bytes from 0x c07a280 to 0x802791cc with channel  0, from 0x c07a280 to 0x8027b1dc with channel  1, consumes  1031 cycles
Packet DMA achieves  524 MB/s when transfer   256 bytes from 0x c03e0a0 to 0x8027d1ec with channel  0, from 0x c03e0a0 to 0x8027f1fc with channel  1, consumes  1171 cycles
Packet DMA achieves  889 MB/s when transfer   512 bytes from 0x c0420c0 to 0x8028120c with channel  0, from 0x c0420c0 to 0x8028321c with channel  1, consumes  1381 cycles
Packet DMA achieves 1610 MB/s when transfer  1024 bytes from 0x c0460e0 to 0x8028522c with channel  0, from 0x c0460e0 to 0x8028723c with channel  1, consumes  1526 cycles
Packet DMA achieves 2071 MB/s when transfer  2048 bytes from 0x c04a100 to 0x8028924c with channel  0, from 0x c04a100 to 0x8028b25c with channel  1, consumes  2373 cycles
Packet DMA achieves 2566 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8028d26c with channel  0, from 0x c04e120 to 0x8028f27c with channel  1, consumes  3830 cycles
Packet DMA achieves 2853 MB/s when transfer  8192 bytes from 0x c05213c to 0x8029128c with channel  0, from 0x c05213c to 0x8029329c with channel  1, consumes  6889 cycles
Packet DMA achieves   12 MB/s when transfer     8 bytes from 0x802972c0 to 0x c05414c with channel  0, from 0x802972c0 to 0x c05615c with channel  1, consumes  1509 cycles
Packet DMA achieves   26 MB/s when transfer    16 bytes from 0x8029b2e0 to 0x c05816c with channel  0, from 0x8029b2e0 to 0x c05a17c with channel  1, consumes  1448 cycles
Packet DMA achieves   54 MB/s when transfer    32 bytes from 0x8029f300 to 0x c05c18c with channel  0, from 0x8029f300 to 0x c05e19c with channel  1, consumes  1403 cycles
Packet DMA achieves  119 MB/s when transfer    64 bytes from 0x802a3320 to 0x c0601ac with channel  0, from 0x802a3320 to 0x c0621bc with channel  1, consumes  1284 cycles
Packet DMA achieves  254 MB/s when transfer   128 bytes from 0x802a7340 to 0x c0641cc with channel  0, from 0x802a7340 to 0x c0661dc with channel  1, consumes  1205 cycles
Packet DMA achieves  460 MB/s when transfer   256 bytes from 0x802ab360 to 0x c0681ec with channel  0, from 0x802ab360 to 0x c06a1fc with channel  1, consumes  1335 cycles
Packet DMA achieves  840 MB/s when transfer   512 bytes from 0x802af380 to 0x c06c20c with channel  0, from 0x802af380 to 0x c06e21c with channel  1, consumes  1462 cycles
Packet DMA achieves 1423 MB/s when transfer  1024 bytes from 0x802b33a0 to 0x c07022c with channel  0, from 0x802b33a0 to 0x c07223c with channel  1, consumes  1726 cycles
Packet DMA achieves 1843 MB/s when transfer  2048 bytes from 0x802b73c0 to 0x c07424c with channel  0, from 0x802b73c0 to 0x c07625c with channel  1, consumes  2666 cycles
Packet DMA achieves 2205 MB/s when transfer  4096 bytes from 0x802bb3e0 to 0x c07826c with channel  0, from 0x802bb3e0 to 0x c07a27c with channel  1, consumes  4457 cycles
Packet DMA achieves 2449 MB/s when transfer  8192 bytes from 0x802bf400 to 0x c03c08c with channel  0, from 0x802bf400 to 0x c03e09c with channel  1, consumes  8025 cycles
host Packet DMA test with 4 channels
Packet DMA achieves   36 MB/s when transfer     8 bytes from 0x c0ea280 to 0x84061200 with channel  0, from 0x c0ea280 to 0x84061300 with channel  1, from 0x c0ea280 to 0x84061400 with channel  2, from 0x c0ea280 to 0x84061500 with channel  3, consumes  1049 cycles
Packet DMA achieves   74 MB/s when transfer    16 bytes from 0x c0f2280 to 0x84061600 with channel  0, from 0x c0f2280 to 0x84061700 with channel  1, from 0x c0f2280 to 0x84061800 with channel  2, from 0x c0f2280 to 0x84061900 with channel  3, consumes  1033 cycles
Packet DMA achieves  148 MB/s when transfer    32 bytes from 0x c0fa280 to 0x84061a00 with channel  0, from 0x c0fa280 to 0x84061b00 with channel  1, from 0x c0fa280 to 0x84061c00 with channel  2, from 0x c0fa280 to 0x84061d00 with channel  3, consumes  1036 cycles
Packet DMA achieves  289 MB/s when transfer    64 bytes from 0x c0e2280 to 0x84061e00 with channel  0, from 0x c0e2280 to 0x84061f00 with channel  1, from 0x c0e2280 to 0x84062000 with channel  2, from 0x c0e2280 to 0x84062100 with channel  3, consumes  1061 cycles
Packet DMA achieves  525 MB/s when transfer   128 bytes from 0x c0ea280 to 0x84062200 with channel  0, from 0x c0ea280 to 0x84062300 with channel  1, from 0x c0ea280 to 0x84062400 with channel  2, from 0x c0ea280 to 0x84062500 with channel  3, consumes  1170 cycles
Packet DMA achieves  893 MB/s when transfer   256 bytes from 0x c0f2280 to 0x84062600 with channel  0, from 0x c0f2280 to 0x84062700 with channel  1, from 0x c0f2280 to 0x84062800 with channel  2, from 0x c0f2280 to 0x84062900 with channel  3, consumes  1376 cycles
Packet DMA achieves 1582 MB/s when transfer   512 bytes from 0x c0fa280 to 0x840a4800 with channel  0, from 0x c0fa280 to 0x840a5000 with channel  1, from 0x c0fa280 to 0x840a5800 with channel  2, from 0x c0fa280 to 0x840a6000 with channel  3, consumes  1553 cycles
Packet DMA achieves 2442 MB/s when transfer  1024 bytes from 0x c0e2280 to 0x840a6800 with channel  0, from 0x c0e2280 to 0x840a7000 with channel  1, from 0x c0e2280 to 0x840a7800 with channel  2, from 0x c0e2280 to 0x840a8000 with channel  3, consumes  2012 cycles
Packet DMA achieves 3591 MB/s when transfer  2048 bytes from 0x c0ea280 to 0x840a8800 with channel  0, from 0x c0ea280 to 0x840a9000 with channel  1, from 0x c0ea280 to 0x840a9800 with channel  2, from 0x c0ea280 to 0x840aa000 with channel  3, consumes  2737 cycles
Packet DMA achieves 4550 MB/s when transfer  4096 bytes from 0x c0f2280 to 0x84138000 with channel  0, from 0x c0f2280 to 0x8413c000 with channel  1, from 0x c0f2280 to 0x84140000 with channel  2, from 0x c0f2280 to 0x84144000 with channel  3, consumes  4321 cycles
Packet DMA achieves 5339 MB/s when transfer  8192 bytes from 0x c0fa280 to 0x84148000 with channel  0, from 0x c0fa280 to 0x8414c000 with channel  1, from 0x c0fa280 to 0x84150000 with channel  2, from 0x c0fa280 to 0x84154000 with channel  3, consumes  7364 cycles
Packet DMA achieves   32 MB/s when transfer     8 bytes from 0x843e0000 to 0x c07d480 with channel  0, from 0x843e0000 to 0x c07d580 with channel  1, from 0x843e0000 to 0x c07d680 with channel  2, from 0x843e0000 to 0x c07d780 with channel  3, consumes  1180 cycles
Packet DMA achieves   66 MB/s when transfer    16 bytes from 0x84260000 to 0x c07d880 with channel  0, from 0x84260000 to 0x c07d980 with channel  1, from 0x84260000 to 0x c07da80 with channel  2, from 0x84260000 to 0x c07db80 with channel  3, consumes  1155 cycles
Packet DMA achieves  128 MB/s when transfer    32 bytes from 0x842e0000 to 0x c07dc80 with channel  0, from 0x842e0000 to 0x c07dd80 with channel  1, from 0x842e0000 to 0x c07de80 with channel  2, from 0x842e0000 to 0x c07df80 with channel  3, consumes  1199 cycles
Packet DMA achieves  241 MB/s when transfer    64 bytes from 0x84360000 to 0x c07e080 with channel  0, from 0x84360000 to 0x c07e180 with channel  1, from 0x84360000 to 0x c07e280 with channel  2, from 0x84360000 to 0x c07e380 with channel  3, consumes  1273 cycles
Packet DMA achieves  472 MB/s when transfer   128 bytes from 0x843e0000 to 0x c07e480 with channel  0, from 0x843e0000 to 0x c07e580 with channel  1, from 0x843e0000 to 0x c07e680 with channel  2, from 0x843e0000 to 0x c07e780 with channel  3, consumes  1299 cycles
Packet DMA achieves  687 MB/s when transfer   256 bytes from 0x84260000 to 0x c07e880 with channel  0, from 0x84260000 to 0x c07e980 with channel  1, from 0x84260000 to 0x c07ea80 with channel  2, from 0x84260000 to 0x c07eb80 with channel  3, consumes  1788 cycles
Packet DMA achieves  936 MB/s when transfer   512 bytes from 0x842e0000 to 0x c09da80 with channel  0, from 0x842e0000 to 0x c09de80 with channel  1, from 0x842e0000 to 0x c09e280 with channel  2, from 0x842e0000 to 0x c09e680 with channel  3, consumes  2623 cycles
Packet DMA achieves 1133 MB/s when transfer  1024 bytes from 0x84360000 to 0x c09ea80 with channel  0, from 0x84360000 to 0x c09ee80 with channel  1, from 0x84360000 to 0x c09f280 with channel  2, from 0x84360000 to 0x c09f680 with channel  3, consumes  4337 cycles
Packet DMA achieves 1245 MB/s when transfer  2048 bytes from 0x843e0000 to 0x c0c2280 with channel  0, from 0x843e0000 to 0x c0c3280 with channel  1, from 0x843e0000 to 0x c0c4280 with channel  2, from 0x843e0000 to 0x c0c5280 with channel  3, consumes  7893 cycles
Packet DMA achieves 1428 MB/s when transfer  4096 bytes from 0x84260000 to 0x c0c6280 with channel  0, from 0x84260000 to 0x c0c7280 with channel  1, from 0x84260000 to 0x c0c8280 with channel  2, from 0x84260000 to 0x c0c9280 with channel  3, consumes 13765 cycles
Packet DMA achieves 1211 MB/s when transfer  8192 bytes from 0x842e0000 to 0x c0dc280 with channel  0, from 0x842e0000 to 0x c0de280 with channel  1, from 0x842e0000 to 0x c0e0280 with channel  2, from 0x842e0000 to 0x c0e2280 with channel  3, consumes 32459 cycles
monolithic Packet DMA test with 4 channels
Packet DMA achieves   41 MB/s when transfer     8 bytes from 0x c0460e0 to 0x802c140c with channel  0, from 0x c0460e0 to 0x802c341c with channel  1, from 0x c0460e0 to 0x802c542c with channel  2, from 0x c0460e0 to 0x802c743c with channel  3, consumes   932 cycles
Packet DMA achieves   82 MB/s when transfer    16 bytes from 0x c04e120 to 0x802c944c with channel  0, from 0x c04e120 to 0x802cb45c with channel  1, from 0x c04e120 to 0x802cd46c with channel  2, from 0x c04e120 to 0x802cf47c with channel  3, consumes   930 cycles
Packet DMA achieves  162 MB/s when transfer    32 bytes from 0x c05615c to 0x802d148c with channel  0, from 0x c05615c to 0x802d349c with channel  1, from 0x c05615c to 0x802d54ac with channel  2, from 0x c05615c to 0x802d74bc with channel  3, consumes   943 cycles
Packet DMA achieves  326 MB/s when transfer    64 bytes from 0x c05e19c to 0x802d94cc with channel  0, from 0x c05e19c to 0x802db4dc with channel  1, from 0x c05e19c to 0x802dd4ec with channel  2, from 0x c05e19c to 0x802df4fc with channel  3, consumes   942 cycles
Packet DMA achieves  645 MB/s when transfer   128 bytes from 0x c0661dc to 0x802e150c with channel  0, from 0x c0661dc to 0x802e351c with channel  1, from 0x c0661dc to 0x802e552c with channel  2, from 0x c0661dc to 0x802e753c with channel  3, consumes   952 cycles
Packet DMA achieves 1044 MB/s when transfer   256 bytes from 0x c06e21c to 0x802e954c with channel  0, from 0x c06e21c to 0x802eb55c with channel  1, from 0x c06e21c to 0x802ed56c with channel  2, from 0x c06e21c to 0x802ef57c with channel  3, consumes  1177 cycles
Packet DMA achieves 1778 MB/s when transfer   512 bytes from 0x c07625c to 0x802f158c with channel  0, from 0x c07625c to 0x802f359c with channel  1, from 0x c07625c to 0x802f55ac with channel  2, from 0x c07625c to 0x802f75bc with channel  3, consumes  1382 cycles
Packet DMA achieves 2718 MB/s when transfer  1024 bytes from 0x c03e09c to 0x802f95cc with channel  0, from 0x c03e09c to 0x802fb5dc with channel  1, from 0x c03e09c to 0x802fd5ec with channel  2, from 0x c03e09c to 0x802ff5fc with channel  3, consumes  1808 cycles
Packet DMA achieves 3907 MB/s when transfer  2048 bytes from 0x c0460e0 to 0x8030160c with channel  0, from 0x c0460e0 to 0x8030361c with channel  1, from 0x c0460e0 to 0x8030562c with channel  2, from 0x c0460e0 to 0x8030763c with channel  3, consumes  2516 cycles
Packet DMA achieves 4777 MB/s when transfer  4096 bytes from 0x c04e120 to 0x8030964c with channel  0, from 0x c04e120 to 0x8030b65c with channel  1, from 0x c04e120 to 0x8030d66c with channel  2, from 0x c04e120 to 0x8030f67c with channel  3, consumes  4115 cycles
Packet DMA achieves 5499 MB/s when transfer  8192 bytes from 0x c05615c to 0x8031168c with channel  0, from 0x c05615c to 0x8031369c with channel  1, from 0x c05615c to 0x803156ac with channel  2, from 0x c05615c to 0x803176bc with channel  3, consumes  7150 cycles
Packet DMA achieves   36 MB/s when transfer     8 bytes from 0x8031f700 to 0x c05816c with channel  0, from 0x8031f700 to 0x c05a17c with channel  1, from 0x8031f700 to 0x c05c18c with channel  2, from 0x8031f700 to 0x c05e19c with channel  3, consumes  1056 cycles
Packet DMA achieves   72 MB/s when transfer    16 bytes from 0x80327740 to 0x c0601ac with channel  0, from 0x80327740 to 0x c0641cc with channel  1, from 0x80327740 to 0x c0621bc with channel  2, from 0x80327740 to 0x c0661dc with channel  3, consumes  1061 cycles
Packet DMA achieves  145 MB/s when transfer    32 bytes from 0x8032f780 to 0x c06c20c with channel  0, from 0x8032f780 to 0x c0681ec with channel  1, from 0x8032f780 to 0x c06a1fc with channel  2, from 0x8032f780 to 0x c06e21c with channel  3, consumes  1057 cycles
Packet DMA achieves  291 MB/s when transfer    64 bytes from 0x803377c0 to 0x c07424c with channel  0, from 0x803377c0 to 0x c07022c with channel  1, from 0x803377c0 to 0x c07223c with channel  2, from 0x803377c0 to 0x c07625c with channel  3, consumes  1055 cycles
Packet DMA achieves  583 MB/s when transfer   128 bytes from 0x8033f800 to 0x c03c08c with channel  0, from 0x8033f800 to 0x c07826c with channel  1, from 0x8033f800 to 0x c07a27c with channel  2, from 0x8033f800 to 0x c03e09c with channel  3, consumes  1053 cycles
Packet DMA achieves  985 MB/s when transfer   256 bytes from 0x80347840 to 0x c0440cc with channel  0, from 0x80347840 to 0x c0400ac with channel  1, from 0x80347840 to 0x c0420bc with channel  2, from 0x80347840 to 0x c0460dc with channel  3, consumes  1247 cycles
Packet DMA achieves 1687 MB/s when transfer   512 bytes from 0x8034f880 to 0x c04c10c with channel  0, from 0x8034f880 to 0x c0480ec with channel  1, from 0x8034f880 to 0x c04a0fc with channel  2, from 0x8034f880 to 0x c04e11c with channel  3, consumes  1456 cycles
Packet DMA achieves 2604 MB/s when transfer  1024 bytes from 0x803578c0 to 0x c05414c with channel  0, from 0x803578c0 to 0x c05012c with channel  1, from 0x803578c0 to 0x c05213c with channel  2, from 0x803578c0 to 0x c05615c with channel  3, consumes  1887 cycles
Packet DMA achieves 3478 MB/s when transfer  2048 bytes from 0x8035f900 to 0x c05816c with channel  0, from 0x8035f900 to 0x c05a17c with channel  1, from 0x8035f900 to 0x c05e19c with channel  2, from 0x8035f900 to 0x c05c18c with channel  3, consumes  2826 cycles
Packet DMA achieves 4242 MB/s when transfer  4096 bytes from 0x80367940 to 0x c0601ac with channel  0, from 0x80367940 to 0x c0641cc with channel  1, from 0x80367940 to 0x c0661dc with channel  2, from 0x80367940 to 0x c0621bc with channel  3, consumes  4634 cycles
Packet DMA achieves 4571 MB/s when transfer  8192 bytes from 0x8036f980 to 0x c06c20c with channel  0, from 0x8036f980 to 0x c0681ec with channel  1, from 0x8036f980 to 0x c06a1fc with channel  2, from 0x8036f980 to 0x c06e21c with channel  3, consumes  8602 cycles
test Packet DMA in PA
host Packet DMA test with 1 channels
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x c0e4280 to 0x84062a00 with channel  0, consumes  1120 cycles
Packet DMA achieves   17 MB/s when transfer    16 bytes from 0x c0e6280 to 0x84062b00 with channel  0, consumes  1095 cycles
Packet DMA achieves   28 MB/s when transfer    32 bytes from 0x c0e8280 to 0x84062c00 with channel  0, consumes  1370 cycles
Packet DMA achieves   58 MB/s when transfer    64 bytes from 0x c0ea280 to 0x84062d00 with channel  0, consumes  1321 cycles
Packet DMA achieves  116 MB/s when transfer   128 bytes from 0x c0ec280 to 0x84062e00 with channel  0, consumes  1315 cycles
Packet DMA achieves  217 MB/s when transfer   256 bytes from 0x c0ee280 to 0x84062f00 with channel  0, consumes  1414 cycles
Packet DMA achieves  369 MB/s when transfer   512 bytes from 0x c0f0280 to 0x840aa800 with channel  0, consumes  1661 cycles
Packet DMA achieves  661 MB/s when transfer  1024 bytes from 0x c0f2280 to 0x840ab000 with channel  0, consumes  1857 cycles
Packet DMA achieves  883 MB/s when transfer  2048 bytes from 0x c0f4280 to 0x840ab800 with channel  0, consumes  2782 cycles
Packet DMA achieves 1130 MB/s when transfer  4096 bytes from 0x c0f6280 to 0x84158000 with channel  0, consumes  4348 cycles
Packet DMA achieves 1333 MB/s when transfer  8192 bytes from 0x c0f8280 to 0x8415c000 with channel  0, consumes  7370 cycles
Packet DMA achieves    8 MB/s when transfer     8 bytes from 0x84300000 to 0x c07ec80 with channel  0, consumes  1170 cycles
Packet DMA achieves   16 MB/s when transfer    16 bytes from 0x84320000 to 0x c07ed80 with channel  0, consumes  1164 cycles
Packet DMA achieves   26 MB/s when transfer    32 bytes from 0x84340000 to 0x c07ee80 with channel  0, consumes  1435 cycles
Packet DMA achieves   58 MB/s when transfer    64 bytes from 0x84360000 to 0x c07ef80 with channel  0, consumes  1312 cycles
Packet DMA achieves  109 MB/s when transfer   128 bytes from 0x84380000 to 0x c07f080 with channel  0, consumes  1409 cycles
Packet DMA achieves  203 MB/s when transfer   256 bytes from 0x843a0000 to 0x c07f180 with channel  0, consumes  1510 cycles
Packet DMA achieves  348 MB/s when transfer   512 bytes from 0x843c0000 to 0x c09fa80 with channel  0, consumes  1762 cycles
Packet DMA achieves  580 MB/s when transfer  1024 bytes from 0x843e0000 to 0x c09fe80 with channel  0, consumes  2115 cycles
Packet DMA achieves  854 MB/s when transfer  2048 bytes from 0x84400000 to 0x c0ca280 with channel  0, consumes  2877 cycles
Packet DMA achieves 1142 MB/s when transfer  4096 bytes from 0x84220000 to 0x c0cb280 with channel  0, consumes  4301 cycles
Packet DMA achieves 1319 MB/s when transfer  8192 bytes from 0x84240000 to 0x c0fa280 with channel  0, consumes  7452 cycles
monolithic Packet DMA test with 1 channels
Packet DMA achieves    7 MB/s when transfer     8 bytes from 0x c07424c to 0x8037198c with channel  0, consumes  1291 cycles
Packet DMA achieves   14 MB/s when transfer    16 bytes from 0x c07022c to 0x8037399c with channel  0, consumes  1300 cycles
Packet DMA achieves   33 MB/s when transfer    32 bytes from 0x c07223c to 0x803759ac with channel  0, consumes  1162 cycles
Packet DMA achieves   65 MB/s when transfer    64 bytes from 0x c07625c to 0x803779bc with channel  0, consumes  1168 cycles
Packet DMA achieves  138 MB/s when transfer   128 bytes from 0x c03c08c to 0x803799cc with channel  0, consumes  1111 cycles
Packet DMA achieves  248 MB/s when transfer   256 bytes from 0x c07826c to 0x8037b9dc with channel  0, consumes  1238 cycles
Packet DMA achieves  425 MB/s when transfer   512 bytes from 0x c07a27c to 0x8037d9ec with channel  0, consumes  1445 cycles
Packet DMA achieves  635 MB/s when transfer  1024 bytes from 0x c03e09c to 0x8037f9fc with channel  0, consumes  1934 cycles
Packet DMA achieves  939 MB/s when transfer  2048 bytes from 0x c0440cc to 0x80381a0c with channel  0, consumes  2615 cycles
Packet DMA achieves 1192 MB/s when transfer  4096 bytes from 0x c0400ac to 0x80383a1c with channel  0, consumes  4122 cycles
Packet DMA achieves 1376 MB/s when transfer  8192 bytes from 0x c0420bc to 0x80385a2c with channel  0, consumes  7140 cycles
Packet DMA achieves    5 MB/s when transfer     8 bytes from 0x80387a40 to 0x c0460dc with channel  0, consumes  1655 cycles
Packet DMA achieves   18 MB/s when transfer    16 bytes from 0x80389a50 to 0x c04c10c with channel  0, consumes  1059 cycles
Packet DMA achieves   31 MB/s when transfer    32 bytes from 0x8038ba60 to 0x c0480ec with channel  0, consumes  1232 cycles
Packet DMA achieves   57 MB/s when transfer    64 bytes from 0x8038da70 to 0x c04a0fc with channel  0, consumes  1344 cycles
Packet DMA achieves  103 MB/s when transfer   128 bytes from 0x8038fa80 to 0x c04e11c with channel  0, consumes  1482 cycles
Packet DMA achieves  196 MB/s when transfer   256 bytes from 0x80391a90 to 0x c05414c with channel  0, consumes  1565 cycles
Packet DMA achieves  390 MB/s when transfer   512 bytes from 0x80393aa0 to 0x c05012c with channel  0, consumes  1575 cycles
Packet DMA achieves  569 MB/s when transfer  1024 bytes from 0x80395ab0 to 0x c05213c with channel  0, consumes  2159 cycles
Packet DMA achieves  915 MB/s when transfer  2048 bytes from 0x80397ac0 to 0x c05615c with channel  0, consumes  2683 cycles
Packet DMA achieves 1171 MB/s when transfer  4096 bytes from 0x80399ad0 to 0x c05816c with channel  0, consumes  4194 cycles
Packet DMA achieves 1353 MB/s when transfer  8192 bytes from 0x8039bae0 to 0x c05a17c with channel  0, consumes  7265 cycles
Test complete
