JTAG ID= 0x0b9a702f. This is a K2L device, version variant = 0
DEVSTAT= 0x0e000ee1. little endian, no boot or I2C slave boot, boot master is ARM core, PLL configuration implies the input clock for core is 122.88MHz
SmartReflex VID= 46, required core voltage= 0.995V.
Die ID= 0x0400500a, 0x0c00ea81, 0x00000000, 0x5f260020
DSP speed grade = 1200MHz, ARM speed grade= 1200MHz
Enable IRQ and FIQ.
Enable Exception handling...
Initialize main core clock = 100.00MHz/1x12 = 1200MHz
Initialize ARM clock = 100.00MHz/1x12 = 1200MHz
DDR3A initialization
Initialize DDR data rate = 100.000/1*16/4*4= 1600.0 MTS, bus width = 64 bits.
DDR PHY status PGSR0=0xb0000fff.
Initializing NAND flash...
Manufacturer ID = 2ch, Device ID = a5h
NAND FLASH size = 4096 x 64 x 4096 = 1073741824 Bytes
Save data from 0x3fc00000 to 0x40000000.
Erasing blocks 4080 through 4095
Passed Memory Fill Test from 0x3fc00000 to 0x40000000 with pattern 0x       0
Erasing blocks 4080 through 4095
Passed Memory Fill Test from 0x3fc00000 to 0x40000000 with pattern 0xaaaaaaaa
Erasing blocks 4080 through 4095
Passed Memory Fill Test from 0x3fc00000 to 0x40000000 with pattern 0x55555555
Erasing blocks 4080 through 4095
Passed Memory Address Test from 0x3fc00000 to 0x40000000
Erasing blocks 4080 through 4095
Restore data from 0x3fc00000 to 0x40000000.
FLASH test complete.
