JTAG ID= 0x0b9a702f. This is a K2L device, version variant = 0
DEVSTAT= 0x0e000ee1. little endian, no boot or I2C slave boot, boot master is ARM core, PLL configuration implies the input clock for core is 122.88MHz
SmartReflex VID= 46, required core voltage= 0.995V.
Die ID= 0x0400500a, 0x0c00ea81, 0x00000000, 0x5f260020
DSP speed grade = 1200MHz, ARM speed grade= 1200MHz
Enable IRQ and FIQ.
Enable Exception handling...
Initialize main core clock = 100.00MHz/1x12 = 1200MHz
Initialize ARM clock = 100.00MHz/1x12 = 1200MHz
DDR3A initialization
Initialize DDR data rate = 100.000/1*16/4*4= 1600.0 MTS, bus width = 64 bits.
DDR PHY status PGSR0=0xb0000fff.
Memory Test Start at 7693916 cycle

Disable instruction and data cache.

MSMC RAM bus test at 8831775 cycle
Passed Times:        1 		Failed Times:        0 

OSR bus test at 9755536 cycle
Passed Times:        2 		Failed Times:        0 

DDR3A bus test at 10043676 cycle
Passed Times:        3 		Failed Times:        0 

Enable Instruction cache only.

MSMC RAM memory test at 10288048 cycle
Memory Fill Test from 0x c039680 to 0x c180000 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x c039680 to 0x c180000
Memory Bit Walking from 0x c039680 to 0x c180000
 0x0000000100000001 		 0xfffffffefffffffe
 0x0000000200000002 		 0xfffffffdfffffffd
 0x0000000400000004 		 0xfffffffbfffffffb
 0x0000000800000008 		 0xfffffff7fffffff7
 0x0000001000000010 		 0xffffffefffffffef
 0x0000002000000020 		 0xffffffdfffffffdf
 0x0000004000000040 		 0xffffffbfffffffbf
 0x0000008000000080 		 0xffffff7fffffff7f
 0x0000010000000100 		 0xfffffefffffffeff
 0x0000020000000200 		 0xfffffdfffffffdff
 0x0000040000000400 		 0xfffffbfffffffbff
 0x0000080000000800 		 0xfffff7fffffff7ff
 0x0000100000001000 		 0xffffefffffffefff
 0x0000200000002000 		 0xffffdfffffffdfff
 0x0000400000004000 		 0xffffbfffffffbfff
 0x0000800000008000 		 0xffff7fffffff7fff
 0x0001000000010000 		 0xfffefffffffeffff
 0x0002000000020000 		 0xfffdfffffffdffff
 0x0004000000040000 		 0xfffbfffffffbffff
 0x0008000000080000 		 0xfff7fffffff7ffff
 0x0010000000100000 		 0xffefffffffefffff
 0x0020000000200000 		 0xffdfffffffdfffff
 0x0040000000400000 		 0xffbfffffffbfffff
 0x0080000000800000 		 0xff7fffffff7fffff
 0x0100000001000000 		 0xfefffffffeffffff
 0x0200000002000000 		 0xfdfffffffdffffff
 0x0400000004000000 		 0xfbfffffffbffffff
 0x0800000008000000 		 0xf7fffffff7ffffff
 0x1000000010000000 		 0xefffffffefffffff
 0x2000000020000000 		 0xdfffffffdfffffff
 0x4000000040000000 		 0xbfffffffbfffffff
 0x8000000080000000 		 0x7fffffff7fffffff
Passed Times:        4 		Failed Times:        0 

OSR memory test at 2380312628 cycle
Memory Fill Test from 0x70000000 to 0x70080000 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x70000000 to 0x70080000
Memory Bit Walking from 0x70000000 to 0x70080000
Passed Times:        5 		Failed Times:        0 

DDR3A memory test at 3587088480 cycle
Memory Fill Test from 0x80000000 to 0x80000400 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x80000000 to 0x80000400
Memory Bit Walking from 0x80000000 to 0x80000400
Passed Times:        6 		Failed Times:        0 

Enable both data and instruction cache.

MSMC RAM memory test with EDMA at 3590044656 cycle
Memory Fill Test from 0x c039680 to 0x c180000 with patterns:
 0x0000000000000000 by EDMA CC0 TC0
 0xffffffffffffffff by EDMA CC1 TC0
 0xaaaaaaaaaaaaaaaa by EDMA CC1 TC2
 0x5555555555555555 by EDMA CC2 TC0
Passed Memory Address Test from 0x c039680 to 0x c180000 with EDMA CC2 TC2
Memory Bit Walking from 0x c039680 to 0x c180000 with EDMA
 0x0000000100000001 with CC0 TC0
 0xfffffffefffffffe with CC1 TC0
 0x0000000200000002 with CC1 TC2
 0xfffffffdfffffffd with CC2 TC0
 0x0000000400000004 with CC2 TC2
 0xfffffffbfffffffb with CC0 TC0
 0x0000000800000008 with CC1 TC0
 0xfffffff7fffffff7 with CC1 TC2
 0x0000001000000010 with CC2 TC0
 0xffffffefffffffef with CC2 TC2
 0x0000002000000020 with CC0 TC0
 0xffffffdfffffffdf with CC1 TC0
 0x0000004000000040 with CC1 TC2
 0xffffffbfffffffbf with CC2 TC0
 0x0000008000000080 with CC2 TC2
 0xffffff7fffffff7f with CC0 TC0
 0x0000010000000100 with CC1 TC0
 0xfffffefffffffeff with CC1 TC2
 0x0000020000000200 with CC2 TC0
 0xfffffdfffffffdff with CC2 TC2
 0x0000040000000400 with CC0 TC0
 0xfffffbfffffffbff with CC1 TC0
 0x0000080000000800 with CC1 TC2
 0xfffff7fffffff7ff with CC2 TC0
 0x0000100000001000 with CC2 TC2
 0xffffefffffffefff with CC0 TC0
 0x0000200000002000 with CC1 TC0
 0xffffdfffffffdfff with CC1 TC2
 0x0000400000004000 with CC2 TC0
 0xffffbfffffffbfff with CC2 TC2
 0x0000800000008000 with CC0 TC0
 0xffff7fffffff7fff with CC1 TC0
 0x0001000000010000 with CC1 TC2
 0xfffefffffffeffff with CC2 TC0
 0x0002000000020000 with CC2 TC2
 0xfffdfffffffdffff with CC0 TC0
 0x0004000000040000 with CC1 TC0
 0xfffbfffffffbffff with CC1 TC2
 0x0008000000080000 with CC2 TC0
 0xfff7fffffff7ffff with CC2 TC2
 0x0010000000100000 with CC0 TC0
 0xffefffffffefffff with CC1 TC0
 0x0020000000200000 with CC1 TC2
 0xffdfffffffdfffff with CC2 TC0
 0x0040000000400000 with CC2 TC2
 0xffbfffffffbfffff with CC0 TC0
 0x0080000000800000 with CC1 TC0
 0xff7fffffff7fffff with CC1 TC2
 0x0100000001000000 with CC2 TC0
 0xfefffffffeffffff with CC2 TC2
 0x0200000002000000 with CC0 TC0
 0xfdfffffffdffffff with CC1 TC0
 0x0400000004000000 with CC1 TC2
 0xfbfffffffbffffff with CC2 TC0
 0x0800000008000000 with CC2 TC2
 0xf7fffffff7ffffff with CC0 TC0
 0x1000000010000000 with CC1 TC0
 0xefffffffefffffff with CC1 TC2
 0x2000000020000000 with CC2 TC0
 0xdfffffffdfffffff with CC2 TC2
 0x4000000040000000 with CC0 TC0
 0xbfffffffbfffffff with CC1 TC0
 0x8000000080000000 with CC1 TC2
 0x7fffffff7fffffff with CC2 TC0
Passed Times:        7 		Failed Times:        0 

MSMC RAM memory test at 3705315860 cycle
Memory Fill Test from 0x c039680 to 0x c180000 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x c039680 to 0x c180000
Memory Bit Walking from 0x c039680 to 0x c180000
 0x0000000100000001 		 0xfffffffefffffffe
 0x0000000200000002 		 0xfffffffdfffffffd
 0x0000000400000004 		 0xfffffffbfffffffb
 0x0000000800000008 		 0xfffffff7fffffff7
 0x0000001000000010 		 0xffffffefffffffef
 0x0000002000000020 		 0xffffffdfffffffdf
 0x0000004000000040 		 0xffffffbfffffffbf
 0x0000008000000080 		 0xffffff7fffffff7f
 0x0000010000000100 		 0xfffffefffffffeff
 0x0000020000000200 		 0xfffffdfffffffdff
 0x0000040000000400 		 0xfffffbfffffffbff
 0x0000080000000800 		 0xfffff7fffffff7ff
 0x0000100000001000 		 0xffffefffffffefff
 0x0000200000002000 		 0xffffdfffffffdfff
 0x0000400000004000 		 0xffffbfffffffbfff
 0x0000800000008000 		 0xffff7fffffff7fff
 0x0001000000010000 		 0xfffefffffffeffff
 0x0002000000020000 		 0xfffdfffffffdffff
 0x0004000000040000 		 0xfffbfffffffbffff
 0x0008000000080000 		 0xfff7fffffff7ffff
 0x0010000000100000 		 0xffefffffffefffff
 0x0020000000200000 		 0xffdfffffffdfffff
 0x0040000000400000 		 0xffbfffffffbfffff
 0x0080000000800000 		 0xff7fffffff7fffff
 0x0100000001000000 		 0xfefffffffeffffff
 0x0200000002000000 		 0xfdfffffffdffffff
 0x0400000004000000 		 0xfbfffffffbffffff
 0x0800000008000000 		 0xf7fffffff7ffffff
 0x1000000010000000 		 0xefffffffefffffff
 0x2000000020000000 		 0xdfffffffdfffffff
 0x4000000040000000 		 0xbfffffffbfffffff
 0x8000000080000000 		 0x7fffffff7fffffff
Passed Times:        8 		Failed Times:        0 

OSR memory test with EDMA at 3813645447 cycle
Memory Fill Test from 0x70000000 to 0x70080000 with patterns:
 0x0000000000000000 by EDMA CC2 TC2
 0xffffffffffffffff by EDMA CC0 TC0
 0xaaaaaaaaaaaaaaaa by EDMA CC1 TC0
 0x5555555555555555 by EDMA CC1 TC2
Passed Memory Address Test from 0x70000000 to 0x70080000 with EDMA CC2 TC0
Memory Bit Walking from 0x70000000 to 0x70080000 with EDMA
Passed Times:        9 		Failed Times:        0 

OSR memory test at 3857681726 cycle
Memory Fill Test from 0x70000000 to 0x70080000 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x70000000 to 0x70080000
Memory Bit Walking from 0x70000000 to 0x70080000
Passed Times:       10 		Failed Times:        0 

DDR3A memory test with EDMA at 3896296219 cycle
Memory Fill Test from 0x80000000 to 0xc0000000 with patterns:
 0x0000000000000000 by EDMA CC2 TC0
 0xffffffffffffffff by EDMA CC2 TC2
 0xaaaaaaaaaaaaaaaa by EDMA CC0 TC0
 0x5555555555555555 by EDMA CC1 TC0
Passed Memory Address Test from 0x80000000 to 0xc0000000 with EDMA CC1 TC2
Memory Bit Walking from 0x80000000 to 0xc0000000 with EDMA
 0x0000000100000001 with CC2 TC0
 0xfffffffefffffffe with CC2 TC2
 0x0000000200000002 with CC0 TC0
 0xfffffffdfffffffd with CC1 TC0
 0x0000000400000004 with CC1 TC2
 0xfffffffbfffffffb with CC2 TC0
 0x0000000800000008 with CC2 TC2
 0xfffffff7fffffff7 with CC0 TC0
 0x0000001000000010 with CC1 TC0
 0xffffffefffffffef with CC1 TC2
 0x0000002000000020 with CC2 TC0
 0xffffffdfffffffdf with CC2 TC2
 0x0000004000000040 with CC0 TC0
 0xffffffbfffffffbf with CC1 TC0
 0x0000008000000080 with CC1 TC2
 0xffffff7fffffff7f with CC2 TC0
 0x0000010000000100 with CC2 TC2
 0xfffffefffffffeff with CC0 TC0
 0x0000020000000200 with CC1 TC0
 0xfffffdfffffffdff with CC1 TC2
 0x0000040000000400 with CC2 TC0
 0xfffffbfffffffbff with CC2 TC2
 0x0000080000000800 with CC0 TC0
 0xfffff7fffffff7ff with CC1 TC0
 0x0000100000001000 with CC1 TC2
 0xffffefffffffefff with CC2 TC0
 0x0000200000002000 with CC2 TC2
 0xffffdfffffffdfff with CC0 TC0
 0x0000400000004000 with CC1 TC0
 0xffffbfffffffbfff with CC1 TC2
 0x0000800000008000 with CC2 TC0
 0xffff7fffffff7fff with CC2 TC2
 0x0001000000010000 with CC0 TC0
 0xfffefffffffeffff with CC1 TC0
 0x0002000000020000 with CC1 TC2
 0xfffdfffffffdffff with CC2 TC0
 0x0004000000040000 with CC2 TC2
 0xfffbfffffffbffff with CC0 TC0
 0x0008000000080000 with CC1 TC0
 0xfff7fffffff7ffff with CC1 TC2
 0x0010000000100000 with CC2 TC0
 0xffefffffffefffff with CC2 TC2
 0x0020000000200000 with CC0 TC0
 0xffdfffffffdfffff with CC1 TC0
 0x0040000000400000 with CC1 TC2
 0xffbfffffffbfffff with CC2 TC0
 0x0080000000800000 with CC2 TC2
 0xff7fffffff7fffff with CC0 TC0
 0x0100000001000000 with CC1 TC0
 0xfefffffffeffffff with CC1 TC2
 0x0200000002000000 with CC2 TC0
 0xfdfffffffdffffff with CC2 TC2
 0x0400000004000000 with CC0 TC0
 0xfbfffffffbffffff with CC1 TC0
 0x0800000008000000 with CC1 TC2
 0xf7fffffff7ffffff with CC2 TC0
 0x1000000010000000 with CC2 TC2
 0xefffffffefffffff with CC0 TC0
 0x2000000020000000 with CC1 TC0
 0xdfffffffdfffffff with CC1 TC2
 0x4000000040000000 with CC2 TC0
 0xbfffffffbfffffff with CC2 TC2
 0x8000000080000000 with CC0 TC0
 0x7fffffff7fffffff with CC1 TC0
Passed Times:       11 		Failed Times:        0 

DDR3A memory test at 96074813720 cycle
Memory Fill Test from 0x80000000 to 0x80400000 with patterns:
 0x0000000000000000
 0xffffffffffffffff
 0xaaaaaaaaaaaaaaaa
 0x5555555555555555
 0xcccccccccccccccc
 0xf0f0f0f0f0f0f0f0
 0xff00ff00ff00ff00
 0xffff0000ffff0000
 0xffffffff00000000
Passed Memory Address Test from 0x80000000 to 0x80400000
Memory Bit Walking from 0x80000000 to 0x80400000
 0x0000000100000001 		 0xfffffffefffffffe
 0x0000000200000002 		 0xfffffffdfffffffd
 0x0000000400000004 		 0xfffffffbfffffffb
 0x0000000800000008 		 0xfffffff7fffffff7
 0x0000001000000010 		 0xffffffefffffffef
 0x0000002000000020 		 0xffffffdfffffffdf
 0x0000004000000040 		 0xffffffbfffffffbf
 0x0000008000000080 		 0xffffff7fffffff7f
 0x0000010000000100 		 0xfffffefffffffeff
 0x0000020000000200 		 0xfffffdfffffffdff
 0x0000040000000400 		 0xfffffbfffffffbff
 0x0000080000000800 		 0xfffff7fffffff7ff
 0x0000100000001000 		 0xffffefffffffefff
 0x0000200000002000 		 0xffffdfffffffdfff
 0x0000400000004000 		 0xffffbfffffffbfff
 0x0000800000008000 		 0xffff7fffffff7fff
 0x0001000000010000 		 0xfffefffffffeffff
 0x0002000000020000 		 0xfffdfffffffdffff
 0x0004000000040000 		 0xfffbfffffffbffff
 0x0008000000080000 		 0xfff7fffffff7ffff
 0x0010000000100000 		 0xffefffffffefffff
 0x0020000000200000 		 0xffdfffffffdfffff
 0x0040000000400000 		 0xffbfffffffbfffff
 0x0080000000800000 		 0xff7fffffff7fffff
 0x0100000001000000 		 0xfefffffffeffffff
 0x0200000002000000 		 0xfdfffffffdffffff
 0x0400000004000000 		 0xfbfffffffbffffff
 0x0800000008000000 		 0xf7fffffff7ffffff
 0x1000000010000000 		 0xefffffffefffffff
 0x2000000020000000 		 0xdfffffffdfffffff
 0x4000000040000000 		 0xbfffffffbfffffff
 0x8000000080000000 		 0x7fffffff7fffffff
Passed Times:       12 		Failed Times:        0 
Memory test complete at 96431062438 cycle
