//*****************************************************************************
//
// Copyright (C) 2012 - 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//  Redistributions of source code must retain the above copyright
//  notice, this list of conditions and the following disclaimer.
//
//  Redistributions in binary form must reproduce the above copyright
//  notice, this list of conditions and the following disclaimer in the
//  documentation and/or other materials provided with the
//  distribution.
//
//  Neither the name of Texas Instruments Incorporated nor the names of
//  its contributors may be used to endorse or promote products derived
//  from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//****************************************************************************

/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430FR2476 devices.
*
********************************************************************/





/* ============================================================================ */
/* Copyright (c) 2013, Texas Instruments Incorporated                           */
/*  All rights reserved.                                                        */
/*                                                                              */
/*  Redistribution and use in source and binary forms, with or without          */
/*  modification, are permitted provided that the following conditions          */
/*  are met:                                                                    */
/*                                                                              */
/*  *  Redistributions of source code must retain the above copyright           */
/*     notice, this list of conditions and the following disclaimer.            */
/*                                                                              */
/*  *  Redistributions in binary form must reproduce the above copyright        */
/*     notice, this list of conditions and the following disclaimer in the      */
/*     documentation and/or other materials provided with the distribution.     */
/*                                                                              */
/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
/*     its contributors may be used to endorse or promote products derived      */
/*     from this software without specific prior written permission.            */
/*                                                                              */
/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
/* ============================================================================ */

/*----------------------------------------------------------------------------*/
/* INTRINSIC MAPPING FOR IAR V1.XX                                            */
/*----------------------------------------------------------------------------*/




/* External references resolved by a device-specific linker command file */
//#define SFR_20BIT(address)  extern volatile unsigned int address
typedef void (* __SFR_FARPTR)();


/************************************************************
* STANDARD BITS
************************************************************/


/************************************************************
* STATUS REGISTER BITS
************************************************************/


/* Low Power Modes coded with Bits 4-7 in SR */


/*****************************************************************************/
/*  INTRINSICS.H                                                             */
/*                                                                           */
/* Copyright (c) 2005 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


/*---------------------------------------------------------------------------*/
/* Handle legacy conflicts                                                   */
/*---------------------------------------------------------------------------*/
/*****************************************************************************/
/*  INTRINSICS_LEGACY_UNDEFS.H                                               */
/*                                                                           */
/* Copyright (c) 2005 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


/*---------------------------------------------------------------------------*/
/* Handle in430.h conflicts with legacy intrinsic names                      */
/*---------------------------------------------------------------------------*/



/*---------------------------------------------------------------------------*/
/* General MSP Intrinsics                                                    */
/*---------------------------------------------------------------------------*/
void           __no_operation(void);

unsigned short __bic_SR_register         (unsigned short mask);
unsigned short __bic_SR_register_on_exit (unsigned short mask);
unsigned short __bis_SR_register         (unsigned short mask);
unsigned short __bis_SR_register_on_exit (unsigned short mask);
unsigned short __get_SR_register         (void);
unsigned short __get_SR_register_on_exit (void);

unsigned short __get_SP_register(void);
void           __set_SP_register(unsigned short value);

void           __delay_cycles(unsigned long cycles);

unsigned int   __even_in_range(unsigned int val, unsigned int range);

void           __op_code(unsigned short op);

/*---------------------------------------------------------------------------*/
/* General MSP Macros                                                        */
/*---------------------------------------------------------------------------*/

/*---------------------------------------------------------------------------*/
/* MSP430/430X Intrinsics                                                    */
/*---------------------------------------------------------------------------*/
void             __disable_interrupt(void);
void             __enable_interrupt(void);
void             __set_interrupt_state(unsigned short state);

unsigned short   __get_R4_register(void);
void             __set_R4_register(unsigned short value);
unsigned short   __get_R5_register(void);
void             __set_R5_register(unsigned short value);

unsigned short   __bcd_add_short(unsigned short, unsigned short);
unsigned long    __bcd_add_long(unsigned long, unsigned long);

unsigned short   __swap_bytes(unsigned short a);

/*---------------------------------------------------------------------------*/
/* MSP430/430X Macros                                                        */
/*---------------------------------------------------------------------------*/



/*---------------------------------------------------------------------------*/
/* MSP430X Intrinsics                                                        */
/*---------------------------------------------------------------------------*/
void           __data16_write_addr(unsigned short, unsigned long);
unsigned long  __data16_read_addr(unsigned short);
void           __data20_write_char(unsigned long, unsigned char);
void           __data20_write_short(unsigned long, unsigned short);
void           __data20_write_long(unsigned long, unsigned long);
unsigned char  __data20_read_char(unsigned long);
unsigned short __data20_read_short(unsigned long);
unsigned long  __data20_read_long(unsigned long);


/*---------------------------------------------------------------------------*/
/* Legacy Macros                                                             */
/*---------------------------------------------------------------------------*/




/************************************************************
* PERIPHERAL FILE MAP
************************************************************/


/*****************************************************************************
 ADC Registers
*****************************************************************************/


extern volatile unsigned int ADCCTL0;                                      /* ADC Control 0 */
extern volatile unsigned char ADCCTL0_L;
extern volatile unsigned char ADCCTL0_H;
extern volatile unsigned int ADCCTL1;                                      /* ADC Control 1 */
extern volatile unsigned char ADCCTL1_L;
extern volatile unsigned char ADCCTL1_H;
extern volatile unsigned int ADCCTL2;                                      /* ADC Control 2 */
extern volatile unsigned char ADCCTL2_L;
extern volatile unsigned char ADCCTL2_H;
extern volatile unsigned int ADCLO;                                        /* ADC Window Comparator Low Threshold Register */
extern volatile unsigned char ADCLO_L;
extern volatile unsigned char ADCLO_H;
extern volatile unsigned int ADCHI;                                        /* ADC Window Comparator High Threshold Register */
extern volatile unsigned char ADCHI_L;
extern volatile unsigned char ADCHI_H;
extern volatile unsigned int ADCMCTL0;                                     /* ADC Conversion Memory Control Register */
extern volatile unsigned char ADCMCTL0_L;
extern volatile unsigned char ADCMCTL0_H;
extern volatile unsigned int ADCMEM0;                                      /* ADC Conversion Memory Register */
extern volatile unsigned char ADCMEM0_L;
extern volatile unsigned char ADCMEM0_H;
extern volatile unsigned int ADCIE;                                        /* ADC Interrupt Enable 0 */
extern volatile unsigned char ADCIE_L;
extern volatile unsigned char ADCIE_H;
extern volatile unsigned int ADCIFG;                                       /* ADC Interrupt Flag */
extern volatile unsigned char ADCIFG_L;
extern volatile unsigned char ADCIFG_H;
extern volatile unsigned int ADCIV;                                        /* ADC Interrupt Vector */
extern volatile unsigned char ADCIV_L;
extern volatile unsigned char ADCIV_H;

/* ADC Register Offsets */

/* ADC Control Bits */

/* ADCCTL0 Control Bits */

/* ADCCTL1 Control Bits */

/* ADCCTL2 Control Bits */

/* ADCLO Control Bits */

/* ADCHI Control Bits */

/* ADCMCTL0 Control Bits */

/* ADCMEM0 Control Bits */

/* ADCIE Control Bits */

/* ADCIFG Control Bits */

/* ADCIV Control Bits */


/*****************************************************************************
 BKMEM Registers
*****************************************************************************/


extern volatile unsigned int BAKMEM0;                                      /* Backup Memory registers. Backup Memory 0. */
extern volatile unsigned char BAKMEM0_L;
extern volatile unsigned char BAKMEM0_H;
extern volatile unsigned int BAKMEM1;                                      /* Backup Memory 1. */
extern volatile unsigned char BAKMEM1_L;
extern volatile unsigned char BAKMEM1_H;
extern volatile unsigned int BAKMEM2;                                      /* Backup Memory 2. */
extern volatile unsigned char BAKMEM2_L;
extern volatile unsigned char BAKMEM2_H;
extern volatile unsigned int BAKMEM3;                                      /* Backup Memory 3. */
extern volatile unsigned char BAKMEM3_L;
extern volatile unsigned char BAKMEM3_H;
extern volatile unsigned int BAKMEM4;                                      /* Backup Memory 4. */
extern volatile unsigned char BAKMEM4_L;
extern volatile unsigned char BAKMEM4_H;
extern volatile unsigned int BAKMEM5;                                      /* Backup Memory 5. */
extern volatile unsigned char BAKMEM5_L;
extern volatile unsigned char BAKMEM5_H;
extern volatile unsigned int BAKMEM6;                                      /* Backup Memory 6. */
extern volatile unsigned char BAKMEM6_L;
extern volatile unsigned char BAKMEM6_H;
extern volatile unsigned int BAKMEM7;                                      /* Backup Memory 7. */
extern volatile unsigned char BAKMEM7_L;
extern volatile unsigned char BAKMEM7_H;
extern volatile unsigned int BAKMEM8;                                      /* Backup Memory 8. */
extern volatile unsigned char BAKMEM8_L;
extern volatile unsigned char BAKMEM8_H;
extern volatile unsigned int BAKMEM9;                                      /* Backup Memory 9. */
extern volatile unsigned char BAKMEM9_L;
extern volatile unsigned char BAKMEM9_H;
extern volatile unsigned int BAKMEM10;                                     /* Backup Memory registers. Backup Memory 10. */
extern volatile unsigned char BAKMEM10_L;
extern volatile unsigned char BAKMEM10_H;
extern volatile unsigned int BAKMEM11;                                     /* Backup Memory 11. */
extern volatile unsigned char BAKMEM11_L;
extern volatile unsigned char BAKMEM11_H;
extern volatile unsigned int BAKMEM12;                                     /* Backup Memory 12. */
extern volatile unsigned char BAKMEM12_L;
extern volatile unsigned char BAKMEM12_H;
extern volatile unsigned int BAKMEM13;                                     /* Backup Memory 13. */
extern volatile unsigned char BAKMEM13_L;
extern volatile unsigned char BAKMEM13_H;
extern volatile unsigned int BAKMEM14;                                     /* Backup Memory 14. */
extern volatile unsigned char BAKMEM14_L;
extern volatile unsigned char BAKMEM14_H;
extern volatile unsigned int BAKMEM15;                                     /* Backup Memory 15. */
extern volatile unsigned char BAKMEM15_L;
extern volatile unsigned char BAKMEM15_H;

/* BKMEM Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 CRC Registers
*****************************************************************************/


extern volatile unsigned int CRCDI;                                        /* CRC Data In */
extern volatile unsigned char CRCDI_L;
extern volatile unsigned char CRCDI_H;
extern volatile unsigned int CRCDIRB;                                      /* CRC Data In Reverse Byte */
extern volatile unsigned char CRCDIRB_L;
extern volatile unsigned char CRCDIRB_H;
extern volatile unsigned int CRCINIRES;                                    /* CRC Initialization and Result */
extern volatile unsigned char CRCINIRES_L;
extern volatile unsigned char CRCINIRES_H;
extern volatile unsigned int CRCRESR;                                      /* CRC Result Reverse */
extern volatile unsigned char CRCRESR_L;
extern volatile unsigned char CRCRESR_H;

/* CRC Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 CS Registers
*****************************************************************************/


extern volatile unsigned int CSCTL0;                                       /* Clock System Control 0 */
extern volatile unsigned char CSCTL0_L;
extern volatile unsigned char CSCTL0_H;
extern volatile unsigned int CSCTL1;                                       /* Clock System Control 1 */
extern volatile unsigned char CSCTL1_L;
extern volatile unsigned char CSCTL1_H;
extern volatile unsigned int CSCTL2;                                       /* Clock System Control 2 */
extern volatile unsigned char CSCTL2_L;
extern volatile unsigned char CSCTL2_H;
extern volatile unsigned int CSCTL3;                                       /* Clock System Control 3 */
extern volatile unsigned char CSCTL3_L;
extern volatile unsigned char CSCTL3_H;
extern volatile unsigned int CSCTL4;                                       /* Clock System Control 4 */
extern volatile unsigned char CSCTL4_L;
extern volatile unsigned char CSCTL4_H;
extern volatile unsigned int CSCTL5;                                       /* Clock System Control 5 */
extern volatile unsigned char CSCTL5_L;
extern volatile unsigned char CSCTL5_H;
extern volatile unsigned int CSCTL6;                                       /* Clock System Control 6 */
extern volatile unsigned char CSCTL6_L;
extern volatile unsigned char CSCTL6_H;
extern volatile unsigned int CSCTL7;                                       /* Clock System Control Register 7 */
extern volatile unsigned char CSCTL7_L;
extern volatile unsigned char CSCTL7_H;
extern volatile unsigned int CSCTL8;                                       /* Clock System Control Register 8 */
extern volatile unsigned char CSCTL8_L;
extern volatile unsigned char CSCTL8_H;

/* CS Register Offsets */

/* CS Control Bits */

/* CSCTL0 Control Bits */

/* CSCTL1 Control Bits */

/* CSCTL2 Control Bits */

/* CSCTL3 Control Bits */

/* CSCTL4 Control Bits */

/* CSCTL5 Control Bits */

/* CSCTL6 Control Bits */

/* CSCTL7 Control Bits */

/* CSCTL8 Control Bits */


/*****************************************************************************
 DIO Registers
*****************************************************************************/


extern volatile unsigned int PAIN;                                         /* Port A Input */
extern volatile unsigned char PAIN_L;
extern volatile unsigned char PAIN_H;
extern volatile unsigned int PAOUT;                                        /* Port A Output */
extern volatile unsigned char PAOUT_L;
extern volatile unsigned char PAOUT_H;
extern volatile unsigned int PADIR;                                        /* Port A Direction */
extern volatile unsigned char PADIR_L;
extern volatile unsigned char PADIR_H;
extern volatile unsigned int PAREN;                                        /* Port A Resistor Enable */
extern volatile unsigned char PAREN_L;
extern volatile unsigned char PAREN_H;
extern volatile unsigned int PASEL0;                                       /* Port A Select 0 */
extern volatile unsigned char PASEL0_L;
extern volatile unsigned char PASEL0_H;
extern volatile unsigned int PASEL1;                                       /* Port A Select 1 */
extern volatile unsigned char PASEL1_L;
extern volatile unsigned char PASEL1_H;
extern volatile unsigned int P1IV;                                         /* Port 1 Interrupt Vector Register */
extern volatile unsigned char P1IV_L;
extern volatile unsigned char P1IV_H;
extern volatile unsigned int PASELC;                                       /* Port A Complement Select */
extern volatile unsigned char PASELC_L;
extern volatile unsigned char PASELC_H;
extern volatile unsigned int PAIES;                                        /* Port A Interrupt Edge Select */
extern volatile unsigned char PAIES_L;
extern volatile unsigned char PAIES_H;
extern volatile unsigned int PAIE;                                         /* Port A Interrupt Enable */
extern volatile unsigned char PAIE_L;
extern volatile unsigned char PAIE_H;
extern volatile unsigned int PAIFG;                                        /* Port A Interrupt Flag */
extern volatile unsigned char PAIFG_L;
extern volatile unsigned char PAIFG_H;
extern volatile unsigned int P2IV;                                         /* Port 2 Interrupt Vector Register */
extern volatile unsigned char P2IV_L;
extern volatile unsigned char P2IV_H;
extern volatile unsigned int PBIN;                                         /* Port B Input */
extern volatile unsigned char PBIN_L;
extern volatile unsigned char PBIN_H;
extern volatile unsigned int PBOUT;                                        /* Port B Output */
extern volatile unsigned char PBOUT_L;
extern volatile unsigned char PBOUT_H;
extern volatile unsigned int PBDIR;                                        /* Port B Direction */
extern volatile unsigned char PBDIR_L;
extern volatile unsigned char PBDIR_H;
extern volatile unsigned int PBREN;                                        /* Port B Resistor Enable */
extern volatile unsigned char PBREN_L;
extern volatile unsigned char PBREN_H;
extern volatile unsigned int PBSEL0;                                       /* Port B Select 0 */
extern volatile unsigned char PBSEL0_L;
extern volatile unsigned char PBSEL0_H;
extern volatile unsigned int PBSEL1;                                       /* Port B Select 1 */
extern volatile unsigned char PBSEL1_L;
extern volatile unsigned char PBSEL1_H;
extern volatile unsigned int P3IV;                                         /* Port 3 Interrupt Vector Register */
extern volatile unsigned char P3IV_L;
extern volatile unsigned char P3IV_H;
extern volatile unsigned int PBSELC;                                       /* Port B Complement Select */
extern volatile unsigned char PBSELC_L;
extern volatile unsigned char PBSELC_H;
extern volatile unsigned int PBIES;                                        /* Port B Interrupt Edge Select */
extern volatile unsigned char PBIES_L;
extern volatile unsigned char PBIES_H;
extern volatile unsigned int PBIE;                                         /* Port B Interrupt Enable */
extern volatile unsigned char PBIE_L;
extern volatile unsigned char PBIE_H;
extern volatile unsigned int PBIFG;                                        /* Port B Interrupt Flag */
extern volatile unsigned char PBIFG_L;
extern volatile unsigned char PBIFG_H;
extern volatile unsigned int P4IV;                                         /* Port 4 Interrupt Vector Register */
extern volatile unsigned char P4IV_L;
extern volatile unsigned char P4IV_H;
extern volatile unsigned int PCIN;                                         /* Port C Input */
extern volatile unsigned char PCIN_L;
extern volatile unsigned char PCIN_H;
extern volatile unsigned int PCOUT;                                        /* Port C Output */
extern volatile unsigned char PCOUT_L;
extern volatile unsigned char PCOUT_H;
extern volatile unsigned int PCDIR;                                        /* Port C Direction */
extern volatile unsigned char PCDIR_L;
extern volatile unsigned char PCDIR_H;
extern volatile unsigned int PCREN;                                        /* Port C Resistor Enable */
extern volatile unsigned char PCREN_L;
extern volatile unsigned char PCREN_H;
extern volatile unsigned int PCSEL0;                                       /* Port C Select 0 */
extern volatile unsigned char PCSEL0_L;
extern volatile unsigned char PCSEL0_H;
extern volatile unsigned int PCSEL1;                                       /* Port C Select 1 */
extern volatile unsigned char PCSEL1_L;
extern volatile unsigned char PCSEL1_H;
extern volatile unsigned int P5IV;                                         /* Port 5 Interrupt Vector Register */
extern volatile unsigned char P5IV_L;
extern volatile unsigned char P5IV_H;
extern volatile unsigned int PCSELC;                                       /* Port C Complement Select */
extern volatile unsigned char PCSELC_L;
extern volatile unsigned char PCSELC_H;
extern volatile unsigned int PCIES;                                        /* Port C Interrupt Edge Select */
extern volatile unsigned char PCIES_L;
extern volatile unsigned char PCIES_H;
extern volatile unsigned int PCIE;                                         /* Port C Interrupt Enable */
extern volatile unsigned char PCIE_L;
extern volatile unsigned char PCIE_H;
extern volatile unsigned int PCIFG;                                        /* Port C Interrupt Flag */
extern volatile unsigned char PCIFG_L;
extern volatile unsigned char PCIFG_H;
extern volatile unsigned int P6IV;                                         /* Port 6 Interrupt Vector Register */
extern volatile unsigned char P6IV_L;
extern volatile unsigned char P6IV_H;
extern volatile unsigned int PJIN;                                         /* Port J Input */
extern volatile unsigned char PJIN_L;
extern volatile unsigned char PJIN_H;
extern volatile unsigned int PJOUT;                                        /* Port J Output */
extern volatile unsigned char PJOUT_L;
extern volatile unsigned char PJOUT_H;
extern volatile unsigned int PJDIR;                                        /* Port J Direction */
extern volatile unsigned char PJDIR_L;
extern volatile unsigned char PJDIR_H;
extern volatile unsigned int PJREN;                                        /* Port J Resistor Enable */
extern volatile unsigned char PJREN_L;
extern volatile unsigned char PJREN_H;
extern volatile unsigned int PJSEL0;                                       /* Port J Select 0 */
extern volatile unsigned char PJSEL0_L;
extern volatile unsigned char PJSEL0_H;
extern volatile unsigned int PJSEL1;                                       /* Port J Select 1 */
extern volatile unsigned char PJSEL1_L;
extern volatile unsigned char PJSEL1_H;
extern volatile unsigned int PJSELC;                                       /* Port J Complement Select */
extern volatile unsigned char PJSELC_L;
extern volatile unsigned char PJSELC_H;
extern volatile unsigned char P1IN;                                          /* Port 1 Input */
extern volatile unsigned char P2IN;                                          /* Port 2 Input */
extern volatile unsigned char P2OUT;                                         /* Port 2 Output */
extern volatile unsigned char P1OUT;                                         /* Port 1 Output */
extern volatile unsigned char P1DIR;                                         /* Port 1 Direction */
extern volatile unsigned char P2DIR;                                         /* Port 2 Direction */
extern volatile unsigned char P1REN;                                         /* Port 1 Resistor Enable */
extern volatile unsigned char P2REN;                                         /* Port 2 Resistor Enable */
extern volatile unsigned char P1SEL0;                                        /* Port 1 Select 0 */
extern volatile unsigned char P2SEL0;                                        /* Port 2 Select 0 */
extern volatile unsigned char P1SEL1;                                        /* Port 1 Select 1 */
extern volatile unsigned char P2SEL1;                                        /* Port 2 Select 1 */
extern volatile unsigned char P1SELC;                                        /* Port 1 Complement Select */
extern volatile unsigned char P2SELC;                                        /* Port 2 Complement Select */
extern volatile unsigned char P1IES;                                         /* Port 1 Interrupt Edge Select */
extern volatile unsigned char P2IES;                                         /* Port 2 Interrupt Edge Select */
extern volatile unsigned char P1IE;                                          /* Port 1 Interrupt Enable */
extern volatile unsigned char P2IE;                                          /* Port 2 Interrupt Enable */
extern volatile unsigned char P1IFG;                                         /* Port 1 Interrupt Flag */
extern volatile unsigned char P2IFG;                                         /* Port 2 Interrupt Flag */
extern volatile unsigned char P3IN;                                          /* Port 3 Input */
extern volatile unsigned char P4IN;                                          /* Port 4 Input */
extern volatile unsigned char P3OUT;                                         /* Port 3 Output */
extern volatile unsigned char P4OUT;                                         /* Port 4 Output */
extern volatile unsigned char P3DIR;                                         /* Port 3 Direction */
extern volatile unsigned char P4DIR;                                         /* Port 4 Direction */
extern volatile unsigned char P3REN;                                         /* Port 3 Resistor Enable */
extern volatile unsigned char P4REN;                                         /* Port 4 Resistor Enable */
extern volatile unsigned char P4SEL0;                                        /* Port 4 Select 0 */
extern volatile unsigned char P3SEL0;                                        /* Port 3 Select 0 */
extern volatile unsigned char P3SEL1;                                        /* Port 3 Select 1 */
extern volatile unsigned char P4SEL1;                                        /* Port 4 Select 1 */
extern volatile unsigned char P3SELC;                                        /* Port 3 Complement Select */
extern volatile unsigned char P4SELC;                                        /* Port 4 Complement Select */
extern volatile unsigned char P3IES;                                         /* Port 3 Interrupt Edge Select */
extern volatile unsigned char P4IES;                                         /* Port 4 Interrupt Edge Select */
extern volatile unsigned char P3IE;                                          /* Port 3 Interrupt Enable */
extern volatile unsigned char P4IE;                                          /* Port 4 Interrupt Enable */
extern volatile unsigned char P3IFG;                                         /* Port 3 Interrupt Flag */
extern volatile unsigned char P4IFG;                                         /* Port 4 Interrupt Flag */
extern volatile unsigned char P5IN;                                          /* Port 5 Input */
extern volatile unsigned char P6IN;                                          /* Port 6 Input */
extern volatile unsigned char P5OUT;                                         /* Port 5 Output */
extern volatile unsigned char P6OUT;                                         /* Port 6 Output */
extern volatile unsigned char P5DIR;                                         /* Port 5 Direction */
extern volatile unsigned char P6DIR;                                         /* Port 6 Direction */
extern volatile unsigned char P5REN;                                         /* Port 5 Resistor Enable */
extern volatile unsigned char P6REN;                                         /* Port 6 Resistor Enable */
extern volatile unsigned char P5SEL0;                                        /* Port 5 Select 0 */
extern volatile unsigned char P6SEL0;                                        /* Port 6 Select 0 */
extern volatile unsigned char P5SEL1;                                        /* Port 5 Select 1 */
extern volatile unsigned char P6SEL1;                                        /* Port 6 Select 1 */
extern volatile unsigned char P5SELC;                                        /* Port 5 Complement Select */
extern volatile unsigned char P6SELC;                                        /* Port 6 Complement Select */
extern volatile unsigned char P5IES;                                         /* Port 5 Interrupt Edge Select */
extern volatile unsigned char P6IES;                                         /* Port 6 Interrupt Edge Select */
extern volatile unsigned char P5IE;                                          /* Port 5 Interrupt Enable */
extern volatile unsigned char P6IE;                                          /* Port 6 Interrupt Enable */
extern volatile unsigned char P5IFG;                                         /* Port 5 Interrupt Flag */
extern volatile unsigned char P6IFG;                                         /* Port 6 Interrupt Flag */

/* DIO Register Offsets */

/* DIO Control Bits */

/* P1IV Control Bits */

/* P2IV Control Bits */

/* P3IV Control Bits */

/* P4IV Control Bits */

/* P5IV Control Bits */

/* P6IV Control Bits */


/*****************************************************************************
 FRCTL Registers
*****************************************************************************/


extern volatile unsigned int FRCTL0;                                       /* FRAM Controller Control Register 0 */
extern volatile unsigned char FRCTL0_L;
extern volatile unsigned char FRCTL0_H;
extern volatile unsigned int GCCTL0;                                       /* General Control Register 0 */
extern volatile unsigned char GCCTL0_L;
extern volatile unsigned char GCCTL0_H;
extern volatile unsigned int GCCTL1;                                       /* General Control Register 1 */
extern volatile unsigned char GCCTL1_L;
extern volatile unsigned char GCCTL1_H;

/* FRCTL Register Offsets */

/* FRCTL Control Bits */

/* FRCTL0 Control Bits */

/* GCCTL0 Control Bits */

/* GCCTL1 Control Bits */


/*****************************************************************************
 MPY32 Registers
*****************************************************************************/


extern volatile unsigned int MPY;                                          /* 16-bit operand one  multiply */
extern volatile unsigned char MPY_L;
extern volatile unsigned char MPY_H;
extern volatile unsigned int MPYS;                                         /* 16-bit operand one  signed multiply */
extern volatile unsigned char MPYS_L;
extern volatile unsigned char MPYS_H;
extern volatile unsigned int MAC;                                          /* 16-bit operand one  multiply accumulate */
extern volatile unsigned char MAC_L;
extern volatile unsigned char MAC_H;
extern volatile unsigned int MACS;                                         /* 16-bit operand one  signed multiply accumulate */
extern volatile unsigned char MACS_L;
extern volatile unsigned char MACS_H;
extern volatile unsigned int OP2;                                          /* 16-bit operand two */
extern volatile unsigned char OP2_L;
extern volatile unsigned char OP2_H;
extern volatile unsigned int RESLO;                                        /* 16x16-bit result low word */
extern volatile unsigned char RESLO_L;
extern volatile unsigned char RESLO_H;
extern volatile unsigned int RESHI;                                        /* 16x16-bit result high word */
extern volatile unsigned char RESHI_L;
extern volatile unsigned char RESHI_H;
extern volatile unsigned int SUMEXT;                                       /* 16x16-bit sum extension register */
extern volatile unsigned char SUMEXT_L;
extern volatile unsigned char SUMEXT_H;
extern volatile unsigned int MPY32L;                                       /* 32-bit operand 1  multiply  low word */
extern volatile unsigned char MPY32L_L;
extern volatile unsigned char MPY32L_H;
extern volatile unsigned int MPY32H;                                       /* 32-bit operand 1  multiply  high word */
extern volatile unsigned char MPY32H_L;
extern volatile unsigned char MPY32H_H;
extern volatile unsigned int MPYS32L;                                      /* 32-bit operand 1  signed multiply  low word */
extern volatile unsigned char MPYS32L_L;
extern volatile unsigned char MPYS32L_H;
extern volatile unsigned int MPYS32H;                                      /* 32-bit operand 1  signed multiply  high word */
extern volatile unsigned char MPYS32H_L;
extern volatile unsigned char MPYS32H_H;
extern volatile unsigned int MAC32L;                                       /* 32-bit operand 1  multiply accumulate  low word */
extern volatile unsigned char MAC32L_L;
extern volatile unsigned char MAC32L_H;
extern volatile unsigned int MAC32H;                                       /* 32-bit operand 1  multiply accumulate  high word */
extern volatile unsigned char MAC32H_L;
extern volatile unsigned char MAC32H_H;
extern volatile unsigned int MACS32L;                                      /* 32-bit operand 1  signed multiply accumulate  low word */
extern volatile unsigned char MACS32L_L;
extern volatile unsigned char MACS32L_H;
extern volatile unsigned int MACS32H;                                      /* 32-bit operand 1  signed multiply accumulate  high word */
extern volatile unsigned char MACS32H_L;
extern volatile unsigned char MACS32H_H;
extern volatile unsigned int OP2L;                                         /* 32-bit operand 2  low word */
extern volatile unsigned char OP2L_L;
extern volatile unsigned char OP2L_H;
extern volatile unsigned int OP2H;                                         /* 32-bit operand 2  high word */
extern volatile unsigned char OP2H_L;
extern volatile unsigned char OP2H_H;
extern volatile unsigned int RES0;                                         /* 32x32-bit result 0  least significant word */
extern volatile unsigned char RES0_L;
extern volatile unsigned char RES0_H;
extern volatile unsigned int RES1;                                         /* 32x32-bit result 1 */
extern volatile unsigned char RES1_L;
extern volatile unsigned char RES1_H;
extern volatile unsigned int RES2;                                         /* 32x32-bit result 2 */
extern volatile unsigned char RES2_L;
extern volatile unsigned char RES2_H;
extern volatile unsigned int RES3;                                         /* 32x32-bit result 3  most significant word */
extern volatile unsigned char RES3_L;
extern volatile unsigned char RES3_H;
extern volatile unsigned int MPY32CTL0;                                    /* MPY32 control register 0 */
extern volatile unsigned char MPY32CTL0_L;
extern volatile unsigned char MPY32CTL0_H;

/* MPY32 Register Offsets */

/* MPY32 Control Bits */

/* MACS32H Control Bits */

/* MPY32CTL0 Control Bits */


/*****************************************************************************
 PMM Registers
*****************************************************************************/


extern volatile unsigned int PMMCTL0;                                      /* Power Management Module control register 0 */
extern volatile unsigned char PMMCTL0_L;
extern volatile unsigned char PMMCTL0_H;
extern volatile unsigned int PMMCTL1;                                      /* Power Management Module Control Register 1. Allows manual 
                                                            overwrite of predictive LDO settings. */
extern volatile unsigned char PMMCTL1_L;
extern volatile unsigned char PMMCTL1_H;
extern volatile unsigned int PMMCTL2;                                      /* Power Management Module Control Register 2 */
extern volatile unsigned char PMMCTL2_L;
extern volatile unsigned char PMMCTL2_H;
extern volatile unsigned int PMMIFG;                                       /* PMM interrupt flag register */
extern volatile unsigned char PMMIFG_L;
extern volatile unsigned char PMMIFG_H;
extern volatile unsigned int PM5CTL0;                                      /* Power mode 5 control register 0 */
extern volatile unsigned char PM5CTL0_L;
extern volatile unsigned char PM5CTL0_H;

/* PMM Register Offsets */

/* PMM Control Bits */

/* PMMCTL0 Control Bits */

/* PMMCTL2 Control Bits */

/* PMMIFG Control Bits */

/* PM5CTL0 Control Bits */


/*****************************************************************************
 RTC Registers
*****************************************************************************/


extern volatile unsigned int RTCCTL;                                       /* RTCCTL0 Register */
extern volatile unsigned char RTCCTL_L;
extern volatile unsigned char RTCCTL_H;
extern volatile unsigned int RTCIV;                                        /* Real-Time Clock Interrupt Vector Register */
extern volatile unsigned char RTCIV_L;
extern volatile unsigned char RTCIV_H;
extern volatile unsigned int RTCMOD;                                       /* RTC Counter Modulo Register */
extern volatile unsigned char RTCMOD_L;
extern volatile unsigned char RTCMOD_H;
extern volatile unsigned int RTCCNT;                                       /* RTC Counter Register */
extern volatile unsigned char RTCCNT_L;
extern volatile unsigned char RTCCNT_H;

/* RTC Register Offsets */

/* RTC Control Bits */

/* RTCCTL Control Bits */

/* RTCIV Control Bits */


/*****************************************************************************
 SFR Registers
*****************************************************************************/


extern volatile unsigned int SFRIE1;                                       /* Interrupt Enable */
extern volatile unsigned char SFRIE1_L;
extern volatile unsigned char SFRIE1_H;
extern volatile unsigned int SFRIFG1;                                      /* Interrupt Flag */
extern volatile unsigned char SFRIFG1_L;
extern volatile unsigned char SFRIFG1_H;
extern volatile unsigned int SFRRPCR;                                      /* Reset Pin Control */
extern volatile unsigned char SFRRPCR_L;
extern volatile unsigned char SFRRPCR_H;

/* SFR Register Offsets */

/* SFR Control Bits */

/* SFRIE1 Control Bits */

/* SFRIFG1 Control Bits */

/* SFRRPCR Control Bits */


/*****************************************************************************
 SYS Registers
*****************************************************************************/


extern volatile unsigned int SYSCTL;                                       /* System Control */
extern volatile unsigned char SYSCTL_L;
extern volatile unsigned char SYSCTL_H;
extern volatile unsigned int SYSBSLC;                                      /* Bootloader Configuration */
extern volatile unsigned char SYSBSLC_L;
extern volatile unsigned char SYSBSLC_H;
extern volatile unsigned int SYSJMBC;                                      /* JTAG Mailbox Control */
extern volatile unsigned char SYSJMBC_L;
extern volatile unsigned char SYSJMBC_H;
extern volatile unsigned int SYSJMBI0;                                     /* JTAG Mailbox Input 0 */
extern volatile unsigned char SYSJMBI0_L;
extern volatile unsigned char SYSJMBI0_H;
extern volatile unsigned int SYSJMBI1;                                     /* JTAG Mailbox Input 1 */
extern volatile unsigned char SYSJMBI1_L;
extern volatile unsigned char SYSJMBI1_H;
extern volatile unsigned int SYSJMBO0;                                     /* JTAG Mailbox Output 0 */
extern volatile unsigned char SYSJMBO0_L;
extern volatile unsigned char SYSJMBO0_H;
extern volatile unsigned int SYSJMBO1;                                     /* JTAG Mailbox Output 1 */
extern volatile unsigned char SYSJMBO1_L;
extern volatile unsigned char SYSJMBO1_H;
extern volatile unsigned int SYSUNIV;                                      /* User NMI Vector Generator */
extern volatile unsigned char SYSUNIV_L;
extern volatile unsigned char SYSUNIV_H;
extern volatile unsigned int SYSSNIV;                                      /* System NMI Vector Generator */
extern volatile unsigned char SYSSNIV_L;
extern volatile unsigned char SYSSNIV_H;
extern volatile unsigned int SYSRSTIV;                                     /* Reset Vector Generator */
extern volatile unsigned char SYSRSTIV_L;
extern volatile unsigned char SYSRSTIV_H;
extern volatile unsigned int SYSCFG0;                                      /* System Configuration 0 */
extern volatile unsigned char SYSCFG0_L;
extern volatile unsigned char SYSCFG0_H;
extern volatile unsigned int SYSCFG1;                                      /* System Configuration 1 */
extern volatile unsigned char SYSCFG1_L;
extern volatile unsigned char SYSCFG1_H;
extern volatile unsigned int SYSCFG2;                                      /* System Configuration 2 */
extern volatile unsigned char SYSCFG2_L;
extern volatile unsigned char SYSCFG2_H;
extern volatile unsigned int SYSCFG3;                                      /* System Configuration 3 */
extern volatile unsigned char SYSCFG3_L;
extern volatile unsigned char SYSCFG3_H;

/* SYS Register Offsets */

/* SYS Control Bits */

/* SYSCTL Control Bits */

/* SYSBSLC Control Bits */

/* SYSJMBC Control Bits */

/* SYSJMBI0 Control Bits */

/* SYSUNIV Control Bits */

/* SYSSNIV Control Bits */

/* SYSRSTIV Control Bits */

/* SYSCFG0 Control Bits */

/* SYSCFG1 Control Bits */

/* SYSCFG2 Control Bits */

/* SYSCFG3 Control Bits */


/*****************************************************************************
 TA0 Registers
*****************************************************************************/


extern volatile unsigned int TA0CTL;                                       /* TimerAx Control Register */
extern volatile unsigned char TA0CTL_L;
extern volatile unsigned char TA0CTL_H;
extern volatile unsigned int TA0CCTL0;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA0CCTL0_L;
extern volatile unsigned char TA0CCTL0_H;
extern volatile unsigned int TA0CCTL1;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA0CCTL1_L;
extern volatile unsigned char TA0CCTL1_H;
extern volatile unsigned int TA0CCTL2;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA0CCTL2_L;
extern volatile unsigned char TA0CCTL2_H;
extern volatile unsigned int TA0R;                                         /* TimerA register */
extern volatile unsigned char TA0R_L;
extern volatile unsigned char TA0R_H;
extern volatile unsigned int TA0CCR0;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA0CCR0_L;
extern volatile unsigned char TA0CCR0_H;
extern volatile unsigned int TA0CCR1;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA0CCR1_L;
extern volatile unsigned char TA0CCR1_H;
extern volatile unsigned int TA0CCR2;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA0CCR2_L;
extern volatile unsigned char TA0CCR2_H;
extern volatile unsigned int TA0EX0;                                       /* TimerAx Expansion 0 Register */
extern volatile unsigned char TA0EX0_L;
extern volatile unsigned char TA0EX0_H;
extern volatile unsigned int TA0IV;                                        /* TimerAx Interrupt Vector Register */
extern volatile unsigned char TA0IV_L;
extern volatile unsigned char TA0IV_H;

/* TA0 Register Offsets */

/* TA0 Control Bits */

/* TA0CTL Control Bits */

/* TA0CCTL Control Bits */

/* TA0EX0 Control Bits */

/* TA0IV Control Bits */


/*****************************************************************************
 TA1 Registers
*****************************************************************************/


extern volatile unsigned int TA1CTL;                                       /* TimerAx Control Register */
extern volatile unsigned char TA1CTL_L;
extern volatile unsigned char TA1CTL_H;
extern volatile unsigned int TA1CCTL0;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA1CCTL0_L;
extern volatile unsigned char TA1CCTL0_H;
extern volatile unsigned int TA1CCTL1;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA1CCTL1_L;
extern volatile unsigned char TA1CCTL1_H;
extern volatile unsigned int TA1CCTL2;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA1CCTL2_L;
extern volatile unsigned char TA1CCTL2_H;
extern volatile unsigned int TA1R;                                         /* TimerA register */
extern volatile unsigned char TA1R_L;
extern volatile unsigned char TA1R_H;
extern volatile unsigned int TA1CCR0;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA1CCR0_L;
extern volatile unsigned char TA1CCR0_H;
extern volatile unsigned int TA1CCR1;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA1CCR1_L;
extern volatile unsigned char TA1CCR1_H;
extern volatile unsigned int TA1CCR2;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA1CCR2_L;
extern volatile unsigned char TA1CCR2_H;
extern volatile unsigned int TA1EX0;                                       /* TimerAx Expansion 0 Register */
extern volatile unsigned char TA1EX0_L;
extern volatile unsigned char TA1EX0_H;
extern volatile unsigned int TA1IV;                                        /* TimerAx Interrupt Vector Register */
extern volatile unsigned char TA1IV_L;
extern volatile unsigned char TA1IV_H;

/* TA1 Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 TA2 Registers
*****************************************************************************/


extern volatile unsigned int TA2CTL;                                       /* TimerAx Control Register */
extern volatile unsigned char TA2CTL_L;
extern volatile unsigned char TA2CTL_H;
extern volatile unsigned int TA2CCTL0;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA2CCTL0_L;
extern volatile unsigned char TA2CCTL0_H;
extern volatile unsigned int TA2CCTL1;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA2CCTL1_L;
extern volatile unsigned char TA2CCTL1_H;
extern volatile unsigned int TA2CCTL2;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA2CCTL2_L;
extern volatile unsigned char TA2CCTL2_H;
extern volatile unsigned int TA2R;                                         /* TimerA register */
extern volatile unsigned char TA2R_L;
extern volatile unsigned char TA2R_H;
extern volatile unsigned int TA2CCR0;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA2CCR0_L;
extern volatile unsigned char TA2CCR0_H;
extern volatile unsigned int TA2CCR1;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA2CCR1_L;
extern volatile unsigned char TA2CCR1_H;
extern volatile unsigned int TA2CCR2;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA2CCR2_L;
extern volatile unsigned char TA2CCR2_H;
extern volatile unsigned int TA2EX0;                                       /* TimerAx Expansion 0 Register */
extern volatile unsigned char TA2EX0_L;
extern volatile unsigned char TA2EX0_H;
extern volatile unsigned int TA2IV;                                        /* TimerAx Interrupt Vector Register */
extern volatile unsigned char TA2IV_L;
extern volatile unsigned char TA2IV_H;

/* TA2 Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 TA3 Registers
*****************************************************************************/


extern volatile unsigned int TA3CTL;                                       /* TimerAx Control Register */
extern volatile unsigned char TA3CTL_L;
extern volatile unsigned char TA3CTL_H;
extern volatile unsigned int TA3CCTL0;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA3CCTL0_L;
extern volatile unsigned char TA3CCTL0_H;
extern volatile unsigned int TA3CCTL1;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA3CCTL1_L;
extern volatile unsigned char TA3CCTL1_H;
extern volatile unsigned int TA3CCTL2;                                     /* Timer_A Capture/Compare Control Register */
extern volatile unsigned char TA3CCTL2_L;
extern volatile unsigned char TA3CCTL2_H;
extern volatile unsigned int TA3R;                                         /* TimerA register */
extern volatile unsigned char TA3R_L;
extern volatile unsigned char TA3R_H;
extern volatile unsigned int TA3CCR0;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA3CCR0_L;
extern volatile unsigned char TA3CCR0_H;
extern volatile unsigned int TA3CCR1;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA3CCR1_L;
extern volatile unsigned char TA3CCR1_H;
extern volatile unsigned int TA3CCR2;                                      /* Timer_A Capture/Compare  Register */
extern volatile unsigned char TA3CCR2_L;
extern volatile unsigned char TA3CCR2_H;
extern volatile unsigned int TA3EX0;                                       /* TimerAx Expansion 0 Register */
extern volatile unsigned char TA3EX0_L;
extern volatile unsigned char TA3EX0_H;
extern volatile unsigned int TA3IV;                                        /* TimerAx Interrupt Vector Register */
extern volatile unsigned char TA3IV_L;
extern volatile unsigned char TA3IV_H;

/* TA3 Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 TB0 Registers
*****************************************************************************/


extern volatile unsigned int TB0CTL;                                       /* Timer_B Control Register */
extern volatile unsigned char TB0CTL_L;
extern volatile unsigned char TB0CTL_H;
extern volatile unsigned int TB0CCTL0;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL0_L;
extern volatile unsigned char TB0CCTL0_H;
extern volatile unsigned int TB0CCTL1;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL1_L;
extern volatile unsigned char TB0CCTL1_H;
extern volatile unsigned int TB0CCTL2;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL2_L;
extern volatile unsigned char TB0CCTL2_H;
extern volatile unsigned int TB0CCTL3;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL3_L;
extern volatile unsigned char TB0CCTL3_H;
extern volatile unsigned int TB0CCTL4;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL4_L;
extern volatile unsigned char TB0CCTL4_H;
extern volatile unsigned int TB0CCTL5;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL5_L;
extern volatile unsigned char TB0CCTL5_H;
extern volatile unsigned int TB0CCTL6;                                     /* Timer_B Capture/Compare Control Register */
extern volatile unsigned char TB0CCTL6_L;
extern volatile unsigned char TB0CCTL6_H;
extern volatile unsigned int TB0R;                                         /* Timer_B count register */
extern volatile unsigned char TB0R_L;
extern volatile unsigned char TB0R_H;
extern volatile unsigned int TB0CCR0;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR0_L;
extern volatile unsigned char TB0CCR0_H;
extern volatile unsigned int TB0CCR1;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR1_L;
extern volatile unsigned char TB0CCR1_H;
extern volatile unsigned int TB0CCR2;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR2_L;
extern volatile unsigned char TB0CCR2_H;
extern volatile unsigned int TB0CCR3;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR3_L;
extern volatile unsigned char TB0CCR3_H;
extern volatile unsigned int TB0CCR4;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR4_L;
extern volatile unsigned char TB0CCR4_H;
extern volatile unsigned int TB0CCR5;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR5_L;
extern volatile unsigned char TB0CCR5_H;
extern volatile unsigned int TB0CCR6;                                      /* Timer_B Capture/Compare  Register */
extern volatile unsigned char TB0CCR6_L;
extern volatile unsigned char TB0CCR6_H;
extern volatile unsigned int TB0EX0;                                       /* Timer_Bx Expansion Register 0 */
extern volatile unsigned char TB0EX0_L;
extern volatile unsigned char TB0EX0_H;
extern volatile unsigned int TB0IV;                                        /* Timer_Bx Interrupt Vector Register */
extern volatile unsigned char TB0IV_L;
extern volatile unsigned char TB0IV_H;

/* TB0 Register Offsets */

/* TB0 Control Bits */

/* TB0CTL Control Bits */

/* TB0CCTL Control Bits */

/* TB0EX0 Control Bits */

/* TB0IV Control Bits */


/*****************************************************************************
 WDT_A Registers
*****************************************************************************/


extern volatile unsigned int WDTCTL;                                       /* Watchdog Timer Control Register */
extern volatile unsigned char WDTCTL_L;
extern volatile unsigned char WDTCTL_H;

/* WDT_A Register Offsets */

/* WDT_A Control Bits */

/* WDTCTL Control Bits */


/*****************************************************************************
 eCOMP0 Registers
*****************************************************************************/


extern volatile unsigned int CP0CTL0;                                      /* Comparator Control Register 0 */
extern volatile unsigned char CP0CTL0_L;
extern volatile unsigned char CP0CTL0_H;
extern volatile unsigned int CP0CTL1;                                      /* Comparator Control Register 1 */
extern volatile unsigned char CP0CTL1_L;
extern volatile unsigned char CP0CTL1_H;
extern volatile unsigned int CP0INT;                                       /* Comparator Interrupt Control Register */
extern volatile unsigned char CP0INT_L;
extern volatile unsigned char CP0INT_H;
extern volatile unsigned int CP0IV;                                        /* Comparator Interrupt Vector Word Register */
extern volatile unsigned char CP0IV_L;
extern volatile unsigned char CP0IV_H;
extern volatile unsigned int CP0DACCTL;                                    /* 6-bit Comparator built-in DAC Control Register */
extern volatile unsigned char CP0DACCTL_L;
extern volatile unsigned char CP0DACCTL_H;
extern volatile unsigned int CP0DACDATA;                                   /* 6-bit Comparator built-in DAC Data Register */
extern volatile unsigned char CP0DACDATA_L;
extern volatile unsigned char CP0DACDATA_H;

/* eCOMP0 Register Offsets */

/* eCOMP0 Control Bits */

/* CP0CTL0 Control Bits */

/* CP0CTL1 Control Bits */

/* CP0INT Control Bits */

/* CP0IV Control Bits */

/* CP0DACCTL Control Bits */

/* CP0DACDATA Control Bits */


/*****************************************************************************
 eUSCI_A0 Registers
*****************************************************************************/


extern volatile unsigned int UCA0CTLW0;                                    /* eUSCI_Ax Control Word Register 0 */
extern volatile unsigned char UCA0CTLW0_L;
extern volatile unsigned char UCA0CTLW0_H;
extern volatile unsigned int UCA0CTLW1;                                    /* eUSCI_Ax Control Word Register 1 */
extern volatile unsigned char UCA0CTLW1_L;
extern volatile unsigned char UCA0CTLW1_H;
extern volatile unsigned int UCA0BRW;                                      /* eUSCI_Ax Baud Rate Control Word Register */
extern volatile unsigned char UCA0BRW_L;
extern volatile unsigned char UCA0BRW_H;
extern volatile unsigned int UCA0MCTLW;                                    /* eUSCI_Ax Modulation Control Word Register */
extern volatile unsigned char UCA0MCTLW_L;
extern volatile unsigned char UCA0MCTLW_H;
extern volatile unsigned int UCA0STATW;                                    /* eUSCI_Ax Status Register */
extern volatile unsigned char UCA0STATW_L;
extern volatile unsigned char UCA0STATW_H;
extern volatile unsigned int UCA0RXBUF;                                    /* eUSCI_Ax Receive Buffer Register */
extern volatile unsigned char UCA0RXBUF_L;
extern volatile unsigned char UCA0RXBUF_H;
extern volatile unsigned int UCA0TXBUF;                                    /* eUSCI_Ax Transmit Buffer Register */
extern volatile unsigned char UCA0TXBUF_L;
extern volatile unsigned char UCA0TXBUF_H;
extern volatile unsigned int UCA0ABCTL;                                    /* eUSCI_Ax Auto Baud Rate Control Register */
extern volatile unsigned char UCA0ABCTL_L;
extern volatile unsigned char UCA0ABCTL_H;
extern volatile unsigned int UCA0IRCTL;                                    /* eUSCI_Ax IrDA Control Word Register */
extern volatile unsigned char UCA0IRCTL_L;
extern volatile unsigned char UCA0IRCTL_H;
extern volatile unsigned int UCA0IE;                                       /* eUSCI_Ax Interrupt Enable Register */
extern volatile unsigned char UCA0IE_L;
extern volatile unsigned char UCA0IE_H;
extern volatile unsigned int UCA0IFG;                                      /* eUSCI_Ax Interrupt Flag Register */
extern volatile unsigned char UCA0IFG_L;
extern volatile unsigned char UCA0IFG_H;
extern volatile unsigned int UCA0IV;                                       /* eUSCI_Ax Interrupt Vector Register */
extern volatile unsigned char UCA0IV_L;
extern volatile unsigned char UCA0IV_H;

/* eUSCI_A0 Register Offsets */

/* eUSCI_A0 Control Bits */

/* UCA0CTLW0 Control Bits */

/* UCA0CTLW0_SPI Control Bits */

/* UCA0CTLW1 Control Bits */

/* UCA0BRW Control Bits */

/* UCA0MCTLW Control Bits */

/* UCA0STATW Control Bits */

/* UCA0RXBUF Control Bits */

/* UCA0TXBUF Control Bits */

/* UCA0ABCTL Control Bits */

/* UCA0IRCTL Control Bits */

/* UCA0IE Control Bits */

/* UCA0IFG Control Bits */

/* UCA0IV Control Bits */


/*****************************************************************************
 eUSCI_A1 Registers
*****************************************************************************/


extern volatile unsigned int UCA1CTLW0;                                    /* eUSCI_Ax Control Word Register 0 */
extern volatile unsigned char UCA1CTLW0_L;
extern volatile unsigned char UCA1CTLW0_H;
extern volatile unsigned int UCA1CTLW1;                                    /* eUSCI_Ax Control Word Register 1 */
extern volatile unsigned char UCA1CTLW1_L;
extern volatile unsigned char UCA1CTLW1_H;
extern volatile unsigned int UCA1BRW;                                      /* eUSCI_Ax Baud Rate Control Word Register */
extern volatile unsigned char UCA1BRW_L;
extern volatile unsigned char UCA1BRW_H;
extern volatile unsigned int UCA1MCTLW;                                    /* eUSCI_Ax Modulation Control Word Register */
extern volatile unsigned char UCA1MCTLW_L;
extern volatile unsigned char UCA1MCTLW_H;
extern volatile unsigned int UCA1STATW;                                    /* eUSCI_Ax Status Register */
extern volatile unsigned char UCA1STATW_L;
extern volatile unsigned char UCA1STATW_H;
extern volatile unsigned int UCA1RXBUF;                                    /* eUSCI_Ax Receive Buffer Register */
extern volatile unsigned char UCA1RXBUF_L;
extern volatile unsigned char UCA1RXBUF_H;
extern volatile unsigned int UCA1TXBUF;                                    /* eUSCI_Ax Transmit Buffer Register */
extern volatile unsigned char UCA1TXBUF_L;
extern volatile unsigned char UCA1TXBUF_H;
extern volatile unsigned int UCA1ABCTL;                                    /* eUSCI_Ax Auto Baud Rate Control Register */
extern volatile unsigned char UCA1ABCTL_L;
extern volatile unsigned char UCA1ABCTL_H;
extern volatile unsigned int UCA1IRCTL;                                    /* eUSCI_Ax IrDA Control Word Register */
extern volatile unsigned char UCA1IRCTL_L;
extern volatile unsigned char UCA1IRCTL_H;
extern volatile unsigned int UCA1IE;                                       /* eUSCI_Ax Interrupt Enable Register */
extern volatile unsigned char UCA1IE_L;
extern volatile unsigned char UCA1IE_H;
extern volatile unsigned int UCA1IFG;                                      /* eUSCI_Ax Interrupt Flag Register */
extern volatile unsigned char UCA1IFG_L;
extern volatile unsigned char UCA1IFG_H;
extern volatile unsigned int UCA1IV;                                       /* eUSCI_Ax Interrupt Vector Register */
extern volatile unsigned char UCA1IV_L;
extern volatile unsigned char UCA1IV_H;

/* eUSCI_A1 Register Offsets */

/* No control bits available or already defined for another module */

/*****************************************************************************
 eUSCI_B0 Registers
*****************************************************************************/


extern volatile unsigned int UCB0CTLW0;                                    /* eUSCI_Bx Control Word Register 0 */
extern volatile unsigned char UCB0CTLW0_L;
extern volatile unsigned char UCB0CTLW0_H;
extern volatile unsigned int UCB0CTLW1;                                    /* eUSCI_Bx Control Word Register 1 */
extern volatile unsigned char UCB0CTLW1_L;
extern volatile unsigned char UCB0CTLW1_H;
extern volatile unsigned int UCB0BRW;                                      /* eUSCI_Bx Baud Rate Control Word Register */
extern volatile unsigned char UCB0BRW_L;
extern volatile unsigned char UCB0BRW_H;
extern volatile unsigned int UCB0STATW;                                    /* eUSCI_Bx Status Register */
extern volatile unsigned char UCB0STATW_L;
extern volatile unsigned char UCB0STATW_H;
extern volatile unsigned int UCB0TBCNT;                                    /* eUSCI_Bx Byte Counter Threshold Register */
extern volatile unsigned char UCB0TBCNT_L;
extern volatile unsigned char UCB0TBCNT_H;
extern volatile unsigned int UCB0RXBUF;                                    /* eUSCI_Bx Receive Buffer Register */
extern volatile unsigned char UCB0RXBUF_L;
extern volatile unsigned char UCB0RXBUF_H;
extern volatile unsigned int UCB0TXBUF;                                    /* eUSCI_Bx Transmit Buffer Register */
extern volatile unsigned char UCB0TXBUF_L;
extern volatile unsigned char UCB0TXBUF_H;
extern volatile unsigned int UCB0I2COA0;                                   /* eUSCI_Bx I2C Own Address 0 Register */
extern volatile unsigned char UCB0I2COA0_L;
extern volatile unsigned char UCB0I2COA0_H;
extern volatile unsigned int UCB0I2COA1;                                   /* eUSCI_Bx I2C Own Address 1 Register */
extern volatile unsigned char UCB0I2COA1_L;
extern volatile unsigned char UCB0I2COA1_H;
extern volatile unsigned int UCB0I2COA2;                                   /* eUSCI_Bx I2C Own Address 2 Register */
extern volatile unsigned char UCB0I2COA2_L;
extern volatile unsigned char UCB0I2COA2_H;
extern volatile unsigned int UCB0I2COA3;                                   /* eUSCI_Bx I2C Own Address 3 Register */
extern volatile unsigned char UCB0I2COA3_L;
extern volatile unsigned char UCB0I2COA3_H;
extern volatile unsigned int UCB0ADDRX;                                    /* eUSCI_Bx I2C Received Address Register */
extern volatile unsigned char UCB0ADDRX_L;
extern volatile unsigned char UCB0ADDRX_H;
extern volatile unsigned int UCB0ADDMASK;                                  /* eUSCI_Bx I2C Address Mask Register */
extern volatile unsigned char UCB0ADDMASK_L;
extern volatile unsigned char UCB0ADDMASK_H;
extern volatile unsigned int UCB0I2CSA;                                    /* eUSCI_Bx I2C Slave Address Register */
extern volatile unsigned char UCB0I2CSA_L;
extern volatile unsigned char UCB0I2CSA_H;
extern volatile unsigned int UCB0IE;                                       /* eUSCI_Bx Interrupt Enable Register */
extern volatile unsigned char UCB0IE_L;
extern volatile unsigned char UCB0IE_H;
extern volatile unsigned int UCB0IFG;                                      /* eUSCI_Bx Interrupt Flag Register */
extern volatile unsigned char UCB0IFG_L;
extern volatile unsigned char UCB0IFG_H;
extern volatile unsigned int UCB0IV;                                       /* eUSCI_Bx Interrupt Vector Register */
extern volatile unsigned char UCB0IV_L;
extern volatile unsigned char UCB0IV_H;

/* eUSCI_B0 Register Offsets */

/* eUSCI_B0 Control Bits */

/* UCB0CTLW0 Control Bits */

/* UCB0CTLW1 Control Bits */

/* UCB0STATW Control Bits */

/* UCB0TBCNT Control Bits */

/* UCB0I2COA0 Control Bits */

/* UCB0I2COA1 Control Bits */

/* UCB0I2COA2 Control Bits */

/* UCB0I2COA3 Control Bits */

/* UCB0ADDRX Control Bits */

/* UCB0ADDMASK Control Bits */

/* UCB0I2CSA Control Bits */

/* UCB0IE Control Bits */

/* UCB0IFG Control Bits */

/* UCB0IV Control Bits */


/*****************************************************************************
 eUSCI_B1 Registers
*****************************************************************************/


extern volatile unsigned int UCB1CTLW0;                                    /* eUSCI_Bx Control Word Register 0 */
extern volatile unsigned char UCB1CTLW0_L;
extern volatile unsigned char UCB1CTLW0_H;
extern volatile unsigned int UCB1CTLW1;                                    /* eUSCI_Bx Control Word Register 1 */
extern volatile unsigned char UCB1CTLW1_L;
extern volatile unsigned char UCB1CTLW1_H;
extern volatile unsigned int UCB1BRW;                                      /* eUSCI_Bx Baud Rate Control Word Register */
extern volatile unsigned char UCB1BRW_L;
extern volatile unsigned char UCB1BRW_H;
extern volatile unsigned int UCB1STATW;                                    /* eUSCI_Bx Status Register */
extern volatile unsigned char UCB1STATW_L;
extern volatile unsigned char UCB1STATW_H;
extern volatile unsigned int UCB1TBCNT;                                    /* eUSCI_Bx Byte Counter Threshold Register */
extern volatile unsigned char UCB1TBCNT_L;
extern volatile unsigned char UCB1TBCNT_H;
extern volatile unsigned int UCB1RXBUF;                                    /* eUSCI_Bx Receive Buffer Register */
extern volatile unsigned char UCB1RXBUF_L;
extern volatile unsigned char UCB1RXBUF_H;
extern volatile unsigned int UCB1TXBUF;                                    /* eUSCI_Bx Transmit Buffer Register */
extern volatile unsigned char UCB1TXBUF_L;
extern volatile unsigned char UCB1TXBUF_H;
extern volatile unsigned int UCB1I2COA0;                                   /* eUSCI_Bx I2C Own Address 0 Register */
extern volatile unsigned char UCB1I2COA0_L;
extern volatile unsigned char UCB1I2COA0_H;
extern volatile unsigned int UCB1I2COA1;                                   /* eUSCI_Bx I2C Own Address 1 Register */
extern volatile unsigned char UCB1I2COA1_L;
extern volatile unsigned char UCB1I2COA1_H;
extern volatile unsigned int UCB1I2COA2;                                   /* eUSCI_Bx I2C Own Address 2 Register */
extern volatile unsigned char UCB1I2COA2_L;
extern volatile unsigned char UCB1I2COA2_H;
extern volatile unsigned int UCB1I2COA3;                                   /* eUSCI_Bx I2C Own Address 3 Register */
extern volatile unsigned char UCB1I2COA3_L;
extern volatile unsigned char UCB1I2COA3_H;
extern volatile unsigned int UCB1ADDRX;                                    /* eUSCI_Bx I2C Received Address Register */
extern volatile unsigned char UCB1ADDRX_L;
extern volatile unsigned char UCB1ADDRX_H;
extern volatile unsigned int UCB1ADDMASK;                                  /* eUSCI_Bx I2C Address Mask Register */
extern volatile unsigned char UCB1ADDMASK_L;
extern volatile unsigned char UCB1ADDMASK_H;
extern volatile unsigned int UCB1I2CSA;                                    /* eUSCI_Bx I2C Slave Address Register */
extern volatile unsigned char UCB1I2CSA_L;
extern volatile unsigned char UCB1I2CSA_H;
extern volatile unsigned int UCB1IE;                                       /* eUSCI_Bx Interrupt Enable Register */
extern volatile unsigned char UCB1IE_L;
extern volatile unsigned char UCB1IE_H;
extern volatile unsigned int UCB1IFG;                                      /* eUSCI_Bx Interrupt Flag Register */
extern volatile unsigned char UCB1IFG_L;
extern volatile unsigned char UCB1IFG_H;
extern volatile unsigned int UCB1IV;                                       /* eUSCI_Bx Interrupt Vector Register */
extern volatile unsigned char UCB1IV_L;
extern volatile unsigned char UCB1IV_H;

/* eUSCI_B1 Register Offsets */

/* No control bits available or already defined for another module */

/************************************************************
* TLV Descriptors
************************************************************/




/************************************************************
* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
************************************************************/

#pragma diag_suppress 1107


/************************************************************
* Memory Boundary Definitions
************************************************************/


/************************************************************
* End of Modules
************************************************************/


//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//  Redistributions of source code must retain the above copyright
//  notice, this list of conditions and the following disclaimer.
//
//  Redistributions in binary form must reproduce the above copyright
//  notice, this list of conditions and the following disclaimer in the
//  documentation and/or other materials provided with the
//  distribution.
//
//  Neither the name of Texas Instruments Incorporated nor the names of
//  its contributors may be used to endorse or promote products derived
//  from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//****************************************************************************


/************************************************************
* ADC
************************************************************/




/************************************************************
* ADC12_B
************************************************************/

/************************************************************
* CAP TOUCH
************************************************************/



/************************************************************
* CLOCK SYSTEM
************************************************************/









/************************************************************
* COMP_E
************************************************************/


/************************************************************
* CRC32
************************************************************/


/************************************************************
* DIO
************************************************************/



/************************************************************
* DMA
************************************************************/


/************************************************************
* ECOMP0
************************************************************/


// not provided due to possible invalid re-define
//#define CPIV                    CP0IV
//#define CPIV_L                  CP0IV_L
//#define CPIV_H                  CP0IV_H


/************************************************************
* FRCTL
************************************************************/


    


/************************************************************
* LCD_C
************************************************************/


/************************************************************
* LEA
************************************************************/


/************************************************************
* MPY32
************************************************************/





/************************************************************
* PMM
************************************************************/


/************************************************************
* RAMCTL
************************************************************/


/************************************************************
* RTC
************************************************************/





/************************************************************
* RTC_C
************************************************************/


/************************************************************
* SAPH_A
************************************************************/


/************************************************************
* SYS
************************************************************/







/************************************************************
* Timer A
************************************************************/



/* TAxIV Definitions */

/* Legacy Defines */












/************************************************************
* Timer B
************************************************************/



/* TBxIV Definitions */

/* Legacy Defines */







    




/************************************************************
* USCI
************************************************************/


 
 






/************************************************************
* USCI Ax
************************************************************/














/************************************************************
* USCI Bx
************************************************************/















/************************************************************
* WDT
************************************************************/


/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
/* WDT is clocked by fACLK (assumed 32KHz) */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
/* WDT is clocked by fACLK (assumed 32KHz) */






unsigned long int global_sec_count = 0;
//unsigned long int sec_start;

unsigned char timer1_cfg()
{
	TA1CTL &= 0xFFCF;	// stop
	TA1CTL |= 0x0004;	// clear
	TA1CTL = 0x01C0;	// other
	TA1CCTL0 = 0x0000;
	TA1CCR0 = 0x0200;	// 32768 / 8 / 8
	TA1EX0 = 0x0007;
	TA1CTL |= 0x0010;	//up mode
	TA1CTL |= 0x0002; // enable interrupt
	return 0;
}

#pragma vector = (40 * 1u)
__interrupt void TIMER1_A1_ISR(void)
{
    switch(TA1IV)
	{
		case 0x00:  // Vector 0: No interrupts
			break;
		case 0x0E:
			global_sec_count++;
			break;
		default:
			break;
	}
}

unsigned char msp430fr2476_init()
{
	WDTCTL = 0x5A29;	// enable watchdog
	PM5CTL0 &= 0xFFFE;
//------------------------------------
    PASEL1 = 0x0000;    // PA is IO
    PBSEL1 = 0x0000;    // PB is IO
    PCSEL1 = 0x0000;    // PC is IO
    PASEL0 = 0x0300;    // P2.0 & P2.1 is 32768
    PBSEL0 = 0x0000;    // PB is IO
    PCSEL0 = 0x0000;    // PC is IO
//----------------------------------
	while(SFRIFG1 & 0x0002)
	{
	    CSCTL7 &= 0xFFFC;
		SFRIFG1 &= 0xFFFD;
		__no_operation();
		__no_operation();
	}
	__bis_SR_register((0x0040));                // disable FLL
	CSCTL3 &= 0xFFCF;
	CSCTL1 = 0x0033;
	CSCTL2 = 60;    // 2M / 32768 = 61
	__delay_cycles(((unsigned long int) 2000000) * 10 / ((unsigned long int)1000000));
	__bic_SR_register((0x0040));                // enable FLL
	CSCTL4 = 0x0000;
	return 0;
}

unsigned char dummy_func()
{
	PAOUT = 0xFFFF;
	PAOUT = 0x0000;
	return 0;
}

unsigned char main()
{
	unsigned long int sec_start;
	global_sec_count = 0;
	msp430fr2476_init();
	timer1_cfg();	// enable timer1 and global_sec_count start to increase
	__enable_interrupt();
	__no_operation();
	__no_operation();

	sec_start = global_sec_count;
	while((global_sec_count - sec_start) <= 3)// wait 3 seconds
	{
//		dummy_func();
		__no_operation();
		__delay_cycles(((unsigned long int) 2000000) * 1 / ((unsigned long int)1));
		__no_operation();
	}
	__no_operation();
	return 0;
}
