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csl_usbAux.h
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    00001 /*  ============================================================================
    00002  *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
    00003  *
    00004  *   Use of this software is controlled by the terms and conditions found in the
    00005  *   license agreement under which this software has been supplied.
    00006  *  ============================================================================
    00007  */
    00008
    00016 /* ============================================================================
    00017  * Revision History
    00018  * ================
    00019  * 05-Sep-2008 Created
    00020  * 21-Jan-2009 Modified for code review comments
    00021  * 14-May-2009 Added DMA word swap work around for C5505 PG1.4
    00022  * 26-May-2009 Modified as per review comments
    00023  * 18-Jul-2009 Added support for DMA mode in USB_handleRx & USB_handleTx APIs
    00024  * 28-Jul-2009 Removed the commented code as per the review comments
    00025  * ============================================================================
    00026  */
    00027
    00028 #ifndef _CSL_USBAUX_H_
    00029 #define _CSL_USBAUX_H_
    00030
    00031 #ifdef __cplusplus
    00032 extern "C" {
    00033 #endif
    00034
    00035 #include <csl_intc.h>
    00036 #include <csl_usb.h>
    00037
    00039 extern CSL_UsbRegsOvly    usbRegisters;
    00041 extern CSL_SysRegsOvly    sysCtrlRegs;
    00042
    00082 static inline
    00083 CSL_Status USB_swapWords (Uint16    *dataBuffer,
    00084                           Uint32    dataLength)
    00085 {
    00086     CSL_Status    status;
    00087     Uint32        looper;
    00088     Uint16        tempData;
    00089
    00090     status = CSL_SOK;
    00091
    00092     /* Check the input parameters */
    00093     if ((dataBuffer != NULL) && (dataLength > 0))
    00094     {
    00095         /* Swap the words in the given buffer */
    00096         for (looper = 0; looper < dataLength/2; looper++)
    00097         {
    00098             tempData = *dataBuffer++;
    00099             *(dataBuffer -1) = *dataBuffer;
    00100             *dataBuffer++ = tempData;
    00101         }
    00102     }
    00103     else
    00104     {
    00105         status = CSL_ESYS_INVPARAMS;
    00106     }
    00107
    00108     return (status);
    00109 }
    00110
    00148 static inline
    00149 void USB_initDma(void)
    00150 {
    00151     Bool  value;
    00152
    00153     // save the
    00154     // disable the hardware interrupt to make sure the
    00155     // following operations are atomic
    00156     value = IRQ_globalDisable();
    00157     /* set TX queue manager number 0, queue number 24 */
    00158     usbRegisters->CHANNEL[0].TXGCR1 = CSL_USB_TXGCR1_RESETVAL;
    00159
    00160     /* enable TX channel 0 for EP1 */
    00161     usbRegisters->CHANNEL[0].TXGCR2 = CSL_USB_TXGCR2_TX_ENABLE_MASK;
    00162
    00163     /* Related to Channel info */
    00164     /* set teardown queue manager number 0, queue number 26
    00165      * set descriptor type to Host (value 1) [15:14]
    00166      */
    00167     usbRegisters->CHANNEL[1].RXGCR1 = CSL_USB_RXGCR1_DEFVAL;
    00168
    00169     /* enable RX channel 1. Channel 1 is for EP2
    00170      * set Starvation error result in dropping packet [24]
    00171      * set SOF offset 0 [23:16]
    00172      */
    00173     usbRegisters->CHANNEL[1].RXGCR2 = CSL_USB_RXGCR2_DEFVAL;
    00174
    00175     usbRegisters->CHANNEL[1].RXHPCR1A = CSL_USB_RXHPCR1A_RESETVAL;
    00176     usbRegisters->CHANNEL[1].RXHPCR2A = CSL_USB_RXHPCR2A_RESETVAL;
    00177     usbRegisters->CHANNEL[1].RXHPCR1B = CSL_USB_RXHPCR1B_RESETVAL;
    00178     usbRegisters->CHANNEL[1].RXHPCR2B = CSL_USB_RXHPCR2B_RESETVAL;
    00179     /* End:Related to Channel info */
    00180
    00181     /* Related to Scheduler Initialization */
    00182     /* setup Channel 1 (EP2) for RX */
    00183     usbRegisters->CDMASCHETBLWORD[0].ENTRYLSW = CSL_USB_ENTRYLSW_DEFVAL;
    00184     usbRegisters->CDMASCHETBLWORD[0].ENTRYMSW = CSL_USB_ENTRYMSW_RESETVAL;
    00185
    00186     /* setup 2 entries */
    00187     usbRegisters->DMA_SCHED_CTRL1 = CSL_USB_DMA_SCHED_CTRL1_DEFVAL;
    00188
    00189     /* enable scheduler */
    00190     usbRegisters->DMA_SCHED_CTRL2 = CSL_USB_DMA_SCHED_CTRL2_ENABLE_MASK;
    00191     /* Ends: Related to Scheduler Initialization */
    00192
    00193     // enable the hardware interrupt
    00194     IRQ_globalRestore(value);
    00195 }
    00196
    00197
    00232 static inline
    00233 CSL_Status USB_initQueueManager(CSL_UsbHostPktDescr    *hpdtx,
    00234                                 Uint32                 *pLinkingRam)
    00235 {
    00236     Uint32        u32Addr;
    00237     Uint16        u16CpyReg;
    00238     CSL_Status    status;
    00239     Bool          value;
    00240
    00241     status =  CSL_SOK;
    00242
    00243     if((hpdtx != NULL) && (pLinkingRam != NULL))
    00244     {
    00245         /* setup linking RAM 0 base address */
    00246         u32Addr   = (Uint32)pLinkingRam;
    00247         u16CpyReg = (Uint16)((u32Addr * 2) & CSL_USB_16BIT_REG_MASK);
    00248
    00249         // disable the hardware interrupt to make sure the
    00250         // following operations are atomic
    00251         value = IRQ_globalDisable();
    00252         usbRegisters->LRAM0BASE1 = u16CpyReg;
    00253         u16CpyReg = (Uint16)(((u32Addr * 2) >> CSL_USB_16BIT_REG_SHIFT) &
    00254                                                CSL_USB_16BIT_REG_MASK);
    00255         /* OR with 8 for SARAM */
    00256         usbRegisters->LRAM0BASE2 = u16CpyReg | 8;
    00257         /* setup linking RAM0 size */
    00258         usbRegisters->LRAM0SIZE  = CSL_USB_LRAM0SIZE_DEFVAL;
    00259
    00260         /* setup linking RAM 1 base address */
    00261         u32Addr   = (Uint32)pLinkingRam;
    00262         u16CpyReg = (Uint16)((u32Addr * 2) & CSL_USB_16BIT_REG_MASK);
    00263         usbRegisters->LRAM1BASE1 = (Uint16)u16CpyReg;
    00264         u16CpyReg = (Uint16)(((u32Addr * 2) >> CSL_USB_16BIT_REG_SHIFT) &
    00265                                                CSL_USB_16BIT_REG_MASK);
    00266         /* OR with 8 for SARAM */
    00267         usbRegisters->LRAM1BASE2 = u16CpyReg | 8;
    00268
    00269         /* setup memory region 0 base address */
    00270         u32Addr = (Uint32)(hpdtx);
    00271         u16CpyReg = (Uint16)((u32Addr * 2) & CSL_USB_16BIT_REG_MASK);
    00272         usbRegisters->QMMEMREGR[0].QMEMRBASE1 = u16CpyReg;
    00273
    00274         /* OR with 8 for SARAM */
    00275         u16CpyReg = (Uint16)( ((u32Addr * 2) >> CSL_USB_16BIT_REG_SHIFT) &
    00276                                                 CSL_USB_16BIT_REG_MASK);
    00277         usbRegisters->QMMEMREGR[0].QMEMRBASE2 = u16CpyReg | 8;
    00278
    00279         /* setup memory region control register 32 byte per descriptor and 32 descriptors  allowed */
    00280         usbRegisters->QMMEMREGR[0].QMEMRCTRL1 = 0x0000;//CSL_USB_QMEMRCTRL1_DEFVAL;
    00281         usbRegisters->QMMEMREGR[0].QMEMRCTRL2 = CSL_USB_QMEMRCTRL2_DEFVAL;
    00282         // enable the hardware interrupt
    00283         IRQ_globalRestore(value);
    00284     }
    00285     else
    00286     {
    00287         status =  CSL_ESYS_INVPARAMS;
    00288     }
    00289
    00290     return(status);
    00291 }
    00292
    00325 static inline
    00326 void USB_dmaPopQue(Uint16 queueNum)
    00327 {
    00328     Uint16 descTemp, countTemp;
    00329
    00330     countTemp = usbRegisters->QMQNS[queueNum].QSTATA;
    00331
    00332     while (countTemp > 0)
    00333     {
    00334         descTemp = usbRegisters->QMQN[queueNum].CTRL1D;
    00335         countTemp = usbRegisters->QMQNS[queueNum].QSTATA;
    00336
    00337         /* TO avoid compilation warnings */
    00338         descTemp= descTemp;
    00339         countTemp = countTemp;
    00340     }
    00341 }
    00342
    00383 static inline
    00384 void USB_dmaRxStart(DWORD    dwEndpoint)
    00385 {
    00386     Uint16    saveIndex;
    00387
    00388     /* save the index register value */
    00389     saveIndex = usbRegisters->INDEX_TESTMODE;
    00390
    00391     /* Write the endpoint configuration*/
    00392     usbRegisters->INDEX_TESTMODE  &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    00393     usbRegisters->INDEX_TESTMODE  |= dwEndpoint;
    00394
    00395     // clear AutoClear (bit 15) and DMAMode (bit 11)
    00396     usbRegisters->PERI_RXCSR_INDX &= 0x6FFF;
    00397
    00398     /* Enable the USB DMA for Rx operation */
    00399     usbRegisters->PERI_RXCSR_INDX |= CSL_USB_PERI_RXCSR_DMAEN_MASK;
    00400
    00401     /* restore the index register */
    00402     usbRegisters->INDEX_TESTMODE   = saveIndex;
    00403 }
    00404
    00446 static inline
    00447 CSL_Status USB_confDmaRx(CSL_UsbHostPktDescr    *hpdrx,
    00448                          Uint32                 packetsize,
    00449                          Uint16                 *pRxBuffer)
    00450 {
    00451     volatile Uint16    index;
    00452     CSL_Status         status;
    00453     Bool               value;
    00454
    00455     status = CSL_SOK;
    00456
    00457     if((hpdrx != NULL) && (pRxBuffer != NULL))
    00458     {
    00459         /* Set packet info word 0 */
    00460         hpdrx->PacketInfoWord0 = 0x80000000 | packetsize;
    00461         /* set source port, channel, sub-channel to 0 */
    00462         hpdrx->PacketInfoWord1 = 0;
    00463
    00464         /* set USB packet, return policy to entire, off-chip memory,
    00465          * return to Q manager 0 and Q 26
    00466          */
    00467         hpdrx->PacketInfoWord2  = 0x1400001A;
    00468         hpdrx->Buffer0InfoWord0 = packetsize;
    00469
    00470         /* buffer pointer in SARAM */
    00471         hpdrx->Buffer0InfoWord1 = ((Uint32)pRxBuffer) << 1 | 0x80000;
    00472
    00473         /* next descriptor */
    00474         hpdrx->LinkingWord = 0;
    00475         hpdrx->OriginalBuffer0InfoWord0 = packetsize;
    00476
    00477         /* buffer pointer in SARAM */
    00478         hpdrx->OriginalBuffer0InfoWord1 = ((Uint32)pRxBuffer) << 1 | 0x80000;
    00479
    00480         // disable the hardware interrupt to make sure the
    00481         // following operations are atomic
    00482         value = IRQ_globalDisable();
    00483         usbRegisters->QMQN[0].CTRL1D = ((((Uint32)hpdrx) << 1) &
    00484                                            CSL_USB_16BIT_REG_MASK) | 2;
    00485         usbRegisters->QMQN[0].CTRL2D = (((((Uint32)hpdrx) >> 15) &
    00486                                            CSL_USB_16BIT_REG_MASK) | 8);
    00487         // enable the hardware interrupt
    00488         IRQ_globalRestore(value);
    00489     }
    00490     else
    00491     {
    00492         status = CSL_ESYS_INVPARAMS;
    00493     }
    00494
    00495     return(status);
    00496 }
    00497
    00498
    00544 static inline
    00545 CSL_Status USB_confDmaTx(CSL_UsbHostPktDescr    *hpdtx,
    00546                          Uint32                 packetsize,
    00547                          Uint16                 *pTxBuffer,
    00548                          Bool                   swapWords)
    00549 {
    00550     CSL_Status    status;
    00551     Bool          value;
    00552
    00553     status = CSL_SOK;
    00554
    00555     if((hpdtx != NULL) && (pTxBuffer != NULL))
    00556     {
    00557         /* Swap the words in the data buffer */
    00558         if(TRUE == swapWords)
    00559         {
    00560             /* On VC5505 DSP, DMA will perform a word swap on the source buffer
    00561                before transferring it to the destination. During USB Tx a word
    00562                swap by software is required before DMA data transfer to ensure
    00563                that the data is transferred to the destination in proper order.
    00564                HW word swap by DMA will be compensated by the software word swap.
    00565              */
    00566             USB_swapWords (pTxBuffer, packetsize/2);
    00567         }
    00568
    00569         /* Set packet info word 0 */
    00570         hpdtx->PacketInfoWord0 = 0x80000000 | packetsize;
    00571         /* set source port, channel, sub-channel to 0 */
    00572         hpdtx->PacketInfoWord1 = 0;
    00573
    00574         /* set USB packet, return policy to entire, off-chip memory,
    00575          * return to Q manager 0 and Q 24
    00576          */
    00577         hpdtx->PacketInfoWord2  = 0x14000018;
    00578         hpdtx->Buffer0InfoWord0 = packetsize;
    00579
    00580         /* buffer pointer in SARAM */
    00581         hpdtx->Buffer0InfoWord1 = ((Uint32)pTxBuffer) << 1 | 0x80000;
    00582
    00583         /* next descriptor */
    00584         hpdtx->LinkingWord = 0;
    00585         hpdtx->OriginalBuffer0InfoWord0 = packetsize;
    00586
    00587         /* buffer pointer in SARAM */
    00588         hpdtx->OriginalBuffer0InfoWord1 = ((Uint32)pTxBuffer) << 1 | 0x80000;
    00589
    00590         // disable the hardware interrupt to make sure the
    00591         // following operations are atomic
    00592         value = IRQ_globalDisable();
    00593         /* add packet descriptor to queue */
    00594         usbRegisters->QMQN[16].CTRL1D = ((((Uint32)hpdtx) << 1) &
    00595                                               CSL_USB_16BIT_REG_MASK) | 2;
    00596         usbRegisters->QMQN[16].CTRL2D = (((((Uint32)hpdtx) >> 15) &
    00597                                              CSL_USB_16BIT_REG_MASK) | 8);
    00598         // enable the hardware interrupt
    00599         IRQ_globalRestore(value);
    00600     }
    00601     else
    00602     {
    00603         status = CSL_ESYS_INVPARAMS;
    00604     }
    00605
    00606     return(status);
    00607 }
    00608
    00654 static inline
    00655 void USB_dmaRxStop(DWORD     dwEndpoint,
    00656                    Uint16    *pRxBuffer,
    00657                    Uint32    packetsize,
    00658                    Bool      swapWords)
    00659 {
    00660     Uint16  saveIndex = 0;
    00661
    00662     /* save the index register value */
    00663     saveIndex = usbRegisters->INDEX_TESTMODE;
    00664
    00665     /*Write the endpoint configuration*/
    00666     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    00667     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    00668
    00669     usbRegisters->PERI_RXCSR_INDX &= ~CSL_USB_PERI_RXCSR_DMAEN_MASK;
    00670
    00671     /* restore the index register */
    00672     usbRegisters->INDEX_TESTMODE = saveIndex;
    00673
    00674     if(swapWords == TRUE)
    00675     {
    00676         /* Swap the words in Rx buffer */
    00677         /* On VC5505 DSP, DMA will perform a word swap on the source buffer
    00678            before transferring it to the destination. During USB Rx a word swap
    00679            by software is required after DMA data transfer to ensure that
    00680            the data is received in proper order.HW word swap by DMA will
    00681            be compensated by the software word swap.
    00682          */
    00683         USB_swapWords (pRxBuffer, packetsize/2);
    00684     }
    00685 }
    00686
    00729 static inline
    00730 void USB_dmaTxStart(DWORD    dwEndpoint)
    00731 {
    00732     Uint16  saveIndex;
    00733
    00734     /* save the index register value */
    00735     saveIndex = usbRegisters->INDEX_TESTMODE;
    00736
    00737     /* Write the endpoint configuration */
    00738     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    00739     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    00740
    00741     /* Flush the FIFO */
    00742     CSL_FINS(usbRegisters->PERI_CSR0_INDX, USB_PERI_TXCSR_FLUSHFIFO, TRUE);
    00743
    00744     /* clear auticlear (bit 15) and set DMA mode (bit 11) */
    00745     usbRegisters->PERI_CSR0_INDX &= 0x7FFF;
    00746     usbRegisters->PERI_CSR0_INDX |= 0x1000;
    00747
    00748     /* Enable the USB DMA */
    00749     usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_DMAEN_MASK;
    00750
    00751     /* restore the index register */
    00752     usbRegisters->INDEX_TESTMODE = saveIndex;
    00753 }
    00754
    00755
    00795 static inline
    00796 void USB_dmaTxStop(DWORD    dwEndpoint)
    00797 {
    00798     Uint16    saveIndex;
    00799
    00800     /* save the index register value */
    00801     saveIndex = usbRegisters->INDEX_TESTMODE;
    00802
    00803     /* Write the endpoint configuration */
    00804     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    00805     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    00806
    00807     /* Disable the USB DMA */
    00808     usbRegisters->PERI_CSR0_INDX &= ~CSL_USB_PERI_TXCSR_DMAEN_MASK;
    00809
    00810     /* restore the index register */
    00811     usbRegisters->INDEX_TESTMODE = saveIndex;
    00812 }
    00813
    00880 static inline
    00881 CSL_Status USB_handleTx(pUsbContext     pContext,
    00882                         DWORD           dwEndpoint)
    00883 {
    00884     DWORD           cbToWrite;
    00885     WORD            *pwBuffer;
    00886     DWORD           cbBuffer;
    00887     DWORD           cbWritten;
    00888     Uint16          count;
    00889     Uint16          saveIndex;
    00890     CSL_Status      status;
    00891     pUsbEpStatus    peps;
    00892     pUsbTransfer    pTransfer;
    00893     volatile ioport Uint16    *pFifoAddr;
    00894     volatile        Uint32 delay;
    00895
    00896     status    = CSL_SOK;
    00897     count     = 0;
    00898     saveIndex = 0;
    00899     cbWritten =0;
    00900
    00901     if(pContext != NULL)
    00902     {
    00903         peps = &pContext->pEpStatus[dwEndpoint];
    00904         pTransfer = peps->pTransfer;
    00905
    00906         if((pTransfer != NULL) && (pTransfer->fComplete == FALSE))
    00907         {
    00908             pwBuffer  = (WORD*)pTransfer->pvBuffer + pTransfer->cbTransferred/2;
    00909             cbBuffer  = (pTransfer->cbBuffer - pTransfer->cbTransferred);
    00910             pFifoAddr = (volatile ioport Uint16*)peps->pFifoAddr;
    00911
    00912             /* Min of input byte count and supported size */
    00913             cbToWrite = CSL_USB_MIN(cbBuffer, peps->dwPacketSizeAssigned);
    00914
    00915             /* No need to transfer the data if this flag is set */
    00916             if(pTransfer->ioFlags == CSL_USB_IOFLAG_NOT)
    00917             {
    00918                 pTransfer->fComplete = TRUE;
    00919             }
    00920             else
    00921             {
    00922                 if(peps->fStalled != TRUE)
    00923                 {
    00924                     /* Check if USB is configured for DMA */
    00925                     if(((cbToWrite == 512) || (cbToWrite == 64)) &&
    00926                        ((pContext->opMode == CSL_USB_OPMODE_DMA) ||
    00927                        (pContext->opMode == CSL_USB_OPMODE_DMA_TXONLY)))
    00928                     {
    00929                         pTransfer->cbTransferred += cbToWrite;
    00930                         pTransfer->prevTxferLen   = cbToWrite;
    00931
    00932                         USB_dmaTxStart(dwEndpoint);
    00933
    00934                         if (pTransfer->cbTransferred == pTransfer->cbBuffer)
    00935                         {
    00936                             pTransfer->fComplete = TRUE;
    00937                         }
    00938                         else
    00939                         {
    00940                             status = pContext->completeTransferCallback(pContext, peps);
    00941                         }
    00942                     }
    00943                     else
    00944                     {
    00945
    00946 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    00947
    00948                         /* TI MSC put the DATA length as the first WORD,
    00949                            bypass it */
    00950                         if((cbToWrite != 512) && ((cbToWrite != 64)))
    00951                         {
    00952                             pwBuffer++;
    00953                         }
    00954 #endif
    00955
    00956                         /* save the index register value */
    00957                         saveIndex = usbRegisters->INDEX_TESTMODE;
    00958
    00959                         /* Select the end point for data transfer */
    00960                         CSL_FINS(usbRegisters->INDEX_TESTMODE,
    00961                                  USB_INDEX_TESTMODE_EPSEL,
    00962                                  CSL_USB_INDEX_TESTMODE_EPSEL_RESETVAL);
    00963
    00964                         CSL_FINS(usbRegisters->INDEX_TESTMODE,
    00965                                  USB_INDEX_TESTMODE_EPSEL,
    00966                                  dwEndpoint);
    00967
    00968                         /* Flush the FIFO */
    00969                         CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    00970                                  USB_PERI_TXCSR_FLUSHFIFO, TRUE);
    00971
    00972                         if(cbToWrite > 0)
    00973                         {
    00974                             /* write out all the bytes */
    00975                             cbWritten = cbToWrite;
    00976
    00977                             for(count = 0; count < (cbToWrite/2); count++)
    00978                             {
    00979                                 *pFifoAddr = *pwBuffer++;
    00980                             }
    00981
    00982                             if(cbToWrite % 2)
    00983                             {
    00984                                 /* Enable byte access */
    00985                                 CSL_FINST(sysCtrlRegs->USBSCR,
    00986                                           SYS_USBSCR_BYTEMODE, LOWER);
    00987                                 CSL_FINS(*pFifoAddr, USB_FIFO1R1_DATA,
    00988                                          *pwBuffer);
    00989                                 /* Disable byte access */
    00990                                 CSL_FINST(sysCtrlRegs->USBSCR,
    00991                                           SYS_USBSCR_BYTEMODE, FULL);
    00992                             }
    00993                         }
    00994
    00995                         if(peps->xferType == CSL_USB_ISO)
    00996                         {
    00997                             usbRegisters->PERI_CSR0_INDX |=
    00998                                             CSL_USB_PERI_TXCSR_CLRDATATOG_MASK;
    00999                         }
    01000
    01001                         /* Commit Tx Packet */
    01002                         CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    01003                                  USB_PERI_CSR0_INDX_RXPKTRDY, TRUE);
    01004
    01005                         /* restore the index register */
    01006                         usbRegisters->INDEX_TESTMODE = saveIndex;
    01007
    01008                         /* Update the Transferred count */
    01009                         pTransfer->cbTransferred += cbWritten;
    01010                         pTransfer->prevTxferLen   = cbWritten;
    01011
    01012                         if((pTransfer->cbTransferred == pTransfer->cbBuffer) ||
    01013                            (cbWritten == 0))
    01014                         {
    01015                             pTransfer->fComplete = TRUE;
    01016                         }
    01017                     }
    01018                 }
    01019             }
    01020
    01021             if (pTransfer->fComplete)
    01022             {
    01023                 pContext->fWaitingOnFlagA = FALSE;
    01024                 status = pContext->completeTransferCallback(pContext, peps);
    01025             }
    01026         }
    01027         else
    01028         {
    01029             status = CSL_ESYS_INVPARAMS;
    01030         }
    01031     }
    01032     else
    01033     {
    01034         status = CSL_ESYS_INVPARAMS;
    01035     }
    01036
    01037     return(status);
    01038 }
    01039
    01106 static inline
    01107 CSL_Status USB_handleRx(pUsbContext     pContext,
    01108                         DWORD           dwEndpoint)
    01109 {
    01110     DWORD               cbToRead;
    01111     DWORD               cbBuffer;
    01112     DWORD               dwBytesRead;
    01113     WORD                *pwBuffer;
    01114     pUsbTransfer        pTransfer;
    01115     CSL_Status          status;
    01116     Uint16              saveIndex;
    01117     pUsbEpStatus        peps;
    01118     volatile Uint16     count;
    01119     volatile ioport Uint16    *pFifoAddr;
    01120
    01121     status      = CSL_SOK;
    01122     dwBytesRead = 0;
    01123
    01124     if(pContext != NULL)
    01125     {
    01126         peps = &pContext->pEpStatus[dwEndpoint];
    01127         pTransfer = peps->pTransfer;
    01128
    01129         if((pTransfer != NULL) && (pTransfer->fComplete == FALSE))
    01130         {
    01131             cbBuffer = pTransfer->cbBuffer - pTransfer->cbTransferred;
    01132             pwBuffer = (WORD*)pTransfer->pvBuffer + pTransfer->cbTransferred/2;
    01133             pFifoAddr   = (volatile ioport Uint16*)peps->pFifoAddr;
    01134
    01135             /* Min of input byte count and supported size */
    01136             cbToRead = CSL_USB_MIN(cbBuffer, peps->dwPacketSizeAssigned);
    01137
    01138             if(((cbToRead == 512) || (cbToRead == 64)) &&
    01139                 (pContext->opMode == CSL_USB_OPMODE_DMA))
    01140             {
    01141                 pTransfer->cbTransferred += cbToRead;
    01142                 pTransfer->prevTxferLen   = cbToRead;
    01143
    01144                 USB_dmaRxStart(dwEndpoint);
    01145
    01146                 if (pTransfer->cbTransferred == pTransfer->cbBuffer)
    01147                 {
    01148                     pTransfer->fComplete = TRUE;
    01149                     pContext->fWaitingOnFlagB = FALSE;
    01150                 }
    01151
    01152                 status = pContext->completeTransferCallback(pContext, peps);
    01153             }
    01154             else
    01155             {
    01156
    01157 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    01158
    01159                 /* TI MSC put the DATA length as the first WORD, bypass it */
    01160                 if((cbToRead != 512) && ((cbToRead != 64)))
    01161                 {
    01162                     pwBuffer++;
    01163                 }
    01164 #endif
    01165
    01166                 if(cbToRead > 0)
    01167                 {
    01168                     /* Write out all the bytes */
    01169                     dwBytesRead = cbToRead;
    01170
    01171                     for(count = 0; count < (cbToRead/2); count++)
    01172                     {
    01173                         *pwBuffer++ = *pFifoAddr;
    01174                     }
    01175
    01176                     if(cbToRead % 2)
    01177                     {
    01178                         /* Enable byte access */
    01179                         CSL_FINST(sysCtrlRegs->USBSCR,
    01180                                   SYS_USBSCR_BYTEMODE, LOWER);
    01181                         *pwBuffer = *pFifoAddr & 0xFF;
    01182
    01183                         /* Disable byte access */
    01184                         CSL_FINST(sysCtrlRegs->USBSCR,
    01185                                   SYS_USBSCR_BYTEMODE, FULL);
    01186                     }
    01187                 }
    01188
    01189                 pTransfer->cbTransferred += dwBytesRead;
    01190                 pTransfer->prevTxferLen   = dwBytesRead;
    01191
    01192                 if((pTransfer->cbTransferred == pTransfer->cbBuffer) ||
    01193                    (dwBytesRead == 0))
    01194                 {
    01195                     pTransfer->fComplete = TRUE;
    01196                 }
    01197
    01198                 /* Save the index register value */
    01199                 saveIndex = usbRegisters->INDEX_TESTMODE;
    01200
    01201                 CSL_FINS(usbRegisters->INDEX_TESTMODE,
    01202                          USB_INDEX_TESTMODE_EPSEL,
    01203                          CSL_USB_INDEX_TESTMODE_EPSEL_RESETVAL);
    01204
    01205                 CSL_FINS(usbRegisters->INDEX_TESTMODE,
    01206                          USB_INDEX_TESTMODE_EPSEL, dwEndpoint);
    01207
    01208                 if(peps->xferType == CSL_USB_ISO)
    01209                 {
    01210                     /* Clear the data toggle bit */
    01211                     usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);
    01212                 }
    01213
    01214                 /* Clear the rxpktrdy bit */
    01215                 CSL_FINS(usbRegisters->PERI_RXCSR_INDX,
    01216                          USB_PERI_RXCSR_RXPKTRDY, FALSE);
    01217
    01218                 /* Restore the index register */
    01219                 usbRegisters->INDEX_TESTMODE = saveIndex;
    01220
    01221                 if(pTransfer->fComplete == TRUE)
    01222                 {
    01223                     pContext->fWaitingOnFlagB = FALSE;
    01224
    01225                     /* This transfer is completed */
    01226 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    01227                     /* TI MSC put the DATA length as the first WORD, bypass it */
    01228                     if((cbToRead != 512) && (cbToRead != 64))
    01229                     {
    01230                         *(PWORD)pTransfer->pvBuffer = pTransfer->cbTransferred;
    01231                     }
    01232 #endif
    01233
    01234                     status = pContext->completeTransferCallback(pContext, peps);
    01235                 }
    01236             }
    01237         }
    01238         else
    01239         {
    01240             status = CSL_ESYS_INVPARAMS;
    01241         }
    01242     }
    01243     else
    01244     {
    01245         status = CSL_ESYS_INVPARAMS;
    01246     }
    01247
    01248     return(status);
    01249 }
    01250
    01296 static inline
    01297 CSL_Status USB_processEP0Out(pUsbContext    pContext)
    01298 {
    01299     pUsbEpStatus    peps;
    01300     pUsbTransfer    pTransfer;
    01301     WORD            *pwBuffer;
    01302     CSL_Status      status;
    01303
    01304     status = CSL_SOK;
    01305
    01306     if(pContext != NULL)
    01307     {
    01308         peps = &pContext->pEpStatus[CSL_USB_EP0];
    01309         pTransfer = peps->pTransfer;
    01310
    01311         if((pTransfer != NULL) && (pTransfer->fComplete == FALSE))
    01312         {
    01313             /* for none-last packet, it is always WORD align */
    01314             pwBuffer = (WORD*)pTransfer->pvBuffer + pTransfer->cbTransferred/2;
    01315
    01316 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    01317
    01318             /* TI MSC put the DATA length as the first WORD, bypass it */
    01319             (WORD*)pwBuffer++;
    01320 #endif
    01321
    01322             /* move data from ep0 fifo to ep buffer */
    01323             pTransfer->cbTransferred = CSL_USB_MIN(pContext->cbOutEP0Buf,
    01324                                                    pTransfer->cbBuffer);
    01325
    01326             memcpy(pwBuffer, (PVOID)pContext->dwOutEP0Buf,
    01327                    (pTransfer->cbTransferred+1)/2);
    01328
    01329             pContext->fOutPhaseCmd  = FALSE;
    01330             pTransfer->fComplete    = TRUE;
    01331             pTransfer->prevTxferLen = pTransfer->cbTransferred;
    01332
    01333 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    01334             /* This transfer is completed */
    01335             *(PWORD)pTransfer->pvBuffer = pTransfer->cbTransferred;
    01336 #endif
    01337             status = pContext->completeTransferCallback(pContext, peps);
    01338         }
    01339         else
    01340         {
    01341             status = CSL_ESYS_INVPARAMS;
    01342         }
    01343     }
    01344     else
    01345     {
    01346         status = CSL_ESYS_INVPARAMS;
    01347     }
    01348     return(status);
    01349 }
    01350
    01396 #if 1
    01397 static inline
    01398 CSL_Status USB_processEP0In(pUsbContext     pContext)
    01399 {
    01400     pUsbEpStatus    peps;
    01401     pUsbTransfer    pTransfer;
    01402     CSL_Status      status;
    01403     PWORD           pwBuffer;
    01404     DWORD           cbBuffer;
    01405     WORD            cbToWrite;
    01406     Uint16          count;
    01407     Uint16          flag;
    01408     Uint16          saveIndex;
    01409
    01410     flag   = 0;
    01411     status = CSL_SOK;
    01412
    01413     if(pContext != NULL)
    01414     {
    01415         peps = &pContext->pEpStatus[CSL_USB_EP0];
    01416         pTransfer = peps->pTransfer;
    01417
    01418         if((pTransfer != NULL) && (pTransfer->fComplete == FALSE))
    01419         {
    01420             /* for none-last packet, it is always WORD align */
    01421             pwBuffer = (PWORD)pTransfer->pvBuffer + pTransfer->cbTransferred/2;
    01422             cbBuffer = pTransfer->cbBuffer - pTransfer->cbTransferred;
    01423
    01424 #if ((defined(CSL_MSC_TEST)) || (defined(CSL_AC_TEST)))
    01425             /* TI MSC put the DATA length as the first WORD, bypass it */
    01426             pwBuffer++;
    01427 #endif
    01428
    01429             /* Min of input byte count and supported size */
    01430             cbToWrite = CSL_USB_MIN(cbBuffer, peps->dwPacketSizeAssigned);
    01431
    01432             while(TRUE)
    01433             {
    01434                 /* write data to EP0 FIFO */
    01435                 for(count = 0; count < cbToWrite/2;count++)
    01436                 {
    01437                     usbRegisters->FIFO0R1 = (*pwBuffer);
    01438                     pwBuffer++;
    01439                 }
    01440
    01441                 if(cbToWrite % 2 == TRUE)
    01442                 {
    01443                     /* Enable byte access */
    01444                     CSL_FINST(sysCtrlRegs->USBSCR, SYS_USBSCR_BYTEMODE, LOWER);
    01445                     usbRegisters->FIFO0R1 = (*pwBuffer);
    01446                     /* Disable byte access */
    01447                     CSL_FINST(sysCtrlRegs->USBSCR, SYS_USBSCR_BYTEMODE, FULL);
    01448                 }
    01449
    01450                 /* update the remainder data length, we may need zero length */
    01451                 if(cbToWrite <= CSL_USB_MAX_EP0_FIFO_LEN)
    01452                 {
    01453                     break;
    01454                 }
    01455                 else
    01456                 {
    01457                     cbToWrite -= CSL_USB_MAX_EP0_FIFO_LEN;
    01458                 }
    01459             }
    01460
    01461             pContext->fEP0BUFAvailable = FALSE;
    01462
    01463             pTransfer->cbTransferred += cbToWrite;
    01464             pTransfer->prevTxferLen   = cbToWrite;
    01465             if(pTransfer->cbTransferred == pTransfer->cbBuffer)
    01466             {
    01467                 pTransfer->fComplete  = TRUE;
    01468             }
    01469
    01470             /* save the index register value */
    01471             saveIndex = usbRegisters->INDEX_TESTMODE;
    01472
    01473             /* Reset Index register end point selection field */
    01474             CSL_FINS(usbRegisters->INDEX_TESTMODE,
    01475                      USB_INDEX_TESTMODE_EPSEL,
    01476                      CSL_USB_INDEX_TESTMODE_EPSEL_RESETVAL);
    01477
    01478             /* Select Ep 0 */
    01479             CSL_FINS(usbRegisters->INDEX_TESTMODE,
    01480                      USB_INDEX_TESTMODE_EPSEL,
    01481                      CSL_USB_EP0);
    01482
    01483             if(pTransfer->fComplete  == TRUE)
    01484             {
    01485                 pContext->fWaitingOnEP0BUFAvail = FALSE;
    01486
    01487                 /* set txpktrdy and data end */
    01488                 flag = (CSL_USB_PERI_CSR0_INDX_DATAEND_MASK |
    01489                         CSL_USB_PERI_CSR0_INDX_TXPKTRDY_MASK);
    01490                 /* change ep0 state to EP0_IDLE */
    01491                 pContext->ep0State = CSL_USB_EP0_IDLE;
    01492                 /* Commit Tx packet */
    01493                 usbRegisters->PERI_CSR0_INDX |= flag;
    01494
    01495                 status = pContext->completeTransferCallback(pContext, peps);
    01496             }
    01497             else
    01498             {
    01499                 /* set txpktrdy */
    01500                 flag = CSL_USB_PERI_CSR0_INDX_TXPKTRDY_MASK;
    01501
    01502                 /* Commit Tx packet */
    01503                 usbRegisters->PERI_CSR0_INDX |= flag;
    01504             }
    01505
    01506             /* restore the index register */
    01507             usbRegisters->INDEX_TESTMODE = saveIndex;
    01508         }
    01509         else
    01510         {
    01511             status = CSL_ESYS_INVPARAMS;
    01512         }
    01513     }
    01514     else
    01515     {
    01516         status = CSL_ESYS_INVPARAMS;
    01517     }
    01518
    01519     return(status);
    01520 }
    01521 #endif
    01522
    01569 static inline
    01570 void USB_handleRxIntr(pUsbContext     pContext)
    01571 {
    01572     Uint16          saveIndex;
    01573     pUsbEpStatus    peps;
    01574
    01575     peps = &pContext->pEpStatus[CSL_USB_EP2];
    01576     saveIndex = 0;
    01577
    01578     /* save the index register value */
    01579     saveIndex = usbRegisters->INDEX_TESTMODE;
    01580
    01581     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01582     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP2;
    01583
    01584     /* check if RxPktRdy bit is set */
    01585     if((usbRegisters->PERI_RXCSR_INDX & CSL_USB_PERI_RXCSR_RXPKTRDY_MASK)
    01586        == CSL_USB_PERI_RXCSR_RXPKTRDY_MASK)
    01587     {
    01588         if(peps->xferType == CSL_USB_ISO)
    01589         {
    01590             pContext->fSetupPktCmd = TRUE;
    01591         }
    01592         else
    01593         {
    01594             pContext->fWaitingOnFlagB = TRUE;
    01595         }
    01596     }
    01597
    01598     /* restore the index register */
    01599     usbRegisters->INDEX_TESTMODE = saveIndex;
    01600 }
    01601
    01645 static inline
    01646 void USB_handleTxIntr(pUsbContext     pContext)
    01647 {
    01648     Uint16          saveIndex;
    01649
    01650     saveIndex = 0;
    01651
    01652     /* Save the index register value */
    01653     saveIndex = usbRegisters->INDEX_TESTMODE;
    01654
    01655     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01656     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP1;
    01657
    01658     /* Check if sendstall bit is set */
    01659     if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_INDX_SENDSTALL_MASK)
    01660        == CSL_USB_PERI_TXCSR_INDX_SENDSTALL_MASK)
    01661     {
    01662         CSL_FINS(usbRegisters->PERI_CSR0_INDX, USB_PERI_TXCSR_SENDSTALL, FALSE);
    01663     }
    01664
    01665     /* Restore the index register */
    01666     usbRegisters->INDEX_TESTMODE = saveIndex;
    01667 }
    01668
    01717 static inline
    01718 Bool USB_checkSpeed(pUsbContext        pContext,
    01719                     CSL_UsbBusSpeed    *pBusSpeed)
    01720 {
    01721     Uint16    wPower;
    01722
    01723     wPower = usbRegisters->FADDR_POWER;
    01724
    01725     if((wPower == 0) || (pBusSpeed == NULL))
    01726     {
    01727         return (FALSE);
    01728     }
    01729
    01730     /*
    01731      * Highspeed mode bit of the power register will be set if the USB
    01732      * successfully negotiates with host for operating in highspeed mode
    01733      */
    01734     if((usbRegisters->FADDR_POWER & CSL_USB_FADDR_POWER_HSMODE_MASK) != 0)
    01735     {
    01736         *pBusSpeed = CSL_USB_BS_HIGH_SPEED;
    01737     }
    01738     else
    01739     {
    01740         *pBusSpeed = CSL_USB_BS_FULL_SPEED;
    01741     }
    01742
    01743     return (TRUE);
    01744 }
    01745
    01792 static inline
    01793 void USB_readEP0Buf(pUsbContext    pContext,
    01794                     DWORD          *pBuf)
    01795 {
    01796     WORD    packetSize;
    01797     Uint16  saveIndex;
    01798     WORD    count = 0;
    01799     Uint32  tempStore;
    01800     Uint16  flag;
    01801
    01802     saveIndex  = 0;
    01803     packetSize = 0;
    01804     flag       = 0;
    01805
    01806     /* save the index register value */
    01807     saveIndex = (usbRegisters->INDEX_TESTMODE &
    01808                  CSL_USB_INDEX_TESTMODE_EPSEL_MASK);
    01809
    01810     /* select EP0 registers */
    01811     usbRegisters->INDEX_TESTMODE &= ~(CSL_USB_INDEX_TESTMODE_EPSEL_MASK);
    01812     /* get RX packet size */
    01813     packetSize = ((usbRegisters->COUNT0_INDX) &
    01814                   CSL_USB_COUNT0_INDX_EP0RXCOUNT_MASK);
    01815
    01816     if((packetSize > CSL_USB_MAX_EP0_FIFO_LEN) ||
    01817        (packetSize > pContext->cbOutEP0DataReceived))
    01818     {
    01819         /* restore the index register */
    01820         usbRegisters->INDEX_TESTMODE &= ~(CSL_USB_INDEX_TESTMODE_EPSEL_MASK);
    01821         usbRegisters->INDEX_TESTMODE |= saveIndex;
    01822         return;
    01823     }
    01824
    01825     pBuf = pContext->dwOutEP0Buf;
    01826
    01827     for(count = 0; count < packetSize; count += 4)
    01828     {
    01829         *pBuf = 0;
    01830         tempStore = 0;
    01831         *pBuf = usbRegisters->FIFO0R1;
    01832         tempStore = usbRegisters->FIFO0R1;
    01833         *pBuf |= (tempStore << 16);
    01834         pBuf++;
    01835     }
    01836
    01837     pContext->cbOutEP0DataReceived -= packetSize;
    01838
    01839     if(pContext->cbOutEP0DataReceived == 0)
    01840     {
    01841         /* set DataEnd bit */
    01842         flag = CSL_USB_PERI_CSR0_INDX_DATAEND_MASK;
    01843     }
    01844
    01845     /* set the ServicedRxPktRdy bit */
    01846     flag |= CSL_USB_PERI_CSR0_INDX_SERV_RXPKTRDY_MASK;
    01847     usbRegisters->PERI_CSR0_INDX |= flag;
    01848
    01849     /* restore the index register */
    01850     usbRegisters->INDEX_TESTMODE &= ~(CSL_USB_INDEX_TESTMODE_EPSEL_MASK);
    01851     usbRegisters->INDEX_TESTMODE |= saveIndex;
    01852 }
    01853
    01901 static inline
    01902 void USB_setConfiguration(CSL_UsbDevNum    devNum,
    01903                           Uint16           confVal)
    01904 {
    01905     Uint16 saveIndex;
    01906     Uint16  tempVal;
    01907
    01908     saveIndex = 0;
    01909
    01910     /* save the index register value */
    01911     saveIndex = usbRegisters->INDEX_TESTMODE;
    01912
    01913     /* Configure EP1 for Tx and Rx */
    01914     /* Select EP1 */
    01915     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01916     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP1;
    01917
    01918     /* set ClrDataTog bit (TxCSR.D6) */
    01919     usbRegisters->PERI_CSR0_INDX |= (CSL_USB_PERI_TXCSR_CLRDATATOG_MASK);
    01920     /* set ClrDataTog bit (RxCSR.D7) */
    01921     usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);
    01922
    01923     /* Flush FIFO if not empty */
    01924     if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK) ==
    01925        CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK)
    01926     {
    01927         //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01928
    01929         tempVal = usbRegisters->PERI_CSR0_INDX;
    01930
    01931         tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01932         tempVal &= ~(0x03);
    01933
    01934         usbRegisters->PERI_CSR0_INDX = tempVal;
    01935     }
    01936
    01937     /* Configure EP2 for Tx and Rx */
    01938     /* Select EP2 */
    01939     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01940     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP2;
    01941
    01942     /* set ClrDataTog bit (TxCSR.D6) */
    01943     usbRegisters->PERI_CSR0_INDX |= (CSL_USB_PERI_TXCSR_CLRDATATOG_MASK);
    01944     /* set ClrDataTog bit (RxCSR.D7) */
    01945     usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);
    01946
    01947     /* Flush FIFO if not empty */
    01948     if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK) ==
    01949        CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK)
    01950     {
    01951         //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01952
    01953         tempVal = usbRegisters->PERI_CSR0_INDX;
    01954
    01955         tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01956         tempVal &= ~(0x03);
    01957
    01958         usbRegisters->PERI_CSR0_INDX = tempVal;
    01959     }
    01960
    01961     /* Configure EP3 for Tx and Rx */
    01962     /* Select EP3 */
    01963     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01964     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP3;
    01965
    01966     /* set ClrDataTog bit (TxCSR.D6) */
    01967     usbRegisters->PERI_CSR0_INDX |= (CSL_USB_PERI_TXCSR_CLRDATATOG_MASK);
    01968     /* set ClrDataTog bit (RxCSR.D7) */
    01969     usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);
    01970
    01971     /* Flush FIFO if not empty */
    01972     if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK) ==
    01973        CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK)
    01974     {
    01975         //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01976
    01977         tempVal = usbRegisters->PERI_CSR0_INDX;
    01978
    01979         tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    01980         tempVal &= ~(0x03);
    01981
    01982         usbRegisters->PERI_CSR0_INDX = tempVal;
    01983     }
    01984
    01985     /* Configure EP4 for Tx and Rx */
    01986     /* Select EP4 */
    01987     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    01988     usbRegisters->INDEX_TESTMODE |= CSL_USB_EP4;
    01989
    01990     /* set ClrDataTog bit (TxCSR.D6) */
    01991     usbRegisters->PERI_CSR0_INDX |= (CSL_USB_PERI_TXCSR_CLRDATATOG_MASK);
    01992     /* set ClrDataTog bit (RxCSR.D7) */
    01993     usbRegisters->PERI_RXCSR_INDX |= (CSL_USB_PERI_RXCSR_CLRDATATOG_MASK);
    01994
    01995     /* Flush FIFO if not empty */
    01996     if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK) ==
    01997        CSL_USB_PERI_TXCSR_FIFONOTEMPTY_MASK)
    01998     {
    01999         //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    02000
    02001         tempVal = usbRegisters->PERI_CSR0_INDX;
    02002
    02003         tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    02004         tempVal &= ~(0x03);
    02005
    02006         usbRegisters->PERI_CSR0_INDX = tempVal;
    02007     }
    02008
    02009     /* restore the index register */
    02010     usbRegisters->INDEX_TESTMODE = saveIndex;
    02011 }
    02012
    02060 static inline
    02061 Bool USB_isValidDataInFifoOut(pUsbEpStatus    peps)
    02062 {
    02063     Uint16    saveIndex;
    02064     Uint16    wByteCount;
    02065     Uint16    flag;
    02066
    02067     saveIndex  = 0;
    02068     wByteCount = 0;
    02069     flag       = FALSE;
    02070
    02071     if(CSL_USB_EP2 == peps->dwEndpoint)
    02072     {
    02073         /* save the index register value */
    02074         saveIndex = usbRegisters->INDEX_TESTMODE;
    02075
    02076         usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    02077             usbRegisters->INDEX_TESTMODE |= CSL_USB_EP2;
    02078
    02079         /* check if RxPktRdy is set */
    02080         if((usbRegisters->PERI_RXCSR_INDX & CSL_USB_PERI_RXCSR_RXPKTRDY_MASK) ==
    02081             CSL_USB_PERI_RXCSR_RXPKTRDY_MASK)
    02082         {
    02083             wByteCount = usbRegisters->COUNT0_INDX & 0xFF;
    02084             peps->dataReadFromFifo = wByteCount;
    02085
    02086             if(peps->xferType != CSL_USB_ISO)
    02087             {
    02088             if((wByteCount <= peps->dwPacketSizeAssigned))
    02089             {
    02090                 /* packet is valid only if RxPktRdy is TRUE and
    02091                   Bytes in FIFO is <= max pkt size assigned for the EP */
    02092                 flag = TRUE;
    02093             }
    02094         }
    02095             else
    02096             {
    02097                 flag = TRUE;
    02098             }
    02099         }
    02100
    02101         /* restore the index register */
    02102        usbRegisters->INDEX_TESTMODE = saveIndex;
    02103     }
    02104
    02105     return(flag);
    02106 }
    02107
    02142 static inline
    02143 void USB_flushFifo(DWORD    dwEndpoint,
    02144                    Bool     fifoDirFlag)
    02145 {
    02146     Uint16 saveIndex;
    02147     Uint16 tempVal;
    02148
    02149     saveIndex = 0;
    02150
    02151     /* save the index register value */
    02152     saveIndex = usbRegisters->INDEX_TESTMODE;
    02153
    02154     /* Select end point */
    02155     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    02156     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    02157
    02158     if (dwEndpoint == CSL_USB_EP0)
    02159     {
    02160         /* Flush EP0 FIFO */
    02161         usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_CSR0_INDX_FLUSHFIFO_MASK;
    02162     }
    02163     else
    02164     {
    02165         if (1 == fifoDirFlag)
    02166         {
    02167             /* Flush Tx FIFO of given end point */
    02168             //usbRegisters->PERI_CSR0_INDX |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    02169             tempVal = usbRegisters->PERI_CSR0_INDX;
    02170
    02171             tempVal |= CSL_USB_PERI_TXCSR_FLUSHFIFO_MASK;
    02172             tempVal &= ~(0x03);
    02173
    02174             usbRegisters->PERI_CSR0_INDX = tempVal;
    02175         }
    02176         else
    02177         {
    02178             /* Flush Rx FIFO of given end point */
    02179             usbRegisters->PERI_RXCSR_INDX |=CSL_USB_PERI_RXCSR_FLUSHFIFO_MASK;
    02180         }
    02181     }
    02182
    02183     /* Restore the index register */
    02184     usbRegisters->INDEX_TESTMODE = saveIndex;
    02185 }
    02186
    02219 static inline
    02220 void USB_serviceEp0RxPkt(Uint16    periCsr0Val)
    02221 {
    02222     usbRegisters->PERI_CSR0_INDX |= periCsr0Val;
    02223 }
    02224
    02225 static inline
    02226 void USB_sendEpZLP(DWORD    dwEndpoint)
    02227 {
    02228     Uint16 saveIndex;
    02229
    02230     /* save the index register value */
    02231     saveIndex = usbRegisters->INDEX_TESTMODE;
    02232
    02233     /* Select end point */
    02234     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    02235     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    02236
    02237     // send zero length packet
    02238     CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    02239              USB_PERI_CSR0_INDX_TXPKTRDY, TRUE);
    02240     CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    02241              USB_PERI_CSR0_INDX_DATAEND, TRUE);
    02242
    02243     /* Restore the index register */
    02244     usbRegisters->INDEX_TESTMODE = saveIndex;
    02245 }
    02246
    02247 static inline
    02248 void USB_clearEpRxPktRdy(DWORD    dwEndpoint)
    02249 {
    02250     Uint16 saveIndex;
    02251
    02252     /* save the index register value */
    02253     saveIndex = usbRegisters->INDEX_TESTMODE;
    02254
    02255     /* Select end point */
    02256     usbRegisters->INDEX_TESTMODE &= ~CSL_USB_INDEX_TESTMODE_EPSEL_MASK;
    02257     usbRegisters->INDEX_TESTMODE |= dwEndpoint;
    02258
    02259     // send zero length packet
    02260     CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    02261              USB_PERI_CSR0_INDX_SERV_RXPKTRDY, TRUE);
    02262     CSL_FINS(usbRegisters->PERI_CSR0_INDX,
    02263              USB_PERI_CSR0_INDX_DATAEND, TRUE);
    02264
    02265     /* Restore the index register */
    02266     usbRegisters->INDEX_TESTMODE = saveIndex;
    02267 }
    02268
    02269 #ifdef __cplusplus
    02270 }
    02271 #endif
    02272
    02273 #endif    //_CSL_USBAUX_H_
    02274