C55XX CSL EXAMPLE

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DMA EXAMPLE DOCUMENTATION

## DMA EXAMPLE1 - POLLED MODE TEST

### TEST DESCRIPTION:

This test verifies the operation of the CSL DMA module in polled mode. C5505/C5515 DSP is having four DMA Engines and each DMA engine is having four channels for the data transfers. Total 16 channels can be configured and used for the data transfer simultaneously. DMA can be used to transfer data with in the memory and between the memory and peripherals with out having intervention of the CPU.

During the test DMA functionality is verified by transferring the data between two buffers allocated in memory of C5505/C5515 DSP. Data in the source buffer 'dmaSRCBuff' is copied into the destination buffer 'dmaDESTBuff'. DMA is configured with proper source and destination address and data length using DMA_config() API. Configured values are read back using DMA_getConfig() API and are verified with the original values. DMA data transfer is triggered using DMA_start() API. DMA transfer completion is detected by polling on the DMA start bit using DMA_getStatus() API. After the transfer completion data in the source and destination buffer is compared. The same test procedure is repeated on all the 16 DMA channels.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_DMA_PollExample.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- DMA configuration values should be read back and verified successfully
- DMA transfer should be successful and source and destination data should match on all the 16 DMA channels

=============================================================================

## DMA EXAMPLE2 - INTERRUPT MODE TEST

### TEST DESCRIPTION:

This test verifies operation of the CSL DMA module in interrupt mode. C5505/C5515 DSP is having four DMA Engines and each DMA engine is having four channels for the data transfers. Total 16 channels can be configured and used for the data transfer simultaneously. DMA can be used to transfer data with in the memory and between the memory and peripherals with out having the intervention of CPU.

During the test DMA functionality is verified by transferring the data between two buffers allocated in memory of C5505/C5515 DSP. Data in the source buffer 'dmaSRCBuff' is copied into the destination buffer 'dmaDESTBuff'. DMA interrupts are configured and DMA ISR is registered using CSL INTC module. DMA ISR will be triggered by the DMA transfer completion interrupt. DMA is configured with proper source and destination address and data length using DMA_config() API. Configured values are read back using DMA_getConfig() API and are verified with the original values. DMA data transfer is triggered using DMA_start() API. After starting the DMA data transfer execution of the test will wait for the occurrence of DMA transfer interrupt. This is done by checking a global variable which will be updated by the DMA ISR. After the transfer completion data in the source and destination buffers is compared. The same test procedure is repeated on all the 16 DMA channels.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target
- Open the project "CSL_DMA_IntcExample.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- DMA configuration values should be read back and verified successfully
- DMA transfer should be successful and source and destination data should match on all the 16 DMA channels

=============================================================================

## DMA EXAMPLE3 - STOP API TEST

### TEST DESCRIPTION:

This test verifies the functionality of DMA_stop() API of the CSL DMA module. This API is not required during normal mode operation of the DMA module. DMA transfer will be stopped automatically after transferring the configured length of data in normal mode of operation. DMA_stop() API is useful in two cases. One case is when DMA is operating in auto-reload mode and it is required to stop the DMA data transfer. Second case is DMA transfer is started in normal mode but it is required to abort the data transfer before the normal completion. This test verifies the functionality of DMA stop API by aborting the data transfer while DMA is transferring the data in normal mode of operation.

During the test DMA will be configured to transfer the data in the source buffer 'dmaSRCBuff' to the destination buffer 'dmaDESTBuff' using DMA_config() API. Configured values are read back using DMA_getConfig() API and are verified with the original values. DMA data transfer is triggered using DMA_start() API. DMA data transfer is aborted immediately using DMA_stop() API. After stopping the DMA data transfer data in the source and destination buffer will be compared. Data in the source and destination buffers should match till the point DMA is stopped by using the stop API and should mismatch after that point. Position of the buffer mismatch will be displayed in the CCS "stdout" window. This position will be different for each DMA channel. Same test procedure is repeated on all the 16 DMA channels.

DMA data length should be large enough and DMA_stop() API should be called immediately after calling the DMA_start() API for proper functionality of the test. DO NOT RUN THE TEST BY SINGLE STEPPING.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_DMA_StopAPIExample.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- DMA configuration values should be read back and verified successfully
- DMA transfer should be stopped successfully and source and destination data should mismatch on all the 16 DMA channels.

=============================================================================

## DMA EXAMPLE4 - PING-PONG MODE TEST

### TEST DESCRIPTION:

This test verifies operation of the CSL DMA module in ping-pong mode. Ping-Pong mode is a special mode of data transfer in which DMA generates a half way interrupt. When ping-pong mode is enabled DMA considers the source data buffer as two parts and generates an interrupt after transferring half of the data. First half of the buffer is Ping data buffer and second half of the buffer is Pong data buffer. These two buffers should be allocated in contiguous memory locations or one ping buffer of size equal to double the data transfer length should be allocated. Buffer being transferred by the DMA currently can be identified by reading 'Last Transfer Type' bit of the channel transfer control register. Ping-Pong mode can be utilized effectively in the interrupt mode of data transfer.

During the test DMA ping-pong functionality is verified by transferring the data between four buffers allocated in memory of C5515 DSP. There is one Ping set of data buffers and one Pong set of data buffers. DMA is configured for ping-pong mode and data transfer is started. Execution will wait for the ping and pong data transfer interrupts to occur. Successful completion of data transfer will copy Ping source buffer data into Ping destination buffer and Pong source buffer data into Pong destination buffer. Status of the Ping and Pong set transfer will be displayed in the CCS stdout window. Test is repeated for all the 16 DMA channels.

NOTE: DMA PING-PONG BUFFER MODE IS SUPPORTED ONLY ON CHIP 5515. THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5515 EVM)
- Open the project "CSL_DMA_PingPongExample.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Ping source and destination data should match on all the 16 DMA channels
- Pong source and destination data should match on all the 16 DMA channels