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csl_lcdc.h
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    00001 /*  ===========================================================================
    00002  *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
    00003  *
    00004  *   Use of this software is controlled by the terms and conditions found in
    00005  *   the license agreement under which this software has been supplied.
    00006  *  ===========================================================================
    00007  */
    00008
    00038 /* ============================================================================
    00039  * Revision History
    00040  * ================
    00041  * 05-Sept-2008 Added LCDC of CSL.
    00042  * 06-May-2009 Removed the Raster mode support for C5505 PG1.4
    00043  * 26-May-2009 Modified based on the review comments
    00044  * ============================================================================
    00045  */
    00046
    00047 #ifndef _CSL_LCD_H_
    00048 #define _CSL_LCD_H_
    00049
    00050 #ifdef __cplusplus
    00051 extern "C" {
    00052 #endif
    00053
    00054 #include <soc.h>
    00055 #include <tistdtypes.h>
    00056 #include <cslr_sysctrl.h>
    00057 #include <csl_types.h>
    00058 #include <csl_error.h>
    00059 #include <csl_general.h>
    00060
    00086 /*****************************************************************************\
    00087           LCDC global macro declarations
    00088 \*****************************************************************************/
    00089
    00093 #define CSL_LCDC_INSTANCE_0             (0x0)
    00094
    00095 #define CSL_LCDC_INSTANCE_INV           (0xFF)
    00096
    00097 #define CSL_LCD_ENABLE                  (Uint16)(0x1)
    00098
    00099 #define CSL_LCD_DISABLE                 (Uint16)(0x0)
    00100
    00101 #define CSL_LCD_ACTIVE                  (Uint16)(0x0)
    00102
    00103 #define CSL_LCD_RESET_CLOCK_CYCLE       (0x20)
    00104
    00105 #define CSL_LCD_SARAM_START_ADDR        (0x08000)
    00106
    00107 #define CSL_LCD_SARAM_END_ADDR          (0x27FFF)
    00108
    00109 #define CSL_LCD_SARAM_DMA_ADDR_OFFSET   (0x080000)
    00110
    00111 #define CSL_LCD_UINT16_MASK             (0xFFFF)
    00112
    00113 #define CSL_LCD_DMA_SHIFT               (0x01)
    00114
    00115 #define CSL_LCD_UINT16_NUMBER_BITS      (0x0010)
    00116
    00117 #define CSL_LCD_LCDLIDDCR_POLARITY_CONTROL_MASK  (0x00F8)
    00118
    00121 /*****************************************************************************\
    00122           LCDC global typedef declarations
    00123 \*****************************************************************************/
    00124
    00131 typedef enum {
    00132     CSL_LCDC_LIDD_CS0,
    00133     CSL_LCDC_LIDD_CS1
    00134 } CSL_LcdcChipSelect;
    00135
    00139 typedef enum {
    00140     CSL_LCDC_LIDD_NOT_USE_CS1,
    00141     CSL_LCDC_LIDD_USE_CS1
    00142 } CSL_LcdcCs1Status;
    00143
    00148 typedef enum {
    00150     CSL_LCDC_LIDD_SYNC_MPU68 = CSL_LCDC_LCDLIDDCR_LIDD_MODE_SEL_SYNC_MPU68,
    00152     CSL_LCDC_LIDD_ASYNC_MPU68 = CSL_LCDC_LCDLIDDCR_LIDD_MODE_SEL_ASYNC_MPU68,
    00154     CSL_LCDC_LIDD_SYNC_MPU80 = CSL_LCDC_LCDLIDDCR_LIDD_MODE_SEL_SYNC_MPU80,
    00156     CSL_LCDC_LIDD_ASYNC_MPU80 = CSL_LCDC_LCDLIDDCR_LIDD_MODE_SEL_ASYNC_MPU80,
    00158     CSL_LCDC_LIDD_ASYNC_HITACHI = CSL_LCDC_LCDLIDDCR_LIDD_MODE_SEL_HITACHI
    00159 } CSL_LcdcLiddMode;
    00160
    00164 typedef enum {
    00166     CSL_LCDC_LIDD_FDONE_DISABLE,
    00168     CSL_LCDC_LIDD_FDONE_ENABLE
    00169 } CSL_LcdcFdoneCtl;
    00170
    00174 typedef enum {
    00180     CSL_LCDC_LIDD_DMA_DISABLE,
    00184     CSL_LCDC_LIDD_DMA_ENABLE
    00185 } CSL_LcdcDmaCtl;
    00186
    00190 typedef enum {
    00192     CSL_LCDC_DMA_BURST1 = CSL_LCDC_LCDDMACR_BURST_SIZE_BSIZE1,
    00194     CSL_LCDC_DMA_BURST2 = CSL_LCDC_LCDDMACR_BURST_SIZE_BSIZE2,
    00196     CSL_LCDC_DMA_BURST4 = CSL_LCDC_LCDDMACR_BURST_SIZE_BSIZE4,
    00198     CSL_LCDC_DMA_BURST8 = CSL_LCDC_LCDDMACR_BURST_SIZE_BSIZE8,
    00200     CSL_LCDC_DMA_BURST16 = CSL_LCDC_LCDDMACR_BURST_SIZE_BSIZE16
    00201 } CSL_LcdcDmaBurst;
    00202
    00206 typedef enum {
    00208     CSL_LCDC_SUBPANEL_DISABLE = 0,
    00210     CSL_LCDC_SUBPANEL_ENABLE  = 1
    00211 } CSL_LcdcSubpanelCtl;
    00212
    00216 typedef enum {
    00219     CSL_LCDC_SUBPANPOS_LOW = 0,
    00222     CSL_LCDC_SUBPANPOS_HIGH  = 1
    00223 } CSL_LcdcSubpanPosCtl;
    00224
    00228 typedef enum {
    00231     CSL_LCDC_SYNCCTL_PIXCLK = 0,
    00234     CSL_LCDC_SYNCCTL_BIT24  = 1
    00235 } CSL_LcdcSyncClkCtl;
    00236
    00240 typedef enum {
    00243     CSL_LCDC_SYNCEDGECTL_FALL = 0,
    00246     CSL_LCDC_SYNCEDGECTL_RISE = 1
    00247 } CSL_LcdcSyncEdgeCtl;
    00248
    00252 typedef enum {
    00254     CSL_LCDC_EOFINT_DISABLE = 0,
    00256     CSL_LCDC_EOFINT_ENABLE = 1
    00257 } CSL_LcdcEofIntCtl;
    00258
    00262 typedef enum {
    00264     CSL_LCDC_ENDIANESS_LITTLE = 0,
    00266     CSL_LCDC_ENDIANESS_BIG    = 1
    00267 } CSL_LcdcEndianess;
    00268
    00272 typedef enum {
    00274     CSL_LCDC_FBMODE_SINGLE = 0,
    00277     CSL_LCDC_FBMODE_DOUBLE = 1
    00278 } CSL_LcdcFrameMode;
    00279
    00292 typedef struct {
    00294     Uint16  clkDiv;
    00296     CSL_LcdcFdoneCtl  fdoneIntEn;
    00300     CSL_LcdcChipSelect  dmaCs0Cs1;
    00302     CSL_LcdcDmaCtl  dmaEnable;
    00304     CSL_BitMask16 polControl;
    00306     CSL_LcdcLiddMode  modeSel;
    00307 } CSL_LcdcConfigLidd;
    00308
    00314 typedef struct {
    00316     Uint16    wSu;
    00318     Uint16    wStrobe;
    00320     Uint16    wHold;
    00322     Uint16    rSu;
    00324     Uint16    rStrobe;
    00326     Uint16    rHold;
    00328     Uint16    ta;
    00329 } CSL_LcdcLiddTiming;
    00330
    00336 typedef struct {
    00338     CSL_LcdcDmaBurst   burstSize;
    00340     CSL_LcdcEofIntCtl  eofIntEn;
    00342     CSL_LcdcEndianess  bigEndian;
    00344     CSL_LcdcFrameMode  frameMode;
    00347     Uint32  fb0Base;
    00350     Uint32  fb0Ceil;
    00353     Uint32  fb1Base;
    00356     Uint32  fb1Ceil;
    00357 } CSL_LcdcConfigDma;
    00358
    00363 typedef struct {
    00365     void                  *extendSetup;
    00367     CSL_LcdcConfigLidd    config;
    00369     CSL_LcdcLiddTiming    timingCs0;
    00371     CSL_LcdcCs1Status     useCs1;
    00373     CSL_LcdcLiddTiming    timingCs1;
    00374 } CSL_LcdcHwSetup;
    00375
    00385 typedef struct CSL_LcdcObj {
    00388     CSL_LcdcRegsOvly    regs;
    00391     CSL_InstNum         perNum;
    00392 } CSL_LcdcObj;
    00393
    00396 typedef CSL_LcdcObj*    CSL_LcdcHandle;
    00397
    00401 typedef struct {
    00404     CSL_LcdcRegsOvly regs;
    00405 } CSL_LcdcBaseAddress;
    00406
    00410 typedef struct {
    00415     CSL_BitMask16   flags;
    00416 } CSL_LcdcParam;
    00417
    00422 typedef struct {
    00427     Uint16  contextInfo;
    00428 } CSL_LcdcContext;
    00429
    00433 /******************************************************************************
    00434  * CSL LCDC function declarations
    00435  *****************************************************************************/
    00474 CSL_Status LCD_init(void);
    00475
    00523 CSL_LcdcHandle LCD_open (
    00524                    Uint16       instanceNum,
    00525                    CSL_LcdcObj  *pLcdcObj,
    00526                    CSL_Status   *status     );
    00527
    00608 CSL_Status LCD_setup (
    00609                CSL_LcdcHandle         hLcdc,
    00610                CSL_LcdcHwSetup*       setup  );
    00611
    00713 CSL_Status LCD_configDMA (
    00714                CSL_LcdcHandle         hLcdc,
    00715                CSL_LcdcConfigDma*     pconfigDma );
    00716
    00756 CSL_Status LCD_close(
    00757                CSL_LcdcHandle     hLcdc);
    00761 #ifdef __cplusplus
    00762 }
    00763 #endif
    00764 #endif /* _CSL_LCDC_H_ */
    00765