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Defines | Typedefs
I2C Symbols Defined
I2C

## Defines
#define | CSL_I2C0 (0)
| I2C Instance number.
#define | CSL_I2C_INT_EVTID (23)
#define | CSL_I2C_EVT_COUNT (7)
#define | CSL_I2C_RESET_COUNT_VAL (0x20)
#define | CSL_I2C_RESET_DELAY (500)
#define | CSL_I2C_MODULE_CLOCK_FREQ (12)
#define | CSL_I2C_CLK_MULT (1000)
#define | CSL_I2C_PSC0 (0)
#define | CSL_I2C_PSC1 (1)
#define | CSL_I2C_PSC_ADJUST_VAL (1)
#define | CSL_I2C_PSC0_DVAL (7)
#define | CSL_I2C_PSC1_DVAL (6)
#define | CSL_I2C_PSC2TOFF_DVAL (5)
#define | CSL_I2C_ERROR_BASE (CSL_EI2C_FIRST)
| I2C Driver Error codes.
#define | CSL_I2C_BUS_BUSY_ERR (CSL_I2C_ERROR_BASE - 1)
#define | CSL_I2C_ARBITRATION_LOSS_ERR (CSL_I2C_ERROR_BASE - 2)
#define | CSL_I2C_NACK_ERR (CSL_I2C_ERROR_BASE - 3)
#define | CSL_I2C_TRANSMIT_UNDERFLOW_ERR (CSL_I2C_ERROR_BASE - 4)
#define | CSL_I2C_RECEIVE_OVERFLOW_ERR (CSL_I2C_ERROR_BASE - 5)
#define | CSL_I2C_CANCEL_IO_ERROR (CSL_I2C_ERROR_BASE - 6)
#define | CSL_I2C_TIMEOUT_ERROR (CSL_I2C_ERROR_BASE - 7)
#define | CSL_I2C_READ (0x1)
| I2C Transaction flags.
#define | CSL_I2C_WRITE (0x2)
#define | CSL_I2C_ADDR_FORMAT_10_BIT (0x10)
#define | CSL_I2C_START (0x100)
#define | CSL_I2C_STOP (0x200)
#define | CSL_I2C_RESTART (0x400)
#define | CSL_I2C_START_BYTE (0x800)
#define | CSL_I2C_FREE_DATA_FORMAT (0x1000)
#define | CSL_I2C_REPEAT (0x2000)
#define | CSL_I2C_IGNORE_BUS_BUSY (0x20000)
#define | CSL_I2C_DEFAULT_STTSTP (CSL_I2C_START | CSL_I2C_STOP)
#define | CSL_I2C_MAX_TIMEOUT (0xFFFF)
#define | CSL_I2C_ICOAR_DEFVAL (0x2F)
#define | CSL_I2C_ICIMR_DEFVAL (0x0000)
#define | CSL_I2C_ICSAR_DEFVAL (0x50)
#define | CSL_I2C_ICPSC_DEFVAL (0x07)
#define | CSL_I2C_ICCLK_DEFVAL (0x026C)
#define | CSL_I2C_ICMDR_WRITE_DEFVAL (0x0E20)
#define | CSL_I2C_ICMDR_READ_DEFVAL (0x0C20)
#define | CSL_I2C_ICEMDR_DEFVAL (0x0000)
#define | CSL_I2C_ICSTR_RESET_VALUE (0xFFFF)
#define | CSL_I2C0_READREG(reg, val) (val = CSL_I2C_0_REGS->##reg)
#define | CSL_I2C0_WRITEREG(reg, val) (CSL_I2C_0_REGS->##reg = val)
#define | CSL_I2C_SETSTART() CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STT, SET);
#define | CSL_I2C_RESETSTART() CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STT, CLEAR);
#define | CSL_I2C_SETSTOP() CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STP, SET);
#define | CSL_I2C_RESETSTOP() CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STP, CLEAR);
## Typedefs
typedef void(* | CSL_I2C_EVENT_ISR )(void)

## Define Documentation

#define CSL_I2C0_READREG | ( |  | reg,
|  |  | val
| ) |  | (val = CSL_I2C_0_REGS->##reg)

Macro to read I2C register NOTE: Pass the name of the register for 'reg' field EX : Read I2C mode register Uint16 mdrVal;

CSL_I2C0_READREG(ICMDR, mdrVal);

#define CSL_I2C0_WRITEREG | ( |  | reg,
|  |  | val
| ) |  | (CSL_I2C_0_REGS->##reg = val)

Macro to write I2C register

#define CSL_I2C_ADDR_FORMAT_10_BIT (0x10)

If this flag is not set, default is 7 bit address

#define CSL_I2C_ARBITRATION_LOSS_ERR (CSL_I2C_ERROR_BASE - 2)

Returned when the I2C driver lost the bus arbitration

#define CSL_I2C_BUS_BUSY_ERR (CSL_I2C_ERROR_BASE - 1)

Returned when the I2C bus find that the bus is busy

Referenced by I2C_read(), and I2C_write().

#define CSL_I2C_CANCEL_IO_ERROR (CSL_I2C_ERROR_BASE - 6)

Returned in case of an Cancelling IO error

#define CSL_I2C_CLK_MULT (1000)

Clock Multiplier to convert the clock into Hz from KHz and MHz

Referenced by I2C_setup().

#define CSL_I2C_DEFAULT_STTSTP (CSL_I2C_START | CSL_I2C_STOP)

Default start stop flag

#define CSL_I2C_ERROR_BASE (CSL_EI2C_FIRST)

I2C Driver Error codes.

Error Code base

#define CSL_I2C_EVT_COUNT (7)

I2C interrupt event count

#define CSL_I2C_FREE_DATA_FORMAT (0x1000)

Free Data Format

#define CSL_I2C_ICCLK_DEFVAL (0x026C)

I2C Clock register defval (For 100MHz sysClk and 10KHz Bus frequency)

#define CSL_I2C_ICEMDR_DEFVAL (0x0000)

Default value of I2C Extended Mode register

#define CSL_I2C_ICIMR_DEFVAL (0x0000)

Default value of I2C Interrupt mask register

#define CSL_I2C_ICMDR_READ_DEFVAL (0x0C20)

Default value of I2C Mode register for read operation

#define CSL_I2C_ICMDR_WRITE_DEFVAL (0x0E20)

Default value of I2C Mode register for write operation

#define CSL_I2C_ICOAR_DEFVAL (0x2F)

Default value of I2C Own address register

#define CSL_I2C_ICPSC_DEFVAL (0x07)

I2C Prescaler register defval(For 100MHz sysClk and 10KHz Bus frequency)

#define CSL_I2C_ICSAR_DEFVAL (0x50)

Default value of I2C Slave address register (EEPROM address)

#define CSL_I2C_ICSTR_RESET_VALUE (0xFFFF)

I2C status register reset value

Referenced by I2C_config().

#define CSL_I2C_IGNORE_BUS_BUSY (0x20000)

Ignore Bus Busy condition

#define CSL_I2C_INT_EVTID (23)

I2C event Id for interrupt operation

#define CSL_I2C_MAX_TIMEOUT (0xFFFF)

I2C timeout value

#define CSL_I2C_MODULE_CLOCK_FREQ (12)

I2C module clock frequency - (This should be between 7MHz and 12MHz)

Referenced by I2C_setup().

#define CSL_I2C_NACK_ERR (CSL_I2C_ERROR_BASE - 3)

Returned when the I2C slave did not generate an acknowledge

Referenced by I2C_write().

#define CSL_I2C_PSC0 (0)

I2C Prescaler value is zero

Referenced by I2C_setup().

#define CSL_I2C_PSC0_DVAL (7)

I2C d value for the prescaler value zero

Referenced by I2C_setup().

#define CSL_I2C_PSC1 (1)

I2C Prescaler value is one

Referenced by I2C_setup().

#define CSL_I2C_PSC1_DVAL (6)

I2C d value for the prescaler value one

Referenced by I2C_setup().

#define CSL_I2C_PSC2TOFF_DVAL (5)

I2C d value for the prescaler value 2h to FFh

Referenced by I2C_setup().

#define CSL_I2C_PSC_ADJUST_VAL (1)

Adjustment for the Prescaler value

Referenced by I2C_setup().

#define CSL_I2C_READ (0x1)

I2C Transaction flags.

Read from I2C bus (device)

#define CSL_I2C_RECEIVE_OVERFLOW_ERR (CSL_I2C_ERROR_BASE - 5)

Returned in case of an rcv overflow error

Referenced by I2C_read().

#define CSL_I2C_REPEAT (0x2000)

Repeat mode as per TI I2C specs

#define CSL_I2C_RESET_COUNT_VAL (0x20)

I2C device reset count value

Referenced by I2C_init().

#define CSL_I2C_RESET_DELAY (500)

I2C reset delay value

Referenced by I2C_init().

#define CSL_I2C_RESETSTART | ( |  | ) | CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STT, CLEAR);

Macro to Reset I2C start bit

#define CSL_I2C_RESETSTOP | ( |  | ) | CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STP, CLEAR);

Macro to Reset I2C stop bit

#define CSL_I2C_RESTART (0x400)

Re-Start is generated by Master

#define CSL_I2C_SETSTART | ( |  | ) | CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STT, SET);

Macro to Set I2C start bit

#define CSL_I2C_SETSTOP | ( |  | ) | CSL_FINST(CSL_I2C_0_REGS->ICMDR, I2C_ICMDR_STP, SET);

Macro to Set I2C stop bit

#define CSL_I2C_START (0x100)

Generate Start - valid in master mode only

Referenced by I2C_read(), and I2C_write().

#define CSL_I2C_START_BYTE (0x800)

Start Byte as per Phillips I2C specs

#define CSL_I2C_STOP (0x200)

Generate Stop - valid in master mode only

Referenced by I2C_read(), and I2C_write().

#define CSL_I2C_TIMEOUT_ERROR (CSL_I2C_ERROR_BASE - 7)

Returned in case of timeout error

Referenced by I2C_read(), and I2C_write().

#define CSL_I2C_TRANSMIT_UNDERFLOW_ERR (CSL_I2C_ERROR_BASE - 4)

Returned in case of an transmit underflow error

#define CSL_I2C_WRITE (0x2)

Write to I2C bus (device)

## Typedef Documentation

typedef void(* CSL_I2C_EVENT_ISR)(void)

I2C event handler