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Defines
I2S Symbols Defined
I2S

## Defines
#define | CSL_I2S_SCRL_ENABLE_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_ENABLE_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_MONO_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_MONO_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_LOOPBACK_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_LOOPBACK_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_FSPOL_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_FSPOL_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_CLOCKPOL_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_CLOCKPOL_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_DATADELAY_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_DATADELAY_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_PACK_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_PACK_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_SIGNEXT_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_SIGNEXT_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_WORDLENGTH_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_WORDLENGTH_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_MODE_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_MODE_ENABLE (Uint16)1
#define | CSL_I2S_SCRL_FORMAT_DISABLE (Uint16)0
#define | CSL_I2S_SCRL_FORMAT_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_XMIT0_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_XMIT0_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_XMIT1_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_XMIT1_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_RCV0_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_RCV0_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_RCV1_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_RCV1_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_FERR_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_FERR_ENABLE (Uint16)1
#define | CSL_I2S_ICMRL_O_U_DISABLE (Uint16)0
#define | CSL_I2S_ICMRL_O_U_ENABLE (Uint16)1
#define | CSL_I2S_LATENCY_2 (2)
#define | CSL_I2S_LATENCY_3 (3)
#define | CSL_I2S_LATENCY_5 (5)
#define | CSL_I2S_LATENCY_6 (6)

## Define Documentation

#define CSL_I2S_ICMRL_FERR_DISABLE (Uint16)0

Frame-sync error reporting disable

#define CSL_I2S_ICMRL_FERR_ENABLE (Uint16)1

Frame-sync error reporting Enable

#define CSL_I2S_ICMRL_O_U_DISABLE (Uint16)0

Overrun or under-run error reporting disable

#define CSL_I2S_ICMRL_O_U_ENABLE (Uint16)1

Overrun or under-run error reporting Enable

#define CSL_I2S_ICMRL_RCV0_DISABLE (Uint16)0

Left channel data receive request interrupt disable

#define CSL_I2S_ICMRL_RCV0_ENABLE (Uint16)1

Left channel data receive request interrupt Enable

#define CSL_I2S_ICMRL_RCV1_DISABLE (Uint16)0

Right channel data receive request interrupt disable

#define CSL_I2S_ICMRL_RCV1_ENABLE (Uint16)1

Right channel data receive request interrupt disable

#define CSL_I2S_ICMRL_XMIT0_DISABLE (Uint16)0

Left channel data transmit request interrupt disable

#define CSL_I2S_ICMRL_XMIT0_ENABLE (Uint16)1

Left channel data transmit request interrupt Enable

#define CSL_I2S_ICMRL_XMIT1_DISABLE (Uint16)0

Right channel data transmit request interrupt disable

#define CSL_I2S_ICMRL_XMIT1_ENABLE (Uint16)1

Right channel data transmit request interrupt Enable

#define CSL_I2S_LATENCY_2 (2)

Macros to insert a latency of 2 frames

Referenced by I2S_read().

#define CSL_I2S_LATENCY_3 (3)

Macros to insert a latency of 3 frames

Referenced by I2S_read().

#define CSL_I2S_LATENCY_5 (5)

Macros to insert a latency of 5 frames

Referenced by I2S_read().

#define CSL_I2S_LATENCY_6 (6)

Macros to insert a latency of 6 frames

Referenced by I2S_read().

#define CSL_I2S_SCRL_CLOCKPOL_DISABLE (Uint16)0

serializer bit-clock polarity enable

#define CSL_I2S_SCRL_CLOCKPOL_ENABLE (Uint16)1

serializer bit-clock polarity disable

#define CSL_I2S_SCRL_DATADELAY_DISABLE (Uint16)0

Serializer receive/transmit data delay disable

#define CSL_I2S_SCRL_DATADELAY_ENABLE (Uint16)1

Serializer receive/transmit data delay enable

#define CSL_I2S_SCRL_ENABLE_DISABLE (Uint16)0

Serializer transmission or reception bit Disable

#define CSL_I2S_SCRL_ENABLE_ENABLE (Uint16)1

serializer transmission or reception bit Enable

#define CSL_I2S_SCRL_FORMAT_DISABLE (Uint16)0

I2S/left-justified format

#define CSL_I2S_SCRL_FORMAT_ENABLE (Uint16)1

DSP format

#define CSL_I2S_SCRL_FSPOL_DISABLE (Uint16)0

Frame-sync is pulsed high

#define CSL_I2S_SCRL_FSPOL_ENABLE (Uint16)1

Frame-sync is pulsed low

#define CSL_I2S_SCRL_LOOPBACK_DISABLE (Uint16)0

Loopback disable

#define CSL_I2S_SCRL_LOOPBACK_ENABLE (Uint16)1

Loopback enable

#define CSL_I2S_SCRL_MODE_DISABLE (Uint16)0

Serializer in master or slave mode

#define CSL_I2S_SCRL_MODE_ENABLE (Uint16)1

Serializer in master or slave mode

#define CSL_I2S_SCRL_MONO_DISABLE (Uint16)0

Stereo Mode

#define CSL_I2S_SCRL_MONO_ENABLE (Uint16)1

Mono Mode

#define CSL_I2S_SCRL_PACK_DISABLE (Uint16)0

Disabling data packing

#define CSL_I2S_SCRL_PACK_ENABLE (Uint16)1

Enabling data packing

#define CSL_I2S_SCRL_SIGNEXT_DISABLE (Uint16)0

Disable sign extension of words

#define CSL_I2S_SCRL_SIGNEXT_ENABLE (Uint16)1

Enable sign extension of words

#define CSL_I2S_SCRL_WORDLENGTH_DISABLE (Uint16)0

disable sign extension of words

#define CSL_I2S_SCRL_WORDLENGTH_ENABLE (Uint16)1

Enable sign extension of words