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csl_dma.h
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    00001 /*  ===========================================================================
    00002  *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
    00003  *
    00004  *   Use of this software is controlled by the terms and conditions found in
    00005  *   the license agreement under which this software has been supplied.
    00006  *  ===========================================================================
    00007  */
    00008
    00016 /* ============================================================================
    00017  * Revision History
    00018  * ================
    00019  * 25-Aug-2008 Added DMA for CSL.
    00020  * 27-Aug-2008 Updated for Doxygen.
    00021  * 28-Aug-2008 Added Return Types for Error checking for API's parameter.
    00022  * 01-Oct-2008 Added additional parameter CSL_DMA_ChannelObj pointer to the
    00023  *             DMA_open() API.
    00024  * 08-May-2009 Added DMA_swapWords API for C5505 PG1.4
    00025  * 26-May-2009 Modified as per the review comments
    00026  * 17-Dec-2009 Added Support for Ping-Pong mode for chip C5515
    00027  * 11-Jan-2010 Modified as per the review comments
    00028  * ============================================================================
    00029  */
    00030
    00047 #ifndef _CSL_DMA_H_
    00048 #define _CSL_DMA_H_
    00049
    00050 #ifdef __cplusplus
    00051 extern "C" {
    00052 #endif
    00053
    00054 #include <cslr_dma.h>
    00055 #include <cslr_sysctrl.h>
    00056 #include <tistdtypes.h>
    00057 #include <csl_types.h>
    00058 #include <csl_error.h>
    00059 #include <soc.h>
    00060 #include <csl_general.h>
    00061
    00087 /*****************************************************************************\
    00088           DMA global macro declarations
    00089 \*****************************************************************************/
    00090
    00094 #define CSL_DMA_MIN_TX_SIZE                 (4)
    00095
    00096 #define CSL_DMA_CHAN_MAX                    (16)
    00097
    00098 #define CSL_DMA_CHAN_COUNT                  (4)
    00099
    00100 #define CSL_DMA_CHANNEL_BUSY                (1)
    00101
    00102 #define CSL_DMA_CHANNEL_FREE                (0)
    00103
    00104 #define CSL_DMA_CHANNEL_ENABLE                (Uint16)1
    00105
    00106 #define CSL_DMA_CHANNEL_DISABLE                (Uint16)0
    00107
    00108 #define CSL_DMA_DMATCR2_DMASTART_SYNC_MASK  (0x8004)
    00109
    00110 #define CSL_DMA_UINT16_MASK                 (0xFFFF)
    00111
    00112 #define CSL_DMA_UINT16_NUMBER_BITS          (0x0010)
    00113
    00114 #define CSL_DMA_RESET_CLOCK_CYCLE           (0x20)
    00115
    00116 #define CSL_DMA_ADDR_MODE_FIXED             (0x02)
    00117
    00118 #define CSL_DMA_ADDR_MODE_INCREMENT         (0x00)
    00119
    00120 #define CSL_DMA_ADDR_SHIFT                  (0x01)
    00121
    00122 #define CSL_DMA_DARAM_START_ADDR            (0x00060)
    00123
    00124 #define CSL_DMA_DARAM_END_ADDR              (0x07FFF)
    00125
    00126 #define CSL_DMA_SARAM_START_ADDR            (0x08000)
    00127
    00128 #define CSL_DMA_SARAM_END_ADDR              (0x27FFF)
    00129
    00130 #define CSL_DMA_DARAM_ADDR_OFFSET           (0x010000)
    00131
    00132 #define CSL_DMA_SARAM_ADDR_OFFSET            (0x080000)
    00133
    00134 #define CSL_DMA_16BIT_MASK                  (0xFFFFu)
    00135
    00136 #define CSL_DMA_16BIT_SHIFT                 (16u)
    00137
    00140 /**************************************************************************\
    00141 * DMA global typedef declarations                                         *
    00142 \**************************************************************************/
    00143
    00152 typedef enum
    00153 {
    00154     CSL_DMA_ENGINE0 = 0,
    00155     CSL_DMA_ENGINE1,
    00156     CSL_DMA_ENGINE2,
    00157     CSL_DMA_ENGINE3,
    00158     CSL_DMA_ENGINEINV
    00159 } CSL_DMAEngineId;
    00160
    00166 typedef enum
    00167 {
    00168     CSL_DMA_CHAN0 = 0,
    00169     CSL_DMA_CHAN1,
    00170     CSL_DMA_CHAN2,
    00171     CSL_DMA_CHAN3,
    00172     CSL_DMA_CHAN4,
    00173     CSL_DMA_CHAN5,
    00174     CSL_DMA_CHAN6,
    00175     CSL_DMA_CHAN7,
    00176     CSL_DMA_CHAN8,
    00177     CSL_DMA_CHAN9,
    00178     CSL_DMA_CHAN10,
    00179     CSL_DMA_CHAN11,
    00180     CSL_DMA_CHAN12,
    00181     CSL_DMA_CHAN13,
    00182     CSL_DMA_CHAN14,
    00183     CSL_DMA_CHAN15,
    00184     CSL_DMA_CHAN_INV
    00185 } CSL_DMAChanNum;
    00186
    00193 typedef enum
    00194 {
    00195     CSL_DMA_AUTORELOAD_DISABLE,
    00196     CSL_DMA_AUTORELOAD_ENABLE
    00197 } CSL_DMAAutoReloadMode;
    00198
    00205 typedef enum
    00206 {
    00207     CSL_DMA_TXBURST_1WORD,
    00208     CSL_DMA_TXBURST_2WORD,
    00209     CSL_DMA_TXBURST_4WORD,
    00210     CSL_DMA_TXBURST_8WORD,
    00211     CSL_DMA_TXBURST_16WORD
    00212 } CSL_DMATxBurstLen;
    00213
    00220 typedef enum
    00221 {
    00222     CSL_DMA_TRANSFER_COMPLETE,
    00223     CSL_DMA_TRANSFER_ERROR
    00224 } CSL_DMATransferStatus;
    00225
    00231 typedef enum
    00232 {
    00233     CSL_DMA_EVT_NONE = 0,
    00234     CSL_DMA_EVT_I2S0_TX = 1,
    00235     CSL_DMA_EVT_I2S0_RX = 2,
    00236     CSL_DMA_EVT_I2S1_TX = 1,
    00237     CSL_DMA_EVT_I2S1_RX = 2,
    00238     CSL_DMA_EVT_I2S2_TX = 1,
    00239     CSL_DMA_EVT_I2S2_RX = 2,
    00240     CSL_DMA_EVT_I2S3_TX = 4,
    00241     CSL_DMA_EVT_I2S3_RX = 5,
    00242     CSL_DMA_EVT_MMC_SD0_TX = 5,
    00243     CSL_DMA_EVT_MMC_SD0_RX = 6,
    00244     CSL_DMA_EVT_MMC_SD1_TX = 7,
    00245     CSL_DMA_EVT_MMC_SD1_RX = 8,
    00246     CSL_DMA_EVT_TIMER0 = 12,
    00247     CSL_DMA_EVT_TIMER1 = 13,
    00248     CSL_DMA_EVT_TIMER2 = 14,
    00249     CSL_DMA_EVT_UART_TX = 5,
    00250     CSL_DMA_EVT_UART_RX = 6,
    00251     CSL_DMA_EVT_I2C_TX = 1,
    00252     CSL_DMA_EVT_I2C_RX = 2,
    00253     CSL_DMA_EVT_SAR_AD = 3,
    00254     CSL_DMA_EVT_INVALID
    00255 } CSL_DMAEvtType;
    00256
    00263 typedef enum
    00264 {
    00265     CSL_DMA_READ,
    00266     CSL_DMA_WRITE
    00267 } CSL_DMAChanDir;
    00268
    00275 typedef enum
    00276 {
    00277     CSL_DMA_TRANSFER_IO_MEMORY,
    00278     CSL_DMA_TRANSFER_MEMORY
    00279 } CSL_DMATransferType;
    00280
    00287 typedef enum
    00288 {
    00289     CSL_DMA_SOFTWARE_TRIGGER,
    00290     CSL_DMA_EVENT_TRIGGER
    00291 } CSL_DMATriggerType;
    00292
    00299 typedef enum
    00300 {
    00301     CSL_DMA_INTERRUPT_DISABLE,
    00302     CSL_DMA_INTERRUPT_ENABLE
    00303 } CSL_DMAInterruptState;
    00304
    00305 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    00306
    00313 typedef enum
    00314 {
    00315     CSL_DMA_PING_PONG_DISABLE,
    00316     CSL_DMA_PING_PONG_ENABLE
    00317 } CSL_DMAPingPongMode;
    00318
    00319 #endif
    00320
    00333 typedef struct
    00334 {
    00335     CSL_DmaRegsOvly        dmaRegs;
    00336     CSL_DMAChanNum         chanNum;
    00337     CSL_DMAEngineId        dmaInstNum;
    00338     Bool                   isChanFree;
    00339     CSL_DMAChanDir         chanDir;
    00340     CSL_DMATriggerType     trigger;
    00341     CSL_DMATransferType    trfType;
    00342     CSL_DMAInterruptState  dmaInt;
    00344 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    00345     Bool                   pingPongEnabled;
    00346 #endif
    00347
    00351 } CSL_DMA_ChannelObj;
    00352
    00357 typedef CSL_DMA_ChannelObj     *CSL_DMA_Handle;
    00358
    00365 typedef struct
    00366 {
    00367 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    00368     CSL_DMAPingPongMode       pingPongMode;
    00369 #endif
    00370
    00371     CSL_DMAAutoReloadMode     autoMode;
    00372     CSL_DMATxBurstLen         burstLen;
    00373     CSL_DMATriggerType        trigger;
    00374     CSL_DMAEvtType            dmaEvt;
    00375     CSL_DMAInterruptState     dmaInt;
    00376     CSL_DMAChanDir            chanDir;
    00377     CSL_DMATransferType       trfType;
    00378     Uint16                    dataLen;
    00380     Uint32                    srcAddr;
    00381     Uint32                    destAddr;
    00382 } CSL_DMA_Config;
    00383
    00388 /******************************************************************************
    00389  * DMA function declarations
    00390  *****************************************************************************/
    00391
    00431 CSL_Status DMA_init (void);
    00432
    00480 CSL_DMA_Handle DMA_open (
    00481     CSL_DMAChanNum       chanNum,
    00482     CSL_DMA_ChannelObj   *pDmaChanObj,
    00483     CSL_Status           *status
    00484 );
    00485
    00527 CSL_Status DMA_close (
    00528     CSL_DMA_Handle         hDMA
    00529 );
    00530
    00600 CSL_Status DMA_config (
    00601     CSL_DMA_Handle            hDMA,
    00602     CSL_DMA_Config            *pConfig
    00603 );
    00604
    00647 CSL_Status DMA_getConfig (
    00648     CSL_DMA_Handle            hDMA,
    00649     CSL_DMA_Config            *pConfig
    00650 );
    00651
    00717 CSL_Status DMA_start (
    00721     CSL_DMA_Handle            hDMA
    00722 );
    00723
    00794 CSL_Status DMA_stop (
    00798     CSL_DMA_Handle            hDMA
    00799 );
    00800
    00839 CSL_Status DMA_reset (
    00840     CSL_DMA_Handle         hDMA
    00841 );
    00842
    00879 CSL_Status DMA_swapWords (Uint16    *dataBuffer,
    00880                           Uint32    dataLength);
    00881
    00882 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    00883
    00927 Bool DMA_getLastTransferType (CSL_DMA_Handle    hDMA,
    00928                               CSL_Status        *status);
    00929 #endif
    00930
    00933 /******************************************************************************
    00934  * CSL DMA Inline function
    00935  *****************************************************************************/
    01007 static inline
    01008 Int DMA_getStatus (
    01012     CSL_DMA_Handle            hDMA
    01013 )
    01014 {
    01015     Int       status;
    01016     Uint16    chanNum;
    01017
    01018     if(hDMA != NULL)
    01019     {
    01020         chanNum = hDMA->chanNum;
    01021
    01022         while(chanNum >= CSL_DMA_PER_CNT)
    01023         {
    01024             chanNum = chanNum - CSL_DMA_PER_CNT;
    01025         }
    01026
    01027         switch((CSL_DMAChanNum)chanNum)
    01028         {
    01029             case CSL_DMA_CHAN0:
    01030                 status = CSL_FEXT(hDMA->dmaRegs->DMACH0TCR2, DMA_DMACH0TCR2_EN);
    01031                 break;
    01032             case CSL_DMA_CHAN1:
    01033                 status = CSL_FEXT(hDMA->dmaRegs->DMACH1TCR2, DMA_DMACH1TCR2_EN);
    01034                 break;
    01035             case CSL_DMA_CHAN2:
    01036                 status = CSL_FEXT(hDMA->dmaRegs->DMACH2TCR2, DMA_DMACH2TCR2_EN);
    01037                 break;
    01038             case CSL_DMA_CHAN3:
    01039                 status = CSL_FEXT(hDMA->dmaRegs->DMACH3TCR2, DMA_DMACH3TCR2_EN);
    01040                 break;
    01041         }
    01042     }
    01043     else
    01044     {
    01045         status = CSL_ESYS_BADHANDLE;
    01046     }
    01047
    01048     return status;
    01049 }
    01053 #ifdef __cplusplus
    01054 }
    01055 #endif
    01056
    01057 #endif /* _CSL_DMA_H_ */
    01058