C55XX CSL EXAMPLE

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I2S EXAMPLE DOCUMENTATION

## I2S EXAMPLE1 - POLL MODE TEST

### TEST DESCRIPTION:

This test verifies the operation of CSL I2S module in polled mode. I2S module on C5505/C5515 DSP is used to exchange the audio data between the audio codec and DSP.

Testing of the I2S with the audio codec is not possible as codec is not part of the CSL package. This test verifies the I2S operation in loopback mode. In loopback mode of operation data written to the I2S data transmit registers will be transmitted to the I2S data receive registers. I2S is configured to master mode, stereo, 16bit data length and to loop back mode. I2S data transfer is enabled and the data is transferred to the I2S using I2S_write() API. After successful completion of I2S write data is read from the I2S using I2S_read() API. I2S write and read buffers are compared for the data verification.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_I2S_PollExample_out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful.

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## I2S EXAMPLE2 - DMA MODE TEST

### TEST DESCRIPTION:

This test verifies the operation of CSL I2S module in DMA mode. I2S module on C5505/C5515 DSP is used to exchange the audio data between the audio codec and DSP.

Testing of the I2S with the audio codec is not possible as codec is not part of the CSL package. This test verifies the I2S operation in loopback mode. In loopback mode of operation data written to the I2S data transmit registers will be transmitted to the I2S data receive registers. CSL DMA module should be configured for the I2S Tx and Rx operations. DMA module is used to transfer the data between CPU memory and I2S data registers. I2S is configured to master mode, stereo, 16bit data length and to loop back mode. Due to word swap behavior of the DMA while transferring the data to/from I2S, I2S write data buffer should be word swapped before transferring it to the I2S registers. In case of I2S no word swap is required on the data received due internal word swap by the I2S in loopback mode. I2S data transfer is enabled and DMA is started using DMA_start() API. DMA writes the data to the I2s Tx registers. After successful completion of write operation DMA is configured for Rx operation and again started to read the data from I2S Rx registers. I2S write and read buffers are compared for the data verification.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_I2S_DMAExampale_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful.

============================================================================

## I2S EXAMPLE3 - INTERRUPT MODE TEST

### TEST DESCRIPTION:

This test verifies the operation of CSL I2S module in interrupt mode. I2S module on C5505/C5515 DSP is used to exchange the audio data between the audio codec and DSP.

Testing of the I2S with the audio codec is not possible as codec is not part of the CSL package. This test verifies the I2S operation in loopback mode. In loopback mode of operation data written to the I2S data transmit registers will be transmitted to the I2S data receive registers. CSL INTC module should be configured and I2S ISR should be registered before starting the data transfer. Separate ISRs are registered for I2S Tx and Rx. Interrupts are used to check the Tx/Rx status of the I2S. I2S is configured to master mode,stereo, 16bit data length and to loop back mode. When the I2S data transfer is enabled I2S starts generating the Tx interrupts. Data is written to the I2S Tx registers in the ISR 'i2s_txIsr'. As the I2S is configured in loopback mode when the data is written to Tx register it will be transmitted to Rx register and Rx interrupt will be generated. Data will be read from the I2S Rx registers in the ISR 'i2s_rxIsr'.I2S write and read buffers are compared for the data verification.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_I2S_INTCExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful.