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Defines
DMA Symbols Defined
DMA

## Defines
#define | CSL_DMA_MIN_TX_SIZE (4)
#define | CSL_DMA_CHAN_MAX (16)
#define | CSL_DMA_CHAN_COUNT (4)
#define | CSL_DMA_CHANNEL_BUSY (1)
#define | CSL_DMA_CHANNEL_FREE (0)
#define | CSL_DMA_CHANNEL_ENABLE (Uint16)1
#define | CSL_DMA_CHANNEL_DISABLE (Uint16)0
#define | CSL_DMA_DMATCR2_DMASTART_SYNC_MASK (0x8004)
#define | CSL_DMA_UINT16_MASK (0xFFFF)
#define | CSL_DMA_UINT16_NUMBER_BITS (0x0010)
#define | CSL_DMA_RESET_CLOCK_CYCLE (0x20)
#define | CSL_DMA_ADDR_MODE_FIXED (0x02)
#define | CSL_DMA_ADDR_MODE_INCREMENT (0x00)
#define | CSL_DMA_ADDR_SHIFT (0x01)
#define | CSL_DMA_DARAM_START_ADDR (0x00060)
#define | CSL_DMA_DARAM_END_ADDR (0x07FFF)
#define | CSL_DMA_SARAM_START_ADDR (0x08000)
#define | CSL_DMA_SARAM_END_ADDR (0x27FFF)
#define | CSL_DMA_DARAM_ADDR_OFFSET (0x010000)
#define | CSL_DMA_SARAM_ADDR_OFFSET (0x080000)
#define | CSL_DMA_16BIT_MASK (0xFFFFu)
#define | CSL_DMA_16BIT_SHIFT (16u)

## Define Documentation

#define CSL_DMA_16BIT_MASK (0xFFFFu)

Macro to mask 16 bits in DMA buffer

#define CSL_DMA_16BIT_SHIFT (16u)

Maro to shift 16 bits in DMA buffer

#define CSL_DMA_ADDR_MODE_FIXED (0x02)

Value for fixed addr mode

#define CSL_DMA_ADDR_MODE_INCREMENT (0x00)

Value for incr. addr mode

#define CSL_DMA_ADDR_SHIFT (0x01)

shift value to change cpu addr for DMA

#define CSL_DMA_CHAN_COUNT (4)

Number of channels on each DMA Engine

#define CSL_DMA_CHAN_MAX (16)

Total no of channels for all DMA Engines

#define CSL_DMA_CHANNEL_BUSY (1)

hash define value for channel busy status

Referenced by DMA_open().

#define CSL_DMA_CHANNEL_DISABLE (Uint16)0

hash define value for channel disable bit

Referenced by DMA_stop().

#define CSL_DMA_CHANNEL_ENABLE (Uint16)1

hash define value for channel enable bit

Referenced by DMA_start().

#define CSL_DMA_CHANNEL_FREE (0)

hash define value for channel free status

Referenced by DMA_close().

#define CSL_DMA_DARAM_ADDR_OFFSET (0x010000)

DARAM starting address seen by DMA

#define CSL_DMA_DARAM_END_ADDR (0x07FFF)

DARAM ending address

#define CSL_DMA_DARAM_START_ADDR (0x00060)

DARAM starting address

#define CSL_DMA_DMATCR2_DMASTART_SYNC_MASK (0x8004)

hash define value for dma start and sync bit mask value

Referenced by DMA_config(), DMA_start(), and DMA_stop().

#define CSL_DMA_MIN_TX_SIZE (4)

Minimum Number of Bytes transfered by DMA

#define CSL_DMA_RESET_CLOCK_CYCLE (0x20)

DMA reset clock cycle count

Referenced by DMA_init().

#define CSL_DMA_SARAM_ADDR_OFFSET (0x080000)

SARAM starting address seen by DMA

#define CSL_DMA_SARAM_END_ADDR (0x27FFF)

SARAM ending address

#define CSL_DMA_SARAM_START_ADDR (0x08000)

SARAM starting address

#define CSL_DMA_UINT16_MASK (0xFFFF)

mask value for 16 bit variable

#define CSL_DMA_UINT16_NUMBER_BITS (0x0010)

no of bits in a Uint16 datatype variable