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soc.h
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    00001 /*  ============================================================================
    00002  *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
    00003  *
    00004  *   Use of this software is controlled by the terms and conditions found in the
    00005  *   license agreement under which this software has been supplied.
    00006  *  ============================================================================
    00007  */
    00008
    00016 /* ============================================================================
    00017  * Revision History
    00018  * ================
    00019  * 11-Aug-2008 Created
    00020  * 29 -Sept -2008 Added cslr_gpio.h header file ,
    00021  *                GPIO Overlay structure and Base Address
    00022  * 15 -Oct -2008 Added cslr_cpu.h header file ,
    00023  *                CPU Overlay structure and Base Address
    00024  * ============================================================================
    00025  */
    00026
    00027 #ifndef _SOC_H
    00028 #define _SOC_H
    00029
    00030 #include <cslr.h>
    00031 #include <tistdtypes.h>
    00032 #include <cslr_sysctrl.h>
    00033 #include <cslr_cpu.h>
    00034
    00035 /*****************************************************************************\
    00036 * Include files for all the modules in the device
    00037 \*****************************************************************************/
    00038
    00039 #include "cslr_i2c.h"
    00040 #include "cslr_i2s.h"
    00041 #include "cslr_emif.h"
    00042 #include "cslr_uart.h"
    00043 #include "cslr_spi.h"
    00044 #include "cslr_mmcsd.h"
    00045 #include "cslr_lcdc.h"
    00046 #include "cslr_rtc.h"
    00047 #include "cslr_dma.h"
    00048 #include "cslr_sar.h"
    00049 #include "cslr_usb.h"
    00050 #include "cslr_gpio.h"
    00051 #include "cslr_tim.h"
    00052 #include "cslr_wdt.h"
    00053 #include "csl_general.h"
    00054
    00055
    00056
    00057 /*****************************************************************************\
    00058 * Peripheral Instance counts
    00059 \*****************************************************************************/
    00060 #define CSL_DMA_PER_CNT     4
    00061 #define CSL_EMIF_PER_CNT    1
    00062 #define CSL_I2C_PER_CNT     1
    00063 #define CSL_I2S_PER_CNT     4
    00064 #define CSL_LCDC_PER_CNT    1
    00065 #define CSL_MMCSD_PER_CNT   2
    00066 #define CSL_PLL_PER_CNT     1
    00067 #define CSL_RTC_PER_CNT     1
    00068 #define CSL_SAR_PER_CNT     1
    00069 #define CSL_SPI_PER_CNT     1
    00070 #define CSL_UART_PER_CNT    1
    00071 #define CSL_USB_PER_CNT     1
    00072 #define CSL_TIM_PER_CNT     3
    00073 #define CSL_WDT_PER_CNT     1
    00074
    00075 /*****************************************************************************\
    00076 * Peripheral Overlay Structures
    00077 \*****************************************************************************/
    00078 typedef volatile ioport CSL_UsbRegs              * CSL_UsbRegsOvly;
    00079 typedef volatile ioport CSL_I2cRegs              * CSL_I2cRegsOvly;
    00080 typedef volatile ioport CSL_I2sRegs              * CSL_I2sRegsOvly;
    00081 typedef volatile ioport CSL_EmifRegs             * CSL_EmifRegsOvly;
    00082 typedef volatile ioport CSL_UartRegs             * CSL_UartRegsOvly;
    00083 typedef volatile ioport CSL_SpiRegs              * CSL_SpiRegsOvly;
    00084 typedef volatile ioport CSL_MmcsdRegs            * CSL_MmcsdRegsOvly;
    00085 typedef volatile ioport CSL_LcdcRegs             * CSL_LcdcRegsOvly;
    00086 typedef volatile ioport CSL_RtcRegs              * CSL_RtcRegsOvly;
    00087 typedef volatile ioport CSL_AnactrlRegs          * CSL_SarRegsOvly;
    00088 typedef volatile ioport CSL_GpioRegs             * CSL_GpioRegsOvly;
    00089 typedef volatile ioport CSL_SysRegs              * CSL_SysRegsOvly;
    00090 typedef volatile ioport CSL_DmaRegs              * CSL_DmaRegsOvly;
    00091 typedef volatile CSL_CpuRegs                     * CSL_CpuRegsOvly;
    00092 typedef volatile ioport CSL_TimRegs              * CSL_TimRegsOvly;
    00093 typedef volatile ioport CSL_WdtRegs              * CSL_WdtRegsOvly;
    00094
    00095 /*****************************************************************************\
    00096 * Peripheral Base Address
    00097 \*****************************************************************************/
    00098 #define CSL_USB_REGS                    ((CSL_UsbRegsOvly)  0x8000)
    00099 #define CSL_SAR_REGS                    ((CSL_SarRegsOvly)  0x7000)
    00100 #define CSL_EMIF_REGS                   ((CSL_EmifRegsOvly) 0x1000)
    00101 #define CSL_I2C_0_REGS                  ((CSL_I2cRegsOvly)  0x1A00)
    00102 #define CSL_I2S0_REGS                   ((CSL_I2sRegsOvly)  0x2800)
    00103 #define CSL_I2S1_REGS                   ((CSL_I2sRegsOvly)  0x2900)
    00104 #define CSL_I2S2_REGS                   ((CSL_I2sRegsOvly)  0x2A00)
    00105 #define CSL_I2S3_REGS                   ((CSL_I2sRegsOvly)  0x2B00)
    00106 #define CSL_UART_REGS                   ((CSL_UartRegsOvly) 0x1B00)
    00107 #define CSL_SPI_REGS                    ((CSL_SpiRegsOvly)  0x3000)
    00108 #define CSL_MMCSD0_REGS                 ((CSL_MmcsdRegsOvly)0x3A00)
    00109 #define CSL_MMCSD1_REGS                 ((CSL_MmcsdRegsOvly)0x3B00)
    00110 #define CSL_LCDC_REGS                   ((CSL_LcdcRegsOvly) 0x2E00)
    00111 #define CSL_RTC_REGS                    ((CSL_RtcRegsOvly)  0x1900)
    00112 #define CSL_DMA0_REGS                   ((CSL_DmaRegsOvly)  0x0C00)
    00113 #define CSL_DMA1_REGS                   ((CSL_DmaRegsOvly)  0x0D00)
    00114 #define CSL_DMA2_REGS                   ((CSL_DmaRegsOvly)  0x0E00)
    00115 #define CSL_DMA3_REGS                   ((CSL_DmaRegsOvly)  0x0F00)
    00116 #define CSL_GPIO_REGS                   ((CSL_GpioRegsOvly) 0x1c00)
    00117 #define CSL_SYSCTRL_REGS                ((CSL_SysRegsOvly)  0x1c00)
    00118 #define CSL_CPU_REGS                    ((CSL_CpuRegsOvly)  0x0000)
    00119 #define CSL_WDT_REGS                    ((CSL_WdtRegsOvly)  0x1880)
    00120 #define CSL_TIM_0_REGS                  ((CSL_TimRegsOvly)  0x1810)
    00121 #define CSL_TIM_1_REGS                  ((CSL_TimRegsOvly)  0x1850)
    00122 #define CSL_TIM_2_REGS                  ((CSL_TimRegsOvly)  0x1890)
    00123
    00124
    00126 #define CSL_EMIF_CS2_DATA_BASE_ADDR                 (0x400000u)
    00127
    00128 #define CSL_EMIF_CS3_DATA_BASE_ADDR                 (0x600000u)
    00129
    00130 #define CSL_EMIF_CS4_DATA_BASE_ADDR                 (0x700000u)
    00131
    00132 #define CSL_EMIF_CS5_DATA_BASE_ADDR                 (0x780000u)
    00133
    00134 #define CSL_EMIF_CSx_ADDR_OFFSET                    (0x1000u)
    00135
    00136 #define CSL_EMIF_CSx_CMD_OFFSET                     (0x2000u)
    00137
    00138 #define CSL_NAND_CE0_ADDR                           (0x2000000u)
    00139
    00140 #define CSL_NAND_CE1_ADDR                           (0x3000000u)
    00141
    00142 #define CSL_ASYNC_CE0_ADDR                          (0x4000000u)
    00143
    00144 #define CSL_ASYNC_CE1_ADDR                          (0x5000000u)
    00145
    00146 #define CSL_IAFR_REGS                               (0x1C14)
    00147 #endif   // _SOC_H