C55XX CSL EXAMPLE

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MMCSD EXAMPLE DOCUMENTATION

## MMCSD EXAMPLE1 - MMC CARD POLL MODE TEST

### TEST DESCRIPTION:

This test code verifies the functionality of the CSL MMCSD module with MultiMediaCard(MMC). This Functionality test includes detecting, initializing, configuring, writing, reading the MMC card using CSL MMCSD module. All these steps are carried out in sequence by different CSL APIs. After the card detection phase test code verifies whether the detected card is MMC or not. Test code stops execution and returns with error incase of card is not MMC. After the successful detection of the MMC, it is initialized and configured. Two data buffers 'gMmcWriteBuff' and 'gMmcReadBuff' are used for MMC write and read operations respectively. MMC write buffer is initialized to values 0 to 255 and is written to MMC sector zero using MMC_write API. Same MMC sector is read using MMC_read API and the data read is stored in the MMC read buffer. Data in the buffers 'gMmcWriteBuff' and 'gMmcReadBuff' is compared to check if MMC read and write operations are successful or not. This test code uses POLLED mode to read and write the MMC data. Functions 'isr_rcv' and 'isr_txmt' are provided to verify MMC_setCallBack API.

Maximum value of the clock at which memory data transaction takes place can be controlled using the macro 'CSL_MMC_CLOCK_MAX_KHZ'. Depending on the clock at which CPU is running, memory clock will be configured to the possible value that is nearest to the value defined by this macro. memory clock will be configured to a value less than or equal to but not greater than the value defined by this macro. Changing this macro value will automatically change the MMC clock divider value. memory clock will be generated from the system clock based on equation

       memory clock = (system clock) / (2 * (CLKRT + 1)
          - memory clock is clock for the memory card
          - system clock is clock at which CPU us running
          - CLKRT is value of clock rate configured in clock control register

As per this equation mmc clock that can be generated is always less than or equal to half of the system clock value. Value of 'CLKRT' can range from 0 to 255. Maximum and minimum mmc clock values that can be generated at a particular frequency are limited by the minimum and maximum value of the memory clock rate (CLKRT).

NOTE: THIS TEST IS INTENDED TO BE USED WITH MMC CARD. IT FAILS WITH SD CARD

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert "MMC" card into the MMC/SD socket(J9) on the C5505/C5515 EVM
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_MMCSD_MmcCardExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Data in the read and write buffers should match

============================================================================

## MMCSD EXAMPLE2 - SD CARD POLL MODE TEST

### TEST DESCRIPTION:

This test code verifies the functionality of the CSL MMCSD module with Secure Digital(SD) card. This Functionality test includes detecting, initializing, configuring, writing, reading the SD card using CSL MMCSD module. All these steps are carried out in sequence by different CSL APIs. After the card detection phase test code verifies whether the detected card is SD or not. Test code stops execution and returns with error incase of card is not SD. After the successful detection of the SD card, it is initialized and configured. Two data buffers 'gSdWriteBuff' and 'gSdReadBuff' are used for SD card write and read operations respectively. SD card write buffer is initialized to values 0 to 255 and is written to SD card sector zero using MMC_write API. Same SD card sector is read using MMC_read API and the data read is stored in the SD card read buffer. Data in the buffers 'gSdWriteBuff' and 'gSdReadBuff' is compared to check whether SD card read and write operations are successful or not. This test code uses POLLED mode to read and write the SD card data.

Maximum value of the clock at which memory data transaction takes place can be controlled using the macro 'CSL_SD_CLOCK_MAX_KHZ'. Depending on the clock at which CPU is running, SD clock will be configured to the possible value that is nearest to the value defined by this macro. SD clock will be configured to a value less than or equal to but not greater than the value defined by this macro. Changing this macro value will automatically change the memory clock divider value. memory clock will be generated from the system clock based on equation

       memory clock = (system clock) / (2 * (CLKRT + 1)
          - memory clock is clock for the memory card
          - system clock is clock at which CPU us running
          - CLKRT is value of clock rate configured in clock control register

As per this equation memory clock that can be generated is always less than or equal to half of the system clock value. Value of 'CLKRT' can range from 0 to 255. Maximum and minimum memory clock values that can be generated at a particular CPU frequency are limited by the minimum and maximum value of the memory clock rate (CLKRT).

NOTE: THIS TEST IS INTENDED TO BE USED WITH SD CARD. IT FAILS WITH MMC.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert "SD" card into the MMC/SD socket(J9) on the C5505/C5515 EVM
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_MMCSD_MmcCardExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Data in the read and write buffers should match

============================================================================

## MMCSD EXAMPLE3 - MMC/SD CARD DMA MODE TEST

### TEST DESCRIPTION:

This test code verifies the functionality of CSL MMCSD module in DMA mode. This Functionality test includes detecting, initializing, configuring, writing, reading the SD/MMC card using CSL MMCSD module.

This test includes two parts. In the first part MMCSD write and read are performed without using the callback function. MMCSD module should be initialized and opened in DMA mode. Two DMA channels are opened for MMCSD data transfers using DMA_open API. These channels should be assigned to MMCSD internal data structures using MMC_setDmaHandle() API. MMC read and write APIs will use these handles to configure the DMA module and start the DMA data transfers. After successful detection of the card MMC module will be configured and MMC_write() API is called to write the data to the card inserted. Write API returns after successful completion of the data write using DMA module. MMC_read() API is called to read the data from the card. Read API returns after successful completion of the read operation using DMA module. Write and read buffers are compared for data verification.

In the second part of the test read and write are performed in the same way as in the first part of the test except that data call back function is configured using MMC_setDataTransferCallback() API. This call back function is called from the MMC write and read APIs after staring the DMA transfer. Completion of the data transfer should be checked in the call back function. Data transfer completion is verified using MMCSD interrupts. MMCSD interrupts should be configured and ISR should be registered using CSL INTC module.

Maximum value of the clock at which memory data transaction takes place can be controlled using the macros 'CSL_SD_CLOCK_MAX_KHZ' and 'CSL_MMC_CLOCK_MAX_KHZ' for SD and MMC cards respectively. Depending on the clock at which CPU is running, memory clock will be configured to the possible value that is nearest to the value defined by these macros. memory clock will be configured to a value less than or equal to but not greater than the value defined by these macros. Changing these macro values will automatically change the memory clock divider value. memory clock will be generated from the system clock based on equation

       memory clock = (system clock) / (2 * (CLKRT + 1)
          - memory clock is clock for the memory card
          - system clock is clock at which CPU us running
          - CLKRT is value of clock rate configured in clock control register

As per this equation memory clock that can be generated is always less than or equal to half of the system clock value. Value of 'CLKRT' can range from 0 to 255. Maximum and minimum memory clock values that can be generated at a particular CPU frequency are limited by the minimum and maximum value of the memory clock rate (CLKRT).

NOTE: THIS TEST WORKS WITH SD AND MMC CARD.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert "MMC/SD" card into the MMC/SD socket(J9) on the C5505/C5515 EVM
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_MMCSD_dmaExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Data in the read and write buffers should match in both parts of the test

============================================================================

## MMCSD EXAMPLE4 - MMCSD-ATFS INTERFACE TEST

### TEST DESCRIPTION:

This test code verifies the functionality of MMCSD-ATAFS interface. ATA File System is used to create, write and read files on the SD card. Files created by the ATFS can be read from windows PC using a card reader.

During the test a file is created on the SD card, 512 bytes of data is written to the file and the same data is read back. CSL MMCSD module should be configured before initializing the file system. During the card detection test code checks for the SD card.If no SD card is detected test exits with error. After successful detection and configuration of the SD card file system should be initialized using ATA_systemInit(). SD card should be formatted to run this test. ATA_systemInit() function fails if the card is not formatted. File with the given name is created using ATA_create() API. 512 bytes of data is written to the file created using ATA_write() API. After successful completion of write operation same data is read from the card using ATA_readLittleEndian(). Write and read buffers are compared for the data verification. The file created and data written can be accessed using a SD card reader. This test is executed in both polling and DMA modes.

Maximum value of the clock at which memory data transaction takes place can be controlled using the macro 'CSL_SD_CLOCK_MAX_KHZ'. Depending on the clock at which CPU is running, SD clock will be configured to the possible value that is nearest to the value defined by this macro. SD clock will be configured to a value less than or equal to but not greater than the value defined by this macro. Changing this macro value will automatically change the memory clock divider value. memory clock will be generated from the system clock based on equation

       memory clock = (system clock) / (2 * (CLKRT + 1)
          - memory clock is clock for the memory card
          - system clock is clock at which CPU us running
          - CLKRT is value of clock rate configured in clock control register

As per this equation memory clock that can be generated is always less than or equal to half of the system clock value. Value of 'CLKRT' can range from 0 to 255. Maximum and minimum memory clock values that can be generated at a particular CPU frequency are limited by the minimum and maximum value of the memory clock rate (CLKRT).

NOTE: THIS TEST WORKS WITH ONLY SD CARD. SD CARD SHOULD BE FORMATTED TO RUN THIS TEST.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert formatted "SD" card into the MMC/SD socket(J9) on the C5505/C5515 EVM
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_MMCSD_SdCardFSExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Data in the read and write buffers should match.
- File created should be accessible from a windows PC using card reader.

============================================================================

## MMCSD EXAMPLE5 - MMC/SD CARD INTERRUPT MODE TEST

### TEST DESCRIPTION:

This test code verifies the functionality of CSL MMCSD module in interrupt mode. This Functionality test includes detecting, initializing, configuring, writing, reading the SD/MMC card using CSL MMCSD module.

During the test MMCSD module will be initialized and opened in interrupt mode. MMCSD data transfer call back function is configured using MMC_setDataTransferCallback() API. This callback function is called from MMC read and write APIs. When this callback function is invoked, execution waits until MMCSD generates an interrupt. After receiving the interrupt call back function disables all the MMCSD interrupts and returns the value of MMC status register(MMCST0). Interrupts enabled during a particular callback will be decided by the CSL APIs. After successful detection of the card MMC module will be configured and MMC_write() API is called to write the data to the card inserted. Write API returns after successful completion of the data write. MMC_read() API is called to read the data from the card. Read API returns after successful completion of the read operation. Both read and write APIs invoke callback function during the data transfers. Write and read buffers are compared for data verification.

Maximum value of the clock at which memory data transaction takes place can be controlled using the macros 'CSL_SD_CLOCK_MAX_KHZ' and 'CSL_MMC_CLOCK_MAX_KHZ' for SD and MMC cards respectively. Depending on the clock at which CPU is running, memory clock will be configured to the possible value that is nearest to the value defined by these macros. memory clock will be configured to a value less than or equal to but not greater than the value defined by these macros. Changing these macro values will automatically change the memory clock divider value. memory clock will be generated from the system clock based on equation

       memory clock = (system clock) / (2 * (CLKRT + 1)
          - memory clock is clock for the memory card
          - system clock is clock at which CPU us running
          - CLKRT is value of clock rate configured in clock control register

As per this equation memory clock that can be generated is always less than or equal to half of the system clock value. Value of 'CLKRT' can range from 0 to 255. Maximum and minimum memory clock values that can be generated at a particular CPU frequency are limited by the minimum and maximum value of the memory clock rate (CLKRT).

NOTE: THIS TEST WORKS WITH SD AND MMC CARD.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert "MMC/SD" card into the MMC/SD socket(J9) on the C5505/C5515 EVM
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_MMCSD_dmaExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Data in the read and write buffers should match