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Modules
PLL

## Modules
| PLL Symbols Defined
| PLL Data Structures
| PLL Functions
| PLL Enumerated Data Types

## Detailed Description

## Introduction

### Overview

In simpler terms, a PLL compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is derived from a crystal oscillator, which is very stable in frequency.

Note:
  :
  - The DSP maximum operating frequency is 100MHz @ 1.3V.
  - The input to the VCO has to fall between 30KHz and 170KHz. The PLL input clock supports 32KHz to 100MHz input frequency, but the reference divider must ensure that the input to the Phase Detector falls between 30KHz and 170KHz. Refer to the formula in section 10.8.1.4.1, on page 53 of C5505 spec v1.16 on how system clock is generated.

### References