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csl_nand.h File Reference

NAND functional layer API header file. More...

`#include <cslr.h>`
`#include <csl_error.h>`
`#include <csl_types.h>`
`#include <cslr_emif.h>`
`#include <soc.h>`
`#include <csl_general.h>`

Go to the source code of this file.

## Data Structures
struct | CSL_NandAsyncWaitCfg
| Nand Async wait config structure. More...
struct | CSL_NandAsyncCfg
| Nand Async config structure. More...
struct | CSL_NandAsyncBank
| Current Asynchronous NAND Bank configuration. More...
struct | CSL_NandConfig
| Nand Hw configuration structure. More...
struct | CSL_NandObj
| This object contains the reference to the instance of nand device. More...
## Defines
#define | CSL_NAND_SB_CMD_LO_PAGE (0x00u)
| NAND device standard commands.
#define | CSL_NAND_SB_CMD_HI_PAGE (0x01u)
#define | CSL_NAND_SB_CMD_SPARE_AREA (0x50u)
#define | CSL_NAND_CMD_DEVID (0x90u)
#define | CSL_NAND_CMD_DEVADD (0x00u)
#define | CSL_NAND_CMD_RESET (0xFFu)
#define | CSL_NAND_CMD_SET (0x00u)
#define | CSL_NAND_CMD_PGRM_START (0x80u)
#define | CSL_NAND_CMD_PGRM_END (0x10u)
#define | CSL_NAND_CMD_BLK_ERASE_CMD1 (0x60u)
#define | CSL_NAND_CMD_BLK_ERASE_CMD2 (0xD0u)
#define | CSL_NAND_CMD_READY (0x40u)
#define | CSL_NAND_CMD_STATUS (0x70u)
#define | CSL_NAND_CMD_READ_START (0x00u)
#define | CSL_NAND_CMD_READ_END (0x30u)
#define | CSL_NAND_BB_CMD_RANDOM_PGRM_START (0x85u)
| Big block NAND extra commands.
#define | CSL_NAND_BB_CMD_RANDOM_READ_START (0x05u)
#define | CSL_NAND_BB_CMD_RANDOM_READ_END (0xE0u)
#define | CSL_NAND_BB_CMD_COPY_BACK_READ (0x35u)
#define | CSL_NAND_FLAG_FIRSTBITPOS (0u)
#define | CSL_NAND_MEDIA_WRITE_PROTECTED ((1L) << (CSL_NAND_FLAG_FIRSTBITPOS + 0))
#define | CSL_NAND_FLAG_LASTBITPOS (1u)
#define | CSL_NAND_BB_CMD_PGRM_STATUS_PASS (0x0000)
| NAND Status Bit definitions - Big Block.
#define | CSL_NAND_BB_CMD_CACHE_PGRM_READY (0x0020u)
#define | CSL_NAND_BB_CMD_CMD_STATUS_READY (0x0040u)
#define | CSL_NAND_BB_CMD_WP_STATUS_OPEN (0x0080u)
#define | CSL_NAND_BB_CMD_STATUS_READY
#define | CSL_NAND_BB_CMD_STATUS_SUCCESS (CSL_NAND_BB_CMD_STATUS_READY)
#define | CSL_NAND_SB_CMD_PGRM_STATUS_PASS (0x0000)
| NAND Status Bit definitions - Small Block.
#define | CSL_NAND_SB_CMD_CMD_STATUS_READY (0x0040u)
#define | CSL_NAND_SB_CMD_WP_STATUS_OPEN (0x0080u)
#define | CSL_NAND_SB_CMD_STATUS_READY
#define | CSL_NAND_SB_CMD_STATUS_SUCCESS (CSL_NAND_SB_CMD_STATUS_READY)
#define | CSL_NAND_PAGE_SIZE_MASK (0x03u)
| Extended ID masks.
#define | CSL_NAND_BLOCK_SIZE_MASK (0x30u)
#define | CSL_NAND_RED_AREA_SIZE_MASK (0x04u)
#define | CSL_NAND_ORGANIZATION_MASK (0x40u)
#define | CSL_NAND_ECC_BANK1_ENABLE (0x100u)
| ECC options for NAND Banks.
#define | CSL_NAND_ECC_BANK2_ENABLE (0x200u)
#define | CSL_NAND_ECC_BANK3_ENABLE (0x400u)
#define | CSL_NAND_ECC_BANK4_ENABLE (0x800u)
#define | CSL_NAND_BB_CACHE_PROG (0x01u)
| Big block NAND extra features.
#define | CSL_NAND_BB_COPY_BACK (0x02u)
#define | CSL_NAND_BB_RANDOM_PAGE_READ (0x04u)
#define | CSL_NAND_BB_RANDOM_PAGE_WRITE (0x08u)
#define | CSL_NAND_BB_OPTIONS
#define | CSL_NAND_BB_MLC_NAND 0x10
#define | CSL_NAND_MAX_TIMEOUT (0x7FFFFFFFu)
#define | CSL_NAND_DELAY (100)
#define | CSL_NAND_READ_STATUS_TIMEOUT (100000u)
#define | CSL_NAND_BB_PAGE_SIZE (2048u)
#define | CSL_NAND_RESET_COUNT_VAL (0x20)
#define | CSL_NAND_INV_INTR_NUM (0xFFFF)
#define | CSL_NAND_ASYNCWAITCFG_WAITPOL_DEFAULT (0x00)
| Default values of NAND Async Wait Config structure.
#define | CSL_NAND_ASYNCWAITCFG_NANDPORT_DEFAULT (0x00)
#define | CSL_NAND_ASYNCWAITCFG_WAITCYCLE_DEFAULT (0x80)
#define | CSL_NAND_ASYNCCFG_SELECTSTROBE_DEFAULT (0x00)
| Default values of NAND Async Config structure.
#define | CSL_NAND_ASYNCCFG_WEMODE_DEFAULT (0x00)
#define | CSL_NAND_ASYNCCFG_WSETUP_DEFAULT (0x0F)
#define | CSL_NAND_ASYNCCFG_WSTROBE_DEFAULT (0x1F)
#define | CSL_NAND_ASYNCCFG_WHOLD_DEFAULT (0x07)
#define | CSL_NAND_ASYNCCFG_RSETUP_DEFAULT (0x0F)
#define | CSL_NAND_ASYNCCFG_RSTROBE_DEFAULT (0x3F)
#define | CSL_NAND_ASYNCCFG_RHOLD_DEFAULT (0x07)
#define | CSL_NAND_ASYNCCFG_TAROUND_DEFAULT (0x03)
#define | CSL_NAND_ASYNCCFG_ASIZE_DEFAULT (0x00)
#define | CSL_EMIF_NCS2ECC1_LSB (0)
| EMIF CSL Bit position macros.
#define | CSL_EMIF_NCS2ECC1_MSB (11)
#define | CSL_EMIF_NCS2ECC2_LSB (0)
#define | CSL_EMIF_NCS2ECC2_MSB (11)
#define | CSL_EMIF_NCS3ECC1_LSB (0)
#define | CSL_EMIF_NCS3ECC1_MSB (11)
#define | CSL_EMIF_NCS3ECC2_LSB (0)
#define | CSL_EMIF_NCS3ECC2_MSB (11)
#define | CSL_EMIF_NCS4ECC1_LSB (0)
#define | CSL_EMIF_NCS4ECC1_MSB (11)
#define | CSL_EMIF_NCS4ECC2_LSB (0)
#define | CSL_EMIF_NCS4ECC2_MSB (11)
#define | CSL_EMIF_NCS5ECC1_LSB (0)
#define | CSL_EMIF_NCS5ECC1_MSB (11)
#define | CSL_EMIF_NCS5ECC2_LSB (0)
#define | CSL_EMIF_NCS5ECC2_MSB (11)
#define | CSL_NAND_WORD_ACCESS (0)
#define | CSL_NAND_HIGHBYTE_ACCESS (1)
#define | CSL_NAND_LOWBYTE_ACCESS (2)
#define | CSL_NAND_CHANGE_ACCESSTYPE(byte) CSL_FINS(CSL_SYSCTRL_REGS->ESCR, SYS_ESCR_BYTEMODE, byte);
| NAND module specific errors.
#define | CSL_NAND_E_TIMEOUT (CSL_ENAND_FIRST - 0)
#define | CSL_NAND_WRITEWORD(hNand, data)
#define | CSL_NAND_READWORD(hNand, data)
#define | CSL_NAND_WRITEBYTE(hNand,data)
#define | CSL_NAND_READBYTE(hNand,addr)
#define | CSL_NANDGETCOMMAND(hNand, cmd) cmd = (*(CSL_VUint16*)hNand->bank.CExCLE); \
#define | CSL_NANDGETADDRESS(hNand, addr) addr = *(CSL_VUint16*)hNand->bank.CExALE; \
#define | CSL_NANDGETWAITCFG(hNand, value) value = (Uint32)((hNand->regs->AWCCR1) | (hNand->regs->AWCCR2 << 16));
#define | CSL_NANDGETCS2ASYNCCFG(hNand, value)
#define | CSL_NANDGETCS3ASYNCCFG(hNand, value)
#define | CSL_NANDGETCS4ASYNC3CFG(hNand, value)
#define | CSL_NANDGETCS5ASYNC4CFG(hNand, value)
#define | CSL_NANDGETCTRL(hNand, value) value = (Uint16)(CSL_FEXTR(hNand->regs->NANDFCR, 13, 0));
#define | CSL_NANDGETINTRAW(hNand, intrStatus) intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIRR, 5, 0));
#define | CSL_NANDGETINTMASK(hNand, intrStatus) intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMR, 5, 0));
#define | CSL_NANDGETINTMASKSET(hNand, intrStatus) intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMSR, 5, 0));
#define | CSL_NANDGETINTMASKCLEAR(hNand, intrStatus) intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMCR, 5, 0));
## Typedefs
typedef struct CSL_NandAsyncWaitCfg | CSL_NandAsyncWaitCfg
| Nand Async wait config structure.
typedef struct CSL_NandAsyncCfg | CSL_NandAsyncCfg
| Nand Async config structure.
typedef struct CSL_NandAsyncBank | CSL_NandAsyncBank
| Current Asynchronous NAND Bank configuration.
typedef struct CSL_NandConfig | CSL_NandConfig
| Nand Hw configuration structure.
typedef struct CSL_NandObj | CSL_NandObj
| This object contains the reference to the instance of nand device.
typedef CSL_NandObj * | CSL_NandHandle
| Nand object structure pointer.
## Enumerations
enum | CSL_NandWidth { CSL_NAND_8_BIT = (0u), CSL_NAND_16_BIT = (1u) }
| NAND Width enumeration. More...
enum | CSL_NandType { CSL_NAND_NONE = 0u, CSL_NAND_BIG_BLOCK, CSL_NAND_SMALL_BLOCK, CSL_NAND_INVALID }
| Type of NAND detected. More...
enum | CSL_NandPageSize { CSL_NAND_PAGESZ_256 = (0u), CSL_NAND_PAGESZ_512 = (1u), CSL_NAND_PAGESZ_1024 = (2u), CSL_NAND_PAGESZ_2048 = (3u) }
| NAND Page size enumeration. More...
enum | CSL_NandBankNo { CSL_NAND_BANK_0 = (0u), CSL_NAND_BANK_1 = (1u), CSL_NAND_BANK_2 = (2u), CSL_NAND_BANK_3 = (3u), CSL_NAND_BANK_MAX }
| NAND Asynchronous Bank number. More...
enum | CSL_NandChipSelect { CSL_NAND_CS2 = (0u), CSL_NAND_CS3 = (1u), CSL_NAND_CS4 = (2u), CSL_NAND_CS5 = (3u) }
| NAND Chip selection. More...
enum | CSL_NandPort { CSL_NAND_RDY0 = (0u), CSL_NAND_RDY1 = (1u), CSL_ASYNC_RDY0 = (2u), CSL_ASYNC_RDY1 = (3u) }
| NAND Ports. More...
enum | CSL_NandWaitPol { CSL_NAND_WP_LOW = (0u), CSL_NAND_WP_HIGH = (1u) }
| NAND wait polarity. More...
enum | CSL_NandOpMode { CSL_NAND_OPMODE_POLLED = (0u), CSL_NAND_OPMODE_DMA = (1u), CSL_NAND_OPMODE_INTRRUPT = (2u) }
| NAND Operating mode. More...
enum | CSL_NandEmifAccess { CSL_NAND_EMIF_16BIT = (0u), CSL_NAND_EMIF_8BIT_HIGH = (1u), CSL_NAND_EMIF_8BIT_LOW = (2u) }
| EMIF Access width. More...
enum | CSL_NandInsId { CSL_NAND_INST_0 = (0u), CSL_NAND_INST_INVALID = (1u) }
| NAND instance number. More...
## Functions
CSL_Status | NAND_init (CSL_NandObj *nandObj, Uint16 nandInstId)
CSL_Status | NAND_setup (CSL_NandHandle hNand, CSL_NandConfig *nandConfig)
CSL_Status | NAND_getBankInfo (CSL_NandHandle hNand, CSL_NandAsyncBank *bank, Uint16 bankNum)
CSL_Status | NAND_setLatchEnableOffset (CSL_NandHandle hNand, Uint32 addrOffset, Uint32 cmdOffset)
CSL_Status | NAND_isStatusWriteProtected (CSL_NandHandle hNand, Uint16 *WPstatus)
CSL_Status | NAND_sendCommand (CSL_NandHandle hNand, CSL_VUint16 cmd)
CSL_Status | NAND_checkCommandStatus (CSL_NandHandle hNand)
CSL_Status | NAND_setAddress (CSL_NandHandle hNand, Uint16 addr)
CSL_Status | NAND_enableHwECC (CSL_NandHandle hNand, CSL_NandChipSelect csInput)
CSL_Status | NAND_disableHwECC (CSL_NandHandle hNand, CSL_NandChipSelect csInput)
CSL_Status | NAND_readECC (CSL_NandHandle hNand, Uint16 *eccBuffer, CSL_NandChipSelect csInput)
CSL_Status | NAND_readNBytes (CSL_NandHandle hNand, Uint16 readRequest, Uint16 *pReadBuffer, Uint16 pack, Bool spare)
CSL_Status | NAND_writeNBytes (CSL_NandHandle hNand, Uint16 writeRequest, Uint16 *pWriteBuffer, Uint16 val, Bool spare)
void | NAND_hasRandomRead (Uint32 nandOptions, Uint16 *RRstatus)
void | NAND_hasRandomWrite (Uint32 nandOptions, Uint16 *RWstatus)
void | NAND_hasCacheProg (Uint32 nandOptions, Uint16 *CPstatus)
void | NAND_hasCopyBack (Uint32 nandOptions, Uint16 *CBstatus)
CSL_Status | NAND_intrEnable (CSL_NandHandle hNand)
CSL_Status | NAND_intrDisable (CSL_NandHandle hNand)
Int16 | NAND_getIntrNum (Uint16 nandInstId)
CSL_Status | NAND_intrReadAT (CSL_NandHandle hNand, Uint16 *ATstatus)
CSL_Status | NAND_intrReadLT (CSL_NandHandle hNand, Uint16 *LTstatus)
CSL_Status | NAND_intrReadWR (CSL_NandHandle hNand, Uint16 *WRstatus)
CSL_Status | NAND_intrClear (CSL_NandHandle hNand)
static CSL_Status | NAND_getSetup (CSL_NandHandle hNand, CSL_NandConfig *getNandConfig)

## Detailed Description

NAND functional layer API header file.

Path: \(CSLPATH)\ inc