C55XX CSL EXAMPLE

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CSL NAND EXAMPLE DOCUMENTATION

## NAND EXAMPLE1 - POLL MODE TEST

### TEST DESCRIPTION:

Following example code tests the read and write operations of CSL NAND module in polled mode. A NAND page is written and read in this test. Data buffer "gnandWriteBuf" will hold the data to be written to NAND. Data buffer "gnandReadBuf" is used to store the data read from the NAND device. NAND page written/read in the current code is having column address 0x0000 and row address 0x000040. Page address can be changed by using the API NAND_setAddress.

During the test CSL NAND module will be initialized and configured write operation. NAND page address is set and write command is send to the NAND device. Data is written to the NAND device using CSL API NAND_writeNBytes. NAND ECC is read to check if there are any errors during the write operation. NAND write operation is complete at this point.

After the successful completion of the write operations NAND page address is set again and read command is send to the NAND device. Data is read from the NAND device using CSL API NAND_readNBytes. NAND ECC is read to check if there are any errors during the read operation. NAND read operation is complete at this point.After completing the read operation read and written buffers are compared to verify the test result.

This test code works with both BIG block and SMALL block NAND devices. NAND device under test should not be write protected to run this test. This test will return with error in the case of NAND device with write protection. Proper NAND device should be inserted in the NAND daughter card attached to the EVM(Applicable only to the EVMs with external daughter card) to run this test. Details of few well known NAND devices are listed in lookup table "cslNandIdLookup" to verify the NAND device ID. This test will not work with any NAND devices for which details are not available in the lookup table.

NOTE: This test assumes that a. NAND flash is connected to emif cs2 on C5505 EVM b. NAND flash is connected to emif cs4 on C5515 EVM. c. On both the EVMs A11 address bit is connected to ALE signal of NAND flash and A12 address bit is connected to CLE signal of NAND flash. This example may not work with connections that are different from above connections.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert a NAND flash into the C5505/C5515 NAND daughter card(Applicable only to the EVMs with external daughter card)
- Insert daughter card into the memory board socket on the C5505/C5515 EVM(J5,J6)(Applicable only to the EVMs with external daughter card)
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_NAND_PollExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful.

============================================================================

## NAND EXAMPLE2 - DMA MODE TEST

### TEST DESCRIPTION:

Following example code will test the read and write operations of CSL NAND module in DMA mode. A NAND page is written and read in this test. Data buffer "gnandDmaWriteBuf" will hold the data to be written to NAND. Data buffer "gnandDmaReadBuf" is used to store the data read from the NAND device. NAND page written/read in the current code is having column address 0x0000 and row address 0x000040. Page address can be changed by using the API NAND_setAddress.

During the test CSL NAND module will be initialized and configured for write operation. Two DMA channels are opened and configured for NAND write and read operations. NAND page address is set and write command is send to the NAND device. Data transfer is started on the DMA channel configured for the NAND write operation. Test code polls on the DMA transfer control register to check the completion of the DMA write to NAND. After DMA transfer completion NAND ECC is read to check if there are any errors during the write operation. NAND write operation is complete at this point. Word swap is required on the data buffer in case of testing on C5505 DSP This is done using CSL API DMA_swapWords.

After the successful completion of the write operations NAND page address is set again and read command is send to the NAND device. Data transfer is started on the DMA channel configured for the NAND read operation. Test codes polls on the DMA transfer control register to check the completion of the DMA read from NAND. After DMA transfer completion NAND ECC is read to check if there are any errors during the read operation. NAND read operation is complete at this point. After completing the read operation read and write buffers are compared to verify the test result.

This test code works with both BIG block and SMALL block NAND devices. NAND device under test should not be write protected to run this test. This test will return with error in the case of NAND device with write protection. Proper NAND device should be inserted in the NAND daughter card attached to the EVM(Applicable only to the EVMs with external daughter card) to run this test. Details of few well known NAND devices are listed in lookup table "cslNandIdLookup" to verify the NAND device ID. This test will not work with any NAND devices for which details are not available in the lookup table.

NOTE: This test assumes that a. NAND flash is connected to emif cs2 on C5505 EVM b. NAND flash is connected to emif cs4 on C5515 EVM. c. On both the EVMs A11 address bit is connected to ALE signal of NAND flash and A12 address bit is connected to CLE signal of NAND flash. This example may not work with connections that are different from above connections.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert a NAND flash into the C5505/C5515 NAND daughter card(Applicable only to the EVMs with external daughter card)
- Insert daughter card into the memory board socket on the C5505/C5515 EVM(J5,J6)(Applicable only to the EVMs with external daughter card)
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_NAND_DmaExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful.

============================================================================

## NAND EXAMPLE3 - INTERRUPT API TEST

### TEST DESCRIPTION:

Following example code tests the interrupt related APIs of CSL NAND module. NAND module interrupts are used to verify the ready status of the NAND device and to detect errors occurred during data transfer operations.

During the test four different NAND pages will be written and read using CSL NAND write and read APIs. After each write-read operation Wait-Raise(WR) interrupt is read using NAND_intrReadWR() API and Asynchronous Time-out(AT) error is read using NAND_intrReadAT() API. Asynchronous Timeout error indicates timeout errors occurred during the data transfer operations. Wait-Raise interrupt indicates NAND ready status for next data operation.

During the test NAND CSL module will be initialized and configured and NAND WR and AT interrupts are enabled. NAND page is written and read using CSL_nandReadWrite() API. This API receives NAND page row and column address as parameters. CSL NAND module will be configured for writing the page with received row address and column address. NAND page will be written using NAND_writeNBytes() API. After successful completion of write operation CSL NAND module will be configured for read operation. NAND page will be read using NAND_readNBytes() API. After completion of the read operation data buffers are compared to verify the read data. NAND_intrReadAT() API is called to check if there is any timeout error during data transfer operation. Test exits with error if the AT interrupt value is 1. If no AT interrupt is occurred NAND Wait-Raise status will be read using NAND_intrReadWR(). This status will be read until NAND device get ready for data transfer. Once the device ready status is detected CSL_nandReadWrite() will be called to write and read next NAND page. NAND row address will be incremented in each call for this API. This cycle will be repeated for four times to write and read four different NAND pages.

This test code works with both BIG block and SMALL block NAND devices. NAND device under test should not be write protected to run this test. This test will return with error in the case of NAND device with write protection. Proper NAND device should be inserted in the NAND daughter card attached to the EVM(Applicable only to the EVMs with external daughter card) to run this test. Details of few well known NAND devices are listed in lookup table "cslNandIdLookup" to verify the NAND device ID. This test will not work with any NAND devices for which details are not available in the lookup table.

NOTE: This test assumes that a. NAND flash is connected to emif cs2 on C5505 EVM b. NAND flash is connected to emif cs4 on C5515 EVM. c. On both the EVMs A11 address bit is connected to ALE signal of NAND flash and A12 address bit is connected to CLE signal of NAND flash. This example may not work with connections that are different from above connections.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert a NAND flash into the C5505/C5515 NAND daughter card(Applicable only to the EVMs with external daughter card)
- Insert daughter card into the memory board socket on the C5505/C5515 EVM(J5,J6)(Applicable only to the EVMs with external daughter card)
- Open the CCS and connect the target(C5505/C5515 EVM)
- Open the project "CSL_NAND_IntrExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- No AT interrupt should occur during data transfer operations
- Read and Write data buffer comparison should be successful.

============================================================================

## NAND EXAMPLE4 - DMA WORD SWAP TEST

### TEST DESCRIPTION:

This test is to verify the software work around for DMA hardware word swap. On C5505 DSP DMA swaps the words in the source buffer before transferring it to the destination. No data mismatch is observed when the write and read operations are done in DMA mode as the word swap occurs in both the operations. There will be data mismatch if data write is in DMA mode and read is in polling mode or vice versa. To ensure that the data will be written to memory properly in DMA mode, words in the write buffer are swapped by software. During DMA transfer DMA hardware again will do a word swap which will bring the data buffer back to original values. Similarly a word swap is required for read buffer after read operation in DMA mode. To verify this work around this test will do one data operation in DMA mode and other data operation in polled mode and compares the data buffers.

On C5515 this test is to verify that the DMA hardware word swap is eliminated and no software work around is required.

This test is having two parts. In the first part NAND page is written in DMA mode and read in polled mode. CSL DMA module will be initialized and configured before starting the NAND data transfer. Words in the NAND write buffer will be swapped as a work around for DMA hardware word swap. NAND module will be initialized, configured, page address is set and write command is sent to NAND device. NAND data width should be set to 16 bits while using DMA for data transfer. DMA data transfer will be started using DMA_start() API. DMA will transfer configured bytes of data to NAND. This completes the NAND page write operation in DMA mode. For read operation NAND page address will be set and read command will be sent to the NAND device. NAND page will be read using NAND_readNBytes() API. This completes the NAND read operation in polled mode. NAND write and read buffers are compared for data verification.

In the second part of the test NAND page will be written in polled mode and read in DMA mode. CSL DMA module will be initialized and configured for NAND read operation. CSL NAND module will be initialized, configured, page address is set and write command is sent to the NAND device. NAND page will be written using NAND_writeNBytes API. This completes the NAND write operation in polled mode. For read operation NAND page address will be set and read command will be sent to the NAND device. NAND data width should be set to 16 bits while using DMA for data read. DMA data read will be started using DMA_start() API. DMA reads configured bytes of data from NAND. This completes the NAND page read operation in DMA mode. NAND write and read buffers are compared for data verification.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

### TEST PROCEDURE:

- Insert a NAND flash into the C5505/C5515 NAND daughter card(Applicable only to the EVMs with external daughter card)
- Insert daughter card into the memory board socket on the C5505/C5515 EVM(J5,J6)(Applicable only to the EVMs with external daughter card)
- Open the CCS and connect the target (C5505/C5515 EVM)
- Open the project "CSL_NAND_DmaWordSwapExample_Out.pjt" and build it
- Load the program on to the target
- Set the PLL frequency to 12.288MHz
- Run the program and observe the test result
- Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
- Repeat the test in Release mode

### TEST RESULT:

- All the CSL APIs should return success
- Read and write data buffer comparison should be successful during both phases of the test.