csl_dma.h

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/*  ===========================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
 *
 *   Use of this software is controlled by the terms and conditions found in
 *   the license agreement under which this software has been supplied.
 *  ===========================================================================
 */

/* ============================================================================
 * Revision History
 * ================
 * 25-Aug-2008 Added DMA for CSL.
 * 27-Aug-2008 Updated for Doxygen.
 * 28-Aug-2008 Added Return Types for Error checking for API's parameter.
 * 01-Oct-2008 Added additional parameter CSL_DMA_ChannelObj pointer to the
 *             DMA_open() API.
 * 08-May-2009 Added DMA_swapWords API for C5505 PG1.4
 * 26-May-2009 Modified as per the review comments
 * 17-Dec-2009 Added Support for Ping-Pong mode for chip C5515
 * 11-Jan-2010 Modified as per the review comments
 * ============================================================================
 */

#ifndef _CSL_DMA_H_
#define _CSL_DMA_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr_dma.h>
#include <cslr_sysctrl.h>
#include <tistdtypes.h>
#include <csl_types.h>
#include <csl_error.h>
#include <soc.h>
#include <csl_general.h>

/*****************************************************************************\
          DMA global macro declarations
\*****************************************************************************/

#define CSL_DMA_MIN_TX_SIZE                 (4)

#define CSL_DMA_CHAN_MAX                    (16)

#define CSL_DMA_CHAN_COUNT                  (4)

#define CSL_DMA_CHANNEL_BUSY                (1)

#define CSL_DMA_CHANNEL_FREE                (0)

#define CSL_DMA_CHANNEL_ENABLE                (Uint16)1

#define CSL_DMA_CHANNEL_DISABLE                (Uint16)0

#define CSL_DMA_DMATCR2_DMASTART_SYNC_MASK  (0x8004)

#define CSL_DMA_UINT16_MASK                 (0xFFFF)

#define CSL_DMA_UINT16_NUMBER_BITS          (0x0010)

#define CSL_DMA_RESET_CLOCK_CYCLE           (0x20)

#define CSL_DMA_ADDR_MODE_FIXED             (0x02)

#define CSL_DMA_ADDR_MODE_INCREMENT         (0x00)

#define CSL_DMA_ADDR_SHIFT                  (0x01)

#define CSL_DMA_DARAM_START_ADDR            (0x00060)

#define CSL_DMA_DARAM_END_ADDR              (0x07FFF)

#define CSL_DMA_SARAM_START_ADDR            (0x08000)

#define CSL_DMA_SARAM_END_ADDR              (0x27FFF)

#define CSL_DMA_DARAM_ADDR_OFFSET           (0x010000)

#define CSL_DMA_SARAM_ADDR_OFFSET            (0x080000)

#define CSL_DMA_16BIT_MASK                  (0xFFFFu)

#define CSL_DMA_16BIT_SHIFT                 (16u)

/**************************************************************************\
* DMA global typedef declarations                                         *
\**************************************************************************/

typedef enum
{
    CSL_DMA_ENGINE0 = 0,                    
    CSL_DMA_ENGINE1,                        
    CSL_DMA_ENGINE2,                        
    CSL_DMA_ENGINE3,                        
    CSL_DMA_ENGINEINV                       
} CSL_DMAEngineId;

typedef enum
{
    CSL_DMA_CHAN0 = 0,                      
    CSL_DMA_CHAN1,                          
    CSL_DMA_CHAN2,                          
    CSL_DMA_CHAN3,                          
    CSL_DMA_CHAN4,                          
    CSL_DMA_CHAN5,                          
    CSL_DMA_CHAN6,                          
    CSL_DMA_CHAN7,                          
    CSL_DMA_CHAN8,                          
    CSL_DMA_CHAN9,                          
    CSL_DMA_CHAN10,                         
    CSL_DMA_CHAN11,                         
    CSL_DMA_CHAN12,                         
    CSL_DMA_CHAN13,                         
    CSL_DMA_CHAN14,                         
    CSL_DMA_CHAN15,                         
    CSL_DMA_CHAN_INV                        
} CSL_DMAChanNum;

typedef enum
{
    CSL_DMA_AUTORELOAD_DISABLE,   
    CSL_DMA_AUTORELOAD_ENABLE     
} CSL_DMAAutoReloadMode;

typedef enum
{
    CSL_DMA_TXBURST_1WORD,        
    CSL_DMA_TXBURST_2WORD,        
    CSL_DMA_TXBURST_4WORD,        
    CSL_DMA_TXBURST_8WORD,        
    CSL_DMA_TXBURST_16WORD        
} CSL_DMATxBurstLen;

typedef enum
{
    CSL_DMA_TRANSFER_COMPLETE,    
    CSL_DMA_TRANSFER_ERROR        
} CSL_DMATransferStatus;

typedef enum
{
    CSL_DMA_EVT_NONE = 0,        
    CSL_DMA_EVT_I2S0_TX = 1,     
    CSL_DMA_EVT_I2S0_RX = 2,     
    CSL_DMA_EVT_I2S1_TX = 1,     
    CSL_DMA_EVT_I2S1_RX = 2,     
    CSL_DMA_EVT_I2S2_TX = 1,     
    CSL_DMA_EVT_I2S2_RX = 2,     
    CSL_DMA_EVT_I2S3_TX = 4,     
    CSL_DMA_EVT_I2S3_RX = 5,     
    CSL_DMA_EVT_MMC_SD0_TX = 5,  
    CSL_DMA_EVT_MMC_SD0_RX = 6,  
    CSL_DMA_EVT_MMC_SD1_TX = 7,  
    CSL_DMA_EVT_MMC_SD1_RX = 8,  
    CSL_DMA_EVT_TIMER0 = 12,     
    CSL_DMA_EVT_TIMER1 = 13,     
    CSL_DMA_EVT_TIMER2 = 14,     
    CSL_DMA_EVT_UART_TX = 5,     
    CSL_DMA_EVT_UART_RX = 6,     
    CSL_DMA_EVT_I2C_TX = 1,      
    CSL_DMA_EVT_I2C_RX = 2,      
    CSL_DMA_EVT_SAR_AD = 3,      
    CSL_DMA_EVT_INVALID          
} CSL_DMAEvtType;

typedef enum
{
    CSL_DMA_READ,                 
    CSL_DMA_WRITE                 
} CSL_DMAChanDir;

typedef enum
{
    CSL_DMA_TRANSFER_IO_MEMORY,   
    CSL_DMA_TRANSFER_MEMORY       
} CSL_DMATransferType;

typedef enum
{
    CSL_DMA_SOFTWARE_TRIGGER,     
    CSL_DMA_EVENT_TRIGGER         
} CSL_DMATriggerType;

typedef enum
{
    CSL_DMA_INTERRUPT_DISABLE,     
    CSL_DMA_INTERRUPT_ENABLE       
} CSL_DMAInterruptState;

#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))

typedef enum
{
    CSL_DMA_PING_PONG_DISABLE,     
    CSL_DMA_PING_PONG_ENABLE       
} CSL_DMAPingPongMode;

#endif

typedef struct
{
    CSL_DmaRegsOvly        dmaRegs;    
    CSL_DMAChanNum         chanNum;   
    CSL_DMAEngineId        dmaInstNum; 
    Bool                   isChanFree; 
    CSL_DMAChanDir         chanDir;    
    CSL_DMATriggerType     trigger;    
    CSL_DMATransferType    trfType;    
    CSL_DMAInterruptState  dmaInt;     
#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    Bool                   pingPongEnabled;
#endif

} CSL_DMA_ChannelObj;

typedef CSL_DMA_ChannelObj     *CSL_DMA_Handle;

typedef struct
{
#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    CSL_DMAPingPongMode       pingPongMode;
#endif

    CSL_DMAAutoReloadMode     autoMode;
    CSL_DMATxBurstLen         burstLen;
    CSL_DMATriggerType        trigger; 
    CSL_DMAEvtType            dmaEvt;  
    CSL_DMAInterruptState     dmaInt;  
    CSL_DMAChanDir            chanDir; 
    CSL_DMATransferType       trfType; 
    Uint16                    dataLen; 
    Uint32                    srcAddr; 
    Uint32                    destAddr;
} CSL_DMA_Config;

/******************************************************************************
 * DMA function declarations
 *****************************************************************************/

CSL_Status DMA_init (void);

CSL_DMA_Handle DMA_open (
    CSL_DMAChanNum       chanNum,
    CSL_DMA_ChannelObj   *pDmaChanObj,
    CSL_Status           *status
);

CSL_Status DMA_close (
    CSL_DMA_Handle         hDMA
);

CSL_Status DMA_config (
    CSL_DMA_Handle            hDMA,
    CSL_DMA_Config            *pConfig
);

CSL_Status DMA_getConfig (
    CSL_DMA_Handle            hDMA,
    CSL_DMA_Config            *pConfig
);

CSL_Status DMA_start (
    CSL_DMA_Handle            hDMA
);

CSL_Status DMA_stop (
    CSL_DMA_Handle            hDMA
);

CSL_Status DMA_reset (
    CSL_DMA_Handle         hDMA
);

CSL_Status DMA_swapWords (Uint16    *dataBuffer,
                          Uint32    dataLength);

#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))

Bool DMA_getLastTransferType (CSL_DMA_Handle    hDMA,
                              CSL_Status        *status);
#endif

/******************************************************************************
 * CSL DMA Inline function
 *****************************************************************************/
static inline
Int DMA_getStatus (
    CSL_DMA_Handle            hDMA
)
{
    Int       status;
    Uint16    chanNum;

    if(hDMA != NULL)
    {
        chanNum = hDMA->chanNum;

        while(chanNum >= CSL_DMA_PER_CNT)
        {
            chanNum = chanNum - CSL_DMA_PER_CNT;
        }

        switch((CSL_DMAChanNum)chanNum)
        {
            case CSL_DMA_CHAN0:
                status = CSL_FEXT(hDMA->dmaRegs->DMACH0TCR2, DMA_DMACH0TCR2_EN);
                break;
            case CSL_DMA_CHAN1:
                status = CSL_FEXT(hDMA->dmaRegs->DMACH1TCR2, DMA_DMACH1TCR2_EN);
                break;
            case CSL_DMA_CHAN2:
                status = CSL_FEXT(hDMA->dmaRegs->DMACH2TCR2, DMA_DMACH2TCR2_EN);
                break;
            case CSL_DMA_CHAN3:
                status = CSL_FEXT(hDMA->dmaRegs->DMACH3TCR2, DMA_DMACH3TCR2_EN);
                break;
        }
    }
    else
    {
        status = CSL_ESYS_BADHANDLE;
    }

    return status;
}
#ifdef __cplusplus
}
#endif

#endif /* _CSL_DMA_H_ */