csl_mem.h
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00001 /*  ============================================================================
00002  *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
00003  *
00004  *   Use of this software is controlled by the terms and conditions found in the
00005  *   license agreement under which this software has been supplied.
00006  *  ============================================================================
00007  */
00008 
00016 /* ============================================================================
00017  * Revision History
00018  * ================
00019  * 04-May-2009 Created for retention mode support on C5505 PG1.4
00020  * 26-May-2009 Code modified as per the review comments
00021  * 14-Dec-2009 Added support for partial retention mode for chip C5515
00022  * ============================================================================
00023  */
00024 
00051 #ifndef _CSL_MEM_H_
00052 #define _CSL_MEM_H_
00053 
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057 
00058 #include <cslr.h>
00059 #include <csl_error.h>
00060 #include <csl_types.h>
00061 #include <soc.h>
00062 #include <csl_general.h>
00063 
00082 /*****************************************************************************\
00083           MEMORY global macro declarations
00084 \*****************************************************************************/
00085 
00090 #define CSL_DARAM_BANK_COUNT          (8)
00091 
00092 #define CSL_SARAM_BANK_COUNT          (32)
00093 
00095 #define CSL_DARAM_BANK_NUM_MAX        (CSL_DARAM_BANK_COUNT - 1)
00096 
00097 #define CSL_SARAM_BANK_NUM_MAX        (CSL_SARAM_BANK_COUNT - 1)
00098 
00100 #define CSL_MEM_DARAM_BANK0           (0)
00101 
00102 #define CSL_MEM_DARAM_BANK7           (7u)
00103 
00105 #define CSL_MEM_SARAM_BANK0           (0)
00106 
00107 #define CSL_MEM_SARAM_BANK8           (8u)
00108 
00109 #define CSL_MEM_SARAM_BANK16          (16u)
00110 
00111 #define CSL_MEM_SARAM_BANK24          (24u)
00112 
00113 #define CSL_MEM_SARAM_BANK31          (31u)
00114 
00116 #define CSL_MEM_ENABLE_ALL_SLEEP      (0xAAAAu)
00117 
00118 #define CSL_MEM_DISABLE_ALL_SLEEP     (0xFFFFu)
00119 
00121 #define CSL_MEM_ENABLE_BANK_SLEEP     (0x0002)
00122 
00123 #define CSL_MEM_DISABLE_BANK_SLEEP    (0x0003)
00124 
00126 #define CSL_MEM_SLEEPMODE_BIT_MASK    (0x0003)
00127 
00129 #define CSL_MEM_DARAM_BANKMASK        (0xFFu)
00130 
00132 #define CSL_MEM_MAKE_BANKMASK(bankNumber)    ((Uint32)1 << bankNumber)
00133 
00137 /**************************************************************************\
00138 * MEMORY global typedef declarations                                       *
00139 \**************************************************************************/
00140 
00151 typedef enum
00152 {
00153     CSL_MEM_DARAM,    /* Memory type is DARAM */
00154     CSL_MEM_SARAM,    /* Memory type is SARAM */
00155     CSL_MEM_INVALID   /* Invalid Memory type  */
00156 } CSL_MemType;
00157 
00163 typedef enum
00164 {
00165     CSL_MEM_MSDARAM_CLOCK_ON,    /* MSDARAM clock will be set to ON  */
00166     CSL_MEM_MSDARAM_CLOCK_OFF    /* MSDARAM clock will be set to OFF */
00167 } CSL_MEMmSDRAMClock;
00168 
00173 /**************************************************************************\
00174 * MEMORY function declarations                                              *
00175 \**************************************************************************/
00176 
00215 CSL_Status MEM_init(void);
00216 
00260 CSL_Status MEM_enableRetentionMode (CSL_MemType    memType);
00261 
00303 CSL_Status MEM_disableRetentionMode (CSL_MemType    memType);
00304 
00305 
00306 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
00307 
00387 CSL_Status MEM_enablePartialRetentionMode (CSL_MemType    memType,
00388                                            Uint16         bankNumber,
00389                                            Uint32         bankMask);
00390 
00466 CSL_Status MEM_disablePartialRetentionMode (CSL_MemType    memType,
00467                                             Uint16         bankNum,
00468                                             Uint32         bankMask);
00469 
00505 CSL_Status MEM_setmSDRAMClock (CSL_MEMmSDRAMClock    clockSwitch);
00506 
00540 Bool MEM_getmSDRAMClock (void);
00541 
00542 #endif
00543 
00544 
00548 #ifdef __cplusplus
00549 }
00550 #endif
00551 
00552 #endif    // _CSL_MEM_H_
00553