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00041 #ifndef _CSL_NAND_H_
00042 #define _CSL_NAND_H_
00043
00044 #ifdef __cplusplus
00045 extern "C" {
00046 #endif
00047
00048 #include <cslr.h>
00049 #include <csl_error.h>
00050 #include <csl_types.h>
00051 #include <cslr_emif.h>
00052 #include <soc.h>
00053 #include <csl_general.h>
00054
00055
00078
00079
00080
00081
00086 #define CSL_NAND_SB_CMD_LO_PAGE (0x00u)
00087
00088 #define CSL_NAND_SB_CMD_HI_PAGE (0x01u)
00089
00090 #define CSL_NAND_SB_CMD_SPARE_AREA (0x50u)
00091
00092 #define CSL_NAND_CMD_DEVID (0x90u)
00093
00094 #define CSL_NAND_CMD_DEVADD (0x00u)
00095
00096 #define CSL_NAND_CMD_RESET (0xFFu)
00097
00098 #define CSL_NAND_CMD_SET (0x00u)
00099
00100 #define CSL_NAND_CMD_PGRM_START (0x80u)
00101
00102 #define CSL_NAND_CMD_PGRM_END (0x10u)
00103
00104 #define CSL_NAND_CMD_BLK_ERASE_CMD1 (0x60u)
00105
00106 #define CSL_NAND_CMD_BLK_ERASE_CMD2 (0xD0u)
00107
00108 #define CSL_NAND_CMD_READY (0x40u)
00109
00110 #define CSL_NAND_CMD_STATUS (0x70u)
00111
00112 #define CSL_NAND_CMD_READ_START (0x00u)
00113
00114 #define CSL_NAND_CMD_READ_END (0x30u)
00115
00120 #define CSL_NAND_BB_CMD_RANDOM_PGRM_START (0x85u)
00121
00122 #define CSL_NAND_BB_CMD_RANDOM_READ_START (0x05u)
00123
00124 #define CSL_NAND_BB_CMD_RANDOM_READ_END (0xE0u)
00125
00126 #define CSL_NAND_BB_CMD_COPY_BACK_READ (0x35u)
00127
00128
00130 #define CSL_NAND_FLAG_FIRSTBITPOS (0u)
00131
00132 #define CSL_NAND_MEDIA_WRITE_PROTECTED ((1L) << (CSL_NAND_FLAG_FIRSTBITPOS + 0))
00133
00134 #define CSL_NAND_FLAG_LASTBITPOS (1u)
00135
00141 #define CSL_NAND_BB_CMD_PGRM_STATUS_PASS (0x0000)
00142
00143 #define CSL_NAND_BB_CMD_CACHE_PGRM_READY (0x0020u)
00144
00145 #define CSL_NAND_BB_CMD_CMD_STATUS_READY (0x0040u)
00146
00147 #define CSL_NAND_BB_CMD_WP_STATUS_OPEN (0x0080u)
00148
00149 #define CSL_NAND_BB_CMD_STATUS_READY (CSL_NAND_BB_CMD_CMD_STATUS_READY | \
00150 CSL_NAND_BB_CMD_PGRM_STATUS_PASS)
00151
00152 #define CSL_NAND_BB_CMD_STATUS_SUCCESS (CSL_NAND_BB_CMD_STATUS_READY)
00153
00159 #define CSL_NAND_SB_CMD_PGRM_STATUS_PASS (0x0000)
00160
00161 #define CSL_NAND_SB_CMD_CMD_STATUS_READY (0x0040u)
00162
00163 #define CSL_NAND_SB_CMD_WP_STATUS_OPEN (0x0080u)
00164
00165 #define CSL_NAND_SB_CMD_STATUS_READY (CSL_NAND_SB_CMD_CMD_STATUS_READY | \
00166 CSL_NAND_SB_CMD_PGRM_STATUS_PASS)
00167
00168 #define CSL_NAND_SB_CMD_STATUS_SUCCESS (CSL_NAND_SB_CMD_STATUS_READY)
00169
00170
00176 #define CSL_NAND_PAGE_SIZE_MASK (0x03u)
00177
00178 #define CSL_NAND_BLOCK_SIZE_MASK (0x30u)
00179
00180 #define CSL_NAND_RED_AREA_SIZE_MASK (0x04u)
00181
00182 #define CSL_NAND_ORGANIZATION_MASK (0x40u)
00183
00189 #define CSL_NAND_ECC_BANK1_ENABLE (0x100u)
00190
00191 #define CSL_NAND_ECC_BANK2_ENABLE (0x200u)
00192
00193 #define CSL_NAND_ECC_BANK3_ENABLE (0x400u)
00194
00195 #define CSL_NAND_ECC_BANK4_ENABLE (0x800u)
00196
00201 #define CSL_NAND_BB_CACHE_PROG (0x01u)
00202
00203 #define CSL_NAND_BB_COPY_BACK (0x02u)
00204
00205 #define CSL_NAND_BB_RANDOM_PAGE_READ (0x04u)
00206
00207 #define CSL_NAND_BB_RANDOM_PAGE_WRITE (0x08u)
00208
00209 #define CSL_NAND_BB_OPTIONS (CSL_NAND_BB_CACHE_PROG |\
00210 CSL_NAND_BB_COPY_BACK |\
00211 CSL_NAND_BB_RANDOM_PAGE_READ |\
00212 CSL_NAND_BB_RANDOM_PAGE_WRITE )
00213
00214 #define CSL_NAND_BB_MLC_NAND 0x10
00215
00217 #define CSL_NAND_MAX_TIMEOUT (0x7FFFFFFFu)
00218
00219 #define CSL_NAND_DELAY (100)
00220
00221 #define CSL_NAND_READ_STATUS_TIMEOUT (100000u)
00222
00223 #define CSL_NAND_BB_PAGE_SIZE (2048u)
00224
00225 #define CSL_NAND_RESET_COUNT_VAL (0x20)
00226
00227 #define CSL_NAND_INV_INTR_NUM (0xFFFF)
00228
00231 #define CSL_NAND_ASYNCWAITCFG_WAITPOL_DEFAULT (0x00)
00232
00233 #define CSL_NAND_ASYNCWAITCFG_NANDPORT_DEFAULT (0x00)
00234
00235 #define CSL_NAND_ASYNCWAITCFG_WAITCYCLE_DEFAULT (0x80)
00236
00239 #define CSL_NAND_ASYNCCFG_SELECTSTROBE_DEFAULT (0x00)
00240
00241 #define CSL_NAND_ASYNCCFG_WEMODE_DEFAULT (0x00)
00242
00243 #define CSL_NAND_ASYNCCFG_WSETUP_DEFAULT (0x0F)
00244
00245 #define CSL_NAND_ASYNCCFG_WSTROBE_DEFAULT (0x1F)
00246
00247 #define CSL_NAND_ASYNCCFG_WHOLD_DEFAULT (0x07)
00248
00249 #define CSL_NAND_ASYNCCFG_RSETUP_DEFAULT (0x0F)
00250
00251 #define CSL_NAND_ASYNCCFG_RSTROBE_DEFAULT (0x3F)
00252
00253 #define CSL_NAND_ASYNCCFG_RHOLD_DEFAULT (0x07)
00254
00255 #define CSL_NAND_ASYNCCFG_TAROUND_DEFAULT (0x03)
00256
00257 #define CSL_NAND_ASYNCCFG_ASIZE_DEFAULT (0x00)
00258
00263 #define CSL_EMIF_NCS2ECC1_LSB (0)
00264
00265 #define CSL_EMIF_NCS2ECC1_MSB (11)
00266
00267 #define CSL_EMIF_NCS2ECC2_LSB (0)
00268
00269 #define CSL_EMIF_NCS2ECC2_MSB (11)
00270
00271 #define CSL_EMIF_NCS3ECC1_LSB (0)
00272
00273 #define CSL_EMIF_NCS3ECC1_MSB (11)
00274
00275 #define CSL_EMIF_NCS3ECC2_LSB (0)
00276
00277 #define CSL_EMIF_NCS3ECC2_MSB (11)
00278
00279 #define CSL_EMIF_NCS4ECC1_LSB (0)
00280
00281 #define CSL_EMIF_NCS4ECC1_MSB (11)
00282
00283 #define CSL_EMIF_NCS4ECC2_LSB (0)
00284
00285 #define CSL_EMIF_NCS4ECC2_MSB (11)
00286
00287 #define CSL_EMIF_NCS5ECC1_LSB (0)
00288
00289 #define CSL_EMIF_NCS5ECC1_MSB (11)
00290
00291 #define CSL_EMIF_NCS5ECC2_LSB (0)
00292
00293 #define CSL_EMIF_NCS5ECC2_MSB (11)
00294
00296 #define CSL_NAND_WORD_ACCESS (0)
00297
00298 #define CSL_NAND_HIGHBYTE_ACCESS (1)
00299
00300 #define CSL_NAND_LOWBYTE_ACCESS (2)
00301
00302
00313 #define CSL_NAND_CHANGE_ACCESSTYPE(byte) \
00314 CSL_FINS(CSL_SYSCTRL_REGS->ESCR, SYS_ESCR_BYTEMODE, byte);
00315
00317 #define CSL_NAND_E_TIMEOUT (CSL_ENAND_FIRST - 0)
00318
00319 #if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
00320
00322 #define CSL_NAND_WRITEWORD(hNand, data) \
00323 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00324 { \
00325 *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)((data >> 8) & 0xFF); \
00326 *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)(data & 0xFFu); \
00327 } \
00328 else \
00329 { \
00330 *(CSL_VUint16*)hNand->bank.CExDATA = (Uint16)data; \
00331 }
00332
00334 #define CSL_NAND_READWORD(hNand, data) \
00335 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00336 { \
00337 data = ((*(CSL_VUint8*)hNand->bank.CExDATA) & 0xFFu); \
00338 data = ((*(CSL_VUint8*)hNand->bank.CExDATA) | (data << 8)); \
00339 } \
00340 else \
00341 { \
00342 data = (*(CSL_VUint16*)hNand->bank.CExDATA); \
00343 }
00344 #else
00345
00347 #define CSL_NAND_WRITEWORD(hNand, data) \
00348 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00349 { \
00350 *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)(data & 0xFFu); \
00351 *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)((data >> 8) & 0xFF); \
00352 } \
00353 else \
00354 { \
00355 *(CSL_VUint16*)hNand->bank.CExDATA = (Uint16)data; \
00356 }
00357
00359 #define CSL_NAND_READWORD(hNand, data) \
00360 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00361 { \
00362 data = ((*(CSL_VUint8*)hNand->bank.CExDATA) & 0xFFu); \
00363 data |= ((*(CSL_VUint8*)hNand->bank.CExDATA) << 8); \
00364 } \
00365 else \
00366 { \
00367 data = (*(CSL_VUint16*)hNand->bank.CExDATA); \
00368 }
00369
00370 #endif
00371
00372
00374 #define CSL_NAND_WRITEBYTE(hNand ,data) \
00375 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00376 { \
00377 *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)(data); \
00378 } \
00379 else \
00380 { \
00381 *(CSL_VUint16*)hNand->bank.CExDATA = (Uint16)data; \
00382 }
00383
00385 #define CSL_NAND_READBYTE(hNand ,addr) \
00386 if(hNand->nandWidth == CSL_NAND_8_BIT) \
00387 { \
00388 *addr = (*(CSL_VUint8*)hNand->bank.CExDATA); \
00389 } \
00390 else \
00391 { \
00392 *addr = (*(CSL_VUint16*)hNand->bank.CExDATA); \
00393 }
00394
00396 #define CSL_NANDGETCOMMAND(hNand,cmd) \
00397 cmd = (*(CSL_VUint16*)hNand->bank.CExCLE); \
00398
00399
00400 #define CSL_NANDGETADDRESS(hNand,addr) \
00401 addr = *(CSL_VUint16*)hNand->bank.CExALE; \
00402
00403
00404 #define CSL_NANDGETWAITCFG(hNand,value) \
00405 value = (Uint32)((hNand->regs->AWCCR1) | (hNand->regs->AWCCR2 << 16));
00406
00407
00409 #define CSL_NANDGETCS2ASYNCCFG(hNand,value) \
00410 value = (Uint32)(hNand->regs->ACS2CR1 | \
00411 (hNand->regs->ACS2CR2 << 16)); \
00412
00413
00414 #define CSL_NANDGETCS3ASYNCCFG(hNand,value) \
00415 value = (Uint32)(hNand->regs->ACS3CR1 | \
00416 (hNand->regs->ACS3CR2 << 16)); \
00417
00418
00419 #define CSL_NANDGETCS4ASYNC3CFG(hNand,value) \
00420 value = (Uint32)(hNand->regs->ACS4CR1 | \
00421 (hNand->regs->ACS4CR2 << 16)); \
00422
00423
00424 #define CSL_NANDGETCS5ASYNC4CFG(hNand,value) \
00425 value = (Uint32)(hNand->regs->ACS5CR1 | \
00426 (hNand->regs->ACS5CR2 << 16)); \
00427
00428
00429 #define CSL_NANDGETCTRL(hNand,value) \
00430 value = (Uint16)(CSL_FEXTR(hNand->regs->NANDFCR, 13, 0));
00431
00433 #define CSL_NANDGETINTRAW(hNand,intrStatus) \
00434 intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIRR, 5, 0));
00435
00437 #define CSL_NANDGETINTMASK(hNand,intrStatus) \
00438 intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMR, 5, 0));
00439
00441 #define CSL_NANDGETINTMASKSET(hNand,intrStatus) \
00442 intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMSR, 5, 0));
00443
00445 #define CSL_NANDGETINTMASKCLEAR(hNand,intrStatus) \
00446 intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMCR, 5, 0));
00447
00452
00453
00454
00455
00462 typedef enum {
00464 CSL_NAND_8_BIT = (0u),
00466 CSL_NAND_16_BIT = (1u)
00467 } CSL_NandWidth;
00468
00472 typedef enum {
00474 CSL_NAND_NONE = 0u,
00476 CSL_NAND_BIG_BLOCK,
00478 CSL_NAND_SMALL_BLOCK,
00480 CSL_NAND_INVALID
00481 } CSL_NandType;
00482
00486 typedef enum {
00488 CSL_NAND_PAGESZ_256 = (0u),
00490 CSL_NAND_PAGESZ_512 = (1u),
00492 CSL_NAND_PAGESZ_1024 = (2u),
00494 CSL_NAND_PAGESZ_2048 = (3u)
00495 } CSL_NandPageSize;
00496
00500 typedef enum {
00502 CSL_NAND_BANK_0 = (0u),
00504 CSL_NAND_BANK_1 = (1u),
00506 CSL_NAND_BANK_2 = (2u),
00508 CSL_NAND_BANK_3 = (3u),
00510 CSL_NAND_BANK_MAX
00511 } CSL_NandBankNo;
00512
00516 typedef enum {
00518 CSL_NAND_CS2 = (0u),
00520 CSL_NAND_CS3 = (1u),
00522 CSL_NAND_CS4 = (2u),
00524 CSL_NAND_CS5 = (3u)
00525 } CSL_NandChipSelect;
00526
00530 typedef enum {
00532 CSL_NAND_RDY0 = (0u),
00534 CSL_NAND_RDY1 = (1u),
00536 CSL_ASYNC_RDY0 = (2u),
00538 CSL_ASYNC_RDY1 = (3u)
00539 } CSL_NandPort;
00540
00544 typedef enum {
00546 CSL_NAND_WP_LOW = (0u),
00548 CSL_NAND_WP_HIGH = (1u)
00549 } CSL_NandWaitPol;
00550
00554 typedef enum {
00556 CSL_NAND_OPMODE_POLLED = (0u),
00558 CSL_NAND_OPMODE_DMA = (1u),
00560 CSL_NAND_OPMODE_INTRRUPT = (2u)
00561 } CSL_NandOpMode;
00562
00566 typedef enum {
00568 CSL_NAND_EMIF_16BIT = (0u),
00570 CSL_NAND_EMIF_8BIT_HIGH = (1u),
00572 CSL_NAND_EMIF_8BIT_LOW = (2u)
00573 } CSL_NandEmifAccess;
00574
00578 typedef enum {
00580 CSL_NAND_INST_0 = (0u),
00582 CSL_NAND_INST_INVALID = (1u)
00583 } CSL_NandInsId;
00584
00585
00589
00590
00591
00592
00600 typedef struct CSL_NandAsyncWaitCfg {
00602 CSL_NandWaitPol waitPol;
00604 CSL_NandPort nandPort;
00606 Uint16 waitCycles;
00607 } CSL_NandAsyncWaitCfg;
00608
00612 typedef struct CSL_NandAsyncCfg {
00614 Uint16 selectStrobe;
00616 Uint16 ewMode;
00618 Uint16 w_setup;
00620 Uint16 w_strobe;
00622 Uint16 w_hold;
00624 Uint16 r_setup;
00626 Uint16 r_strobe;
00628 Uint16 r_hold;
00630 Uint16 turnAround;
00632 Uint16 aSize;
00633 } CSL_NandAsyncCfg;
00634
00638 typedef struct CSL_NandAsyncBank {
00640 volatile Uint32 CExDATA;
00642 volatile Uint32 CExALE;
00644 volatile Uint32 CExCLE;
00646 volatile Uint32 CExNUM;
00647 } CSL_NandAsyncBank;
00648
00652 typedef struct CSL_NandConfig {
00654 CSL_NandWidth nandWidth;
00656 CSL_NandPageSize nandPageSize;
00658 CSL_NandBankNo nandBankNo;
00660 CSL_NandEmifAccess emifAccess;
00662 CSL_NandOpMode nandOpMode;
00664 CSL_NandType nandType;
00666 CSL_NandChipSelect chipSelect;
00668 CSL_NandAsyncWaitCfg *asyncWaitCfg;
00670 CSL_NandAsyncCfg *asyncCfg;
00671 } CSL_NandConfig;
00672
00679 typedef struct CSL_NandObj {
00681 CSL_EmifRegsOvly regs;
00683 CSL_SysRegsOvly sysCtrlRegs;
00685 Uint16 instId;
00687 CSL_NandWidth nandWidth;
00689 Int intrNumNand;
00691 CSL_NandAsyncBank bank;
00693 CSL_NandPageSize nandPageSize;
00695 Uint16 addrCycles;
00697 CSL_NandOpMode nandOpMode;
00699 CSL_NandType nandType;
00701 CSL_NandChipSelect chipSelect;
00703 Uint8 waitPin;
00704 } CSL_NandObj;
00705
00707 typedef CSL_NandObj *CSL_NandHandle;
00708
00713
00714
00715
00716
00757 CSL_Status NAND_init(CSL_NandObj *nandObj,
00758 Uint16 nandInstId);
00759
00809 CSL_Status NAND_setup(CSL_NandHandle hNand,
00810 CSL_NandConfig *nandConfig);
00811
00869 CSL_Status NAND_getBankInfo(CSL_NandHandle hNand,
00870 CSL_NandAsyncBank *bank,
00871 Uint16 bankNum);
00872
00933 CSL_Status NAND_setLatchEnableOffset(CSL_NandHandle hNand,
00934 Uint32 addrOffset,
00935 Uint32 cmdOffset);
00936
00989 CSL_Status NAND_isStatusWriteProtected(CSL_NandHandle hNand,
00990 Uint16 *WPstatus);
00991
01039 CSL_Status NAND_sendCommand(CSL_NandHandle hNand,
01040 CSL_VUint16 cmd);
01041
01082 CSL_Status NAND_checkCommandStatus(CSL_NandHandle hNand);
01083
01133 CSL_Status NAND_setAddress(CSL_NandHandle hNand,
01134 Uint16 addr);
01135
01182 CSL_Status NAND_enableHwECC(CSL_NandHandle hNand,
01183 CSL_NandChipSelect csInput);
01184
01226 CSL_Status NAND_disableHwECC(CSL_NandHandle hNand,
01227 CSL_NandChipSelect csInput);
01228
01273 CSL_Status NAND_readECC(CSL_NandHandle hNand,
01274 Uint16 *eccBuffer,
01275 CSL_NandChipSelect csInput);
01276
01334 CSL_Status NAND_readNBytes(CSL_NandHandle hNand,
01335 Uint16 readRequest,
01336 Uint16 *pReadBuffer,
01337 Uint16 pack,
01338 Bool spare);
01339
01399 CSL_Status NAND_writeNBytes(CSL_NandHandle hNand,
01400 Uint16 writeRequest,
01401 Uint16 *pWriteBuffer,
01402 Uint16 val,
01403 Bool spare);
01404
01443 void NAND_hasRandomRead(Uint32 nandOptions,
01444 Uint16 *RRstatus);
01445
01484 void NAND_hasRandomWrite(Uint32 nandOptions,
01485 Uint16 *RWstatus);
01486
01524 void NAND_hasCacheProg(Uint32 nandOptions,
01525 Uint16 *CPstatus);
01526
01564 void NAND_hasCopyBack(Uint32 nandOptions,
01565 Uint16 *CBstatus);
01566
01608 CSL_Status NAND_intrEnable(CSL_NandHandle hNand);
01609
01654 CSL_Status NAND_intrDisable(CSL_NandHandle hNand);
01655
01690 Int16 NAND_getIntrNum(Uint16 nandInstId);
01691
01737 CSL_Status NAND_intrReadAT(CSL_NandHandle hNand,
01738 Uint16 *ATstatus);
01739
01785 CSL_Status NAND_intrReadLT(CSL_NandHandle hNand,
01786 Uint16 *LTstatus);
01787
01834 CSL_Status NAND_intrReadWR(CSL_NandHandle hNand,
01835 Uint16 *WRstatus);
01836
01881 CSL_Status NAND_intrClear(CSL_NandHandle hNand);
01882
01938 static inline
01939 CSL_Status NAND_getSetup(CSL_NandHandle hNand,
01940 CSL_NandConfig *getNandConfig)
01941 {
01942 volatile ioport Uint16 *asyncCfg0Addr;
01943 volatile ioport Uint16 *asyncCfg1Addr;
01944 Int16 loopCount;
01945 Uint16 tempVal;
01946 CSL_Status result;
01947
01948 result = CSL_SOK;
01949
01950 if((hNand != NULL) && (getNandConfig != NULL))
01951 {
01952 getNandConfig->nandWidth = hNand->nandWidth;
01953 getNandConfig->nandPageSize = hNand->nandPageSize;
01954 getNandConfig->nandOpMode = hNand->nandOpMode;
01955 getNandConfig->nandType = hNand->nandType;
01956
01957
01958 tempVal = CSL_FEXTR(hNand->regs->NANDFCR,
01959 CSL_EMIF_NANDFCR_CS5_USE_NAND_SHIFT,
01960 CSL_EMIF_NANDFCR_CS2_USE_NAND_SHIFT);
01961
01962 loopCount = -1;
01963 while(tempVal)
01964 {
01965 loopCount++;
01966 tempVal = (tempVal >> 1);
01967 }
01968
01969 getNandConfig->chipSelect = (CSL_NandChipSelect)loopCount;
01970
01971
01972 switch(getNandConfig->chipSelect)
01973 {
01974 case CSL_NAND_CS2:
01975
01976 getNandConfig->asyncWaitCfg->nandPort = \
01977 (CSL_NandPort)CSL_FEXT(hNand->regs->AWCCR2, \
01978 EMIF_AWCCR2_CS2_WAIT);
01979
01980 asyncCfg0Addr = &(hNand->regs->ACS2CR1);
01981 asyncCfg1Addr = &(hNand->regs->ACS2CR2);
01982 break;
01983
01984 case CSL_NAND_CS3:
01985
01986 getNandConfig->asyncWaitCfg->nandPort = \
01987 (CSL_NandPort)CSL_FEXT(hNand->regs->AWCCR2, \
01988 EMIF_AWCCR2_CS3_WAIT);
01989
01990 asyncCfg0Addr = &(hNand->regs->ACS3CR1);
01991 asyncCfg1Addr = &(hNand->regs->ACS3CR2);
01992 break;
01993
01994 case CSL_NAND_CS4:
01995
01996 getNandConfig->asyncWaitCfg->nandPort = \
01997 (CSL_NandPort)CSL_FEXT(hNand->regs->AWCCR2, \
01998 EMIF_AWCCR2_CS4_WAIT);
01999
02000 asyncCfg0Addr = &(hNand->regs->ACS4CR1);
02001 asyncCfg1Addr = &(hNand->regs->ACS4CR2);
02002 break;
02003
02004 case CSL_NAND_CS5:
02005
02006 getNandConfig->asyncWaitCfg->nandPort = \
02007 (CSL_NandPort)CSL_FEXT(hNand->regs->AWCCR2, \
02008 EMIF_AWCCR2_CS5_WAIT);
02009
02010 asyncCfg0Addr = &(hNand->regs->ACS5CR1);
02011 asyncCfg1Addr = &(hNand->regs->ACS5CR2);
02012 break;
02013
02014 default:
02015 break;
02016 }
02017
02018
02019 getNandConfig->asyncWaitCfg->waitPol = \
02020 (CSL_NandWaitPol)CSL_FEXT(hNand->regs->AWCCR2, \
02021 EMIF_AWCCR2_WP0);
02022
02023
02024 getNandConfig->asyncWaitCfg->waitCycles = CSL_FEXT(hNand->regs->AWCCR1, \
02025 EMIF_AWCCR1_MEWC);
02026
02027
02028
02029
02030 getNandConfig->asyncCfg->selectStrobe = CSL_FEXT(*asyncCfg1Addr, \
02031 EMIF_ACS2CR2_SS);
02032
02033 getNandConfig->asyncCfg->ewMode = CSL_FEXT(*asyncCfg1Addr, \
02034 EMIF_ACS2CR2_EW);
02035
02036 getNandConfig->asyncCfg->w_setup = CSL_FEXT(*asyncCfg1Addr, \
02037 EMIF_ACS2CR2_WSETUP);
02038
02039 getNandConfig->asyncCfg->w_strobe = CSL_FEXT(*asyncCfg1Addr, \
02040 EMIF_ACS2CR2_WSTROBE);
02041
02042 getNandConfig->asyncCfg->w_hold = CSL_FEXT(*asyncCfg1Addr, \
02043 EMIF_ACS2CR2_WHOLD);
02044
02045 getNandConfig->asyncCfg->r_setup = ((CSL_FEXT(*asyncCfg1Addr, \
02046 EMIF_ACS2CR2_RSETUPMSB) << 3) | \
02047 (CSL_FEXT(*asyncCfg0Addr, \
02048 EMIF_ACS2CR1_RSETUPLSB) & 0x7));
02049
02050 getNandConfig->asyncCfg->r_strobe = CSL_FEXT(*asyncCfg0Addr, \
02051 EMIF_ACS2CR1_RSTROBE);
02052
02053 getNandConfig->asyncCfg->r_hold = CSL_FEXT(*asyncCfg0Addr, \
02054 EMIF_ACS2CR1_RHOLD);
02055
02056 getNandConfig->asyncCfg->turnAround = CSL_FEXT(*asyncCfg0Addr, \
02057 EMIF_ACS2CR1_TA);
02058
02059 getNandConfig->asyncCfg->aSize = CSL_FEXT(*asyncCfg0Addr, \
02060 EMIF_ACS2CR1_ASIZE);
02061
02062
02063 getNandConfig->emifAccess = \
02064 (CSL_NandEmifAccess)CSL_FEXT(hNand->sysCtrlRegs->ESCR, \
02065 SYS_ESCR_BYTEMODE);
02066 }
02067 else
02068 {
02069 result = CSL_ESYS_INVPARAMS;
02070 }
02071
02072 return(result);
02073 }
02074
02080 #ifdef __cplusplus
02081 }
02082 #endif
02083
02084 #endif // _CSL_NAND_H_
02085
1.7.4