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Defines | |
| #define | CSL_DAT_TIME_OUT (0xFFF) |
| #define | CSL_DAT_CHANNEL_BUSY (0x1) |
| #define | CSL_DAT_CHANNEL_FREE (0) |
| #define | CSL_DAT_TXBURST_WORD_LENGTH (0x0) |
| #define | CSL_DAT_CHANNEL_ENABLE (Uint16)1 |
| #define | CSL_DAT_CHANNEL_DISABLE (Uint16)0 |
| #define | CSL_DAT_CHAN_MAX (16) |
| #define | CSL_DAT_CHAN_PRIORITY_HIGH (0xF) |
| #define | CSL_DAT_CHAN_PRIORITY_LOW (0x0) |
| #define | CSL_DMA_MIN_TX_SIZE (4) |
| #define | CSL_DMA_UINT16_MASK (0xFFFF) |
| #define | CSL_DMA_UINT16_NUMBER_BITS (0x0010) |
| #define | CSL_DMA_ADDR_SHIFT (0x01) |
| #define | CSL_DMA_ADDR_MODE_FIXED (0x02) |
| #define | CSL_DMA_ADDR_MODE_INCREMENT (0x00) |
| #define | CSL_DMA_DARAM_START_ADDR (0x00060) |
| #define | CSL_DMA_DARAM_END_ADDR (0x07FFF) |
| #define | CSL_DMA_SARAM_START_ADDR (0x08000) |
| #define | CSL_DMA_SARAM_END_ADDR (0x27FFF) |
| #define | CSL_DMA_DARAM_ADDR_OFFSET (0x010000) |
| #define | CSL_DMA_SARAM_ADDR_OFFSET (0x080000) |
| #define CSL_DAT_CHAN_MAX (16) |
Total no of channels for all DMA Engines
| #define CSL_DAT_CHAN_PRIORITY_HIGH (0xF) |
Total no of channels for all DMA Engines
| #define CSL_DAT_CHAN_PRIORITY_LOW (0x0) |
Total no of channels for all DMA Engines
Referenced by DAT_close().
| #define CSL_DAT_CHANNEL_BUSY (0x1) |
hash define value for channel busy status
Referenced by DAT_open().
| #define CSL_DAT_CHANNEL_DISABLE (Uint16)0 |
hash define value for channel disable bit
Referenced by DAT_copy(), and DAT_fill().
| #define CSL_DAT_CHANNEL_ENABLE (Uint16)1 |
hash define value for channel enable bit
Referenced by DAT_copy(), and DAT_fill().
| #define CSL_DAT_CHANNEL_FREE (0) |
hash define value for channel free status
Referenced by DAT_close().
| #define CSL_DAT_TIME_OUT (0xFFF) |
Time out value for comming out of the infinite loop
Referenced by DAT_wait().
| #define CSL_DAT_TXBURST_WORD_LENGTH (0x0) |
hash define value for burst length
Referenced by DAT_copy(), and DAT_fill().
| #define CSL_DMA_ADDR_MODE_FIXED (0x02) |
Value for fixed addr mode
Referenced by DAT_fill(), and DMA_config().
| #define CSL_DMA_ADDR_MODE_INCREMENT (0x00) |
Value for incr. addr mode
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_ADDR_SHIFT (0x01) |
shift value to change cpu addr for DMA
Referenced by DAT_copy(), DAT_fill(), DMA_config(), and DMA_getConfig().
| #define CSL_DMA_DARAM_ADDR_OFFSET (0x010000) |
DARAM starting address seen by DMA
Referenced by DAT_copy(), DAT_fill(), DMA_config(), and DMA_getConfig().
| #define CSL_DMA_DARAM_END_ADDR (0x07FFF) |
DARAM ending address
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_DARAM_START_ADDR (0x00060) |
DARAM starting address
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_MIN_TX_SIZE (4) |
Minimum Number of Bytes transfered by DMA
Referenced by DAT_copy(), and DAT_fill().
| #define CSL_DMA_SARAM_ADDR_OFFSET (0x080000) |
SARAM starting address seen by DMA
Referenced by DAT_copy(), DAT_fill(), DMA_config(), and DMA_getConfig().
| #define CSL_DMA_SARAM_END_ADDR (0x27FFF) |
SARAM ending address
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_SARAM_START_ADDR (0x08000) |
SARAM starting address
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_UINT16_MASK (0xFFFF) |
mask value for 16 bit variable
Referenced by DAT_copy(), DAT_fill(), and DMA_config().
| #define CSL_DMA_UINT16_NUMBER_BITS (0x0010) |
no of bits in a Uint16 datatype variable
Referenced by DAT_copy(), DAT_fill(), DMA_config(), and DMA_getConfig().
1.7.4