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Defines | |
| #define | CSL_DARAM_BANK_COUNT (8) |
| #define | CSL_SARAM_BANK_COUNT (32) |
| #define | CSL_DARAM_BANK_NUM_MAX (CSL_DARAM_BANK_COUNT - 1) |
| #define | CSL_SARAM_BANK_NUM_MAX (CSL_SARAM_BANK_COUNT - 1) |
| #define | CSL_MEM_DARAM_BANK0 (0) |
| #define | CSL_MEM_DARAM_BANK7 (7u) |
| #define | CSL_MEM_SARAM_BANK0 (0) |
| #define | CSL_MEM_SARAM_BANK8 (8u) |
| #define | CSL_MEM_SARAM_BANK16 (16u) |
| #define | CSL_MEM_SARAM_BANK24 (24u) |
| #define | CSL_MEM_SARAM_BANK31 (31u) |
| #define | CSL_MEM_ENABLE_ALL_SLEEP (0xAAAAu) |
| #define | CSL_MEM_DISABLE_ALL_SLEEP (0xFFFFu) |
| #define | CSL_MEM_ENABLE_BANK_SLEEP (0x0002) |
| #define | CSL_MEM_DISABLE_BANK_SLEEP (0x0003) |
| #define | CSL_MEM_SLEEPMODE_BIT_MASK (0x0003) |
| #define | CSL_MEM_DARAM_BANKMASK (0xFFu) |
| #define | CSL_MEM_MAKE_BANKMASK(bankNumber) ((Uint32)1 << bankNumber) |
| #define CSL_DARAM_BANK_COUNT (8) |
Number of banks in DARAM memory
Referenced by MEM_disablePartialRetentionMode(), and MEM_enablePartialRetentionMode().
| #define CSL_DARAM_BANK_NUM_MAX (CSL_DARAM_BANK_COUNT - 1) |
Maximum allowed bank number for DARAM memory
Referenced by MEM_disablePartialRetentionMode(), and MEM_enablePartialRetentionMode().
| #define CSL_MEM_DARAM_BANK0 (0) |
Macro to indicate DARAM Bank 0
| #define CSL_MEM_DARAM_BANK7 (7u) |
Macro to indicate DARAM Bank 7
| #define CSL_MEM_DARAM_BANKMASK (0xFFu) |
Maximum value of bank mask for DARAM memory
Referenced by MEM_disablePartialRetentionMode(), and MEM_enablePartialRetentionMode().
| #define CSL_MEM_DISABLE_ALL_SLEEP (0xFFFFu) |
Macro value to disable to memory retention mode for all the blocks
Referenced by MEM_disableRetentionMode().
| #define CSL_MEM_DISABLE_BANK_SLEEP (0x0003) |
Macro value to disable to memory retention mode for single bank
Referenced by MEM_disablePartialRetentionMode().
| #define CSL_MEM_ENABLE_ALL_SLEEP (0xAAAAu) |
Macro value to enable to memory retention mode for all the blocks
Referenced by MEM_enableRetentionMode().
| #define CSL_MEM_ENABLE_BANK_SLEEP (0x0002) |
Macro value to enable to memory retention mode for single bank
Referenced by MEM_enablePartialRetentionMode().
| #define CSL_MEM_MAKE_BANKMASK | ( | bankNumber | ) | ((Uint32)1 << bankNumber) |
Macro to make the bank mask based on the bank number
| #define CSL_MEM_SARAM_BANK0 (0) |
Macro to indicate SARAM Bank 0
| #define CSL_MEM_SARAM_BANK16 (16u) |
Macro to indicate SARAM Bank 16
| #define CSL_MEM_SARAM_BANK24 (24u) |
Macro to indicate SARAM Bank 24
| #define CSL_MEM_SARAM_BANK31 (31u) |
Macro to indicate SARAM Bank 31
| #define CSL_MEM_SARAM_BANK8 (8u) |
Macro to indicate SARAM Bank 8
| #define CSL_MEM_SLEEPMODE_BIT_MASK (0x0003) |
Mask for sleep mode control register bits of a memory bank
Referenced by MEM_enablePartialRetentionMode().
| #define CSL_SARAM_BANK_COUNT (32) |
Number of banks in SARAM memory
Referenced by MEM_disablePartialRetentionMode(), and MEM_enablePartialRetentionMode().
| #define CSL_SARAM_BANK_NUM_MAX (CSL_SARAM_BANK_COUNT - 1) |
Maximum allowed bank number for SARAM memory
Referenced by MEM_disablePartialRetentionMode(), and MEM_enablePartialRetentionMode().
1.7.4