Defines
NAND Symbols Defined
NAND

Defines

#define CSL_NAND_SB_CMD_LO_PAGE   (0x00u)
 NAND device standard commands.
#define CSL_NAND_SB_CMD_HI_PAGE   (0x01u)
#define CSL_NAND_SB_CMD_SPARE_AREA   (0x50u)
#define CSL_NAND_CMD_DEVID   (0x90u)
#define CSL_NAND_CMD_DEVADD   (0x00u)
#define CSL_NAND_CMD_RESET   (0xFFu)
#define CSL_NAND_CMD_SET   (0x00u)
#define CSL_NAND_CMD_PGRM_START   (0x80u)
#define CSL_NAND_CMD_PGRM_END   (0x10u)
#define CSL_NAND_CMD_BLK_ERASE_CMD1   (0x60u)
#define CSL_NAND_CMD_BLK_ERASE_CMD2   (0xD0u)
#define CSL_NAND_CMD_READY   (0x40u)
#define CSL_NAND_CMD_STATUS   (0x70u)
#define CSL_NAND_CMD_READ_START   (0x00u)
#define CSL_NAND_CMD_READ_END   (0x30u)
#define CSL_NAND_BB_CMD_RANDOM_PGRM_START   (0x85u)
 Big block NAND extra commands.
#define CSL_NAND_BB_CMD_RANDOM_READ_START   (0x05u)
#define CSL_NAND_BB_CMD_RANDOM_READ_END   (0xE0u)
#define CSL_NAND_BB_CMD_COPY_BACK_READ   (0x35u)
#define CSL_NAND_FLAG_FIRSTBITPOS   (0u)
#define CSL_NAND_MEDIA_WRITE_PROTECTED   ((1L) << (CSL_NAND_FLAG_FIRSTBITPOS + 0))
#define CSL_NAND_FLAG_LASTBITPOS   (1u)
#define CSL_NAND_BB_CMD_PGRM_STATUS_PASS   (0x0000)
 NAND Status Bit definitions - Big Block.
#define CSL_NAND_BB_CMD_CACHE_PGRM_READY   (0x0020u)
#define CSL_NAND_BB_CMD_CMD_STATUS_READY   (0x0040u)
#define CSL_NAND_BB_CMD_WP_STATUS_OPEN   (0x0080u)
#define CSL_NAND_BB_CMD_STATUS_READY
#define CSL_NAND_BB_CMD_STATUS_SUCCESS   (CSL_NAND_BB_CMD_STATUS_READY)
#define CSL_NAND_SB_CMD_PGRM_STATUS_PASS   (0x0000)
 NAND Status Bit definitions - Small Block.
#define CSL_NAND_SB_CMD_CMD_STATUS_READY   (0x0040u)
#define CSL_NAND_SB_CMD_WP_STATUS_OPEN   (0x0080u)
#define CSL_NAND_SB_CMD_STATUS_READY
#define CSL_NAND_SB_CMD_STATUS_SUCCESS   (CSL_NAND_SB_CMD_STATUS_READY)
#define CSL_NAND_PAGE_SIZE_MASK   (0x03u)
 Extended ID masks.
#define CSL_NAND_BLOCK_SIZE_MASK   (0x30u)
#define CSL_NAND_RED_AREA_SIZE_MASK   (0x04u)
#define CSL_NAND_ORGANIZATION_MASK   (0x40u)
#define CSL_NAND_ECC_BANK1_ENABLE   (0x100u)
 ECC options for NAND Banks.
#define CSL_NAND_ECC_BANK2_ENABLE   (0x200u)
#define CSL_NAND_ECC_BANK3_ENABLE   (0x400u)
#define CSL_NAND_ECC_BANK4_ENABLE   (0x800u)
#define CSL_NAND_BB_CACHE_PROG   (0x01u)
 Big block NAND extra features.
#define CSL_NAND_BB_COPY_BACK   (0x02u)
#define CSL_NAND_BB_RANDOM_PAGE_READ   (0x04u)
#define CSL_NAND_BB_RANDOM_PAGE_WRITE   (0x08u)
#define CSL_NAND_BB_OPTIONS
#define CSL_NAND_BB_MLC_NAND   0x10
#define CSL_NAND_MAX_TIMEOUT   (0x7FFFFFFFu)
#define CSL_NAND_DELAY   (100)
#define CSL_NAND_READ_STATUS_TIMEOUT   (100000u)
#define CSL_NAND_BB_PAGE_SIZE   (2048u)
#define CSL_NAND_RESET_COUNT_VAL   (0x20)
#define CSL_NAND_INV_INTR_NUM   (0xFFFF)
#define CSL_NAND_ASYNCWAITCFG_WAITPOL_DEFAULT   (0x00)
 Default values of NAND Async Wait Config structure.
#define CSL_NAND_ASYNCWAITCFG_NANDPORT_DEFAULT   (0x00)
#define CSL_NAND_ASYNCWAITCFG_WAITCYCLE_DEFAULT   (0x80)
#define CSL_NAND_ASYNCCFG_SELECTSTROBE_DEFAULT   (0x00)
 Default values of NAND Async Config structure.
#define CSL_NAND_ASYNCCFG_WEMODE_DEFAULT   (0x00)
#define CSL_NAND_ASYNCCFG_WSETUP_DEFAULT   (0x0F)
#define CSL_NAND_ASYNCCFG_WSTROBE_DEFAULT   (0x1F)
#define CSL_NAND_ASYNCCFG_WHOLD_DEFAULT   (0x07)
#define CSL_NAND_ASYNCCFG_RSETUP_DEFAULT   (0x0F)
#define CSL_NAND_ASYNCCFG_RSTROBE_DEFAULT   (0x3F)
#define CSL_NAND_ASYNCCFG_RHOLD_DEFAULT   (0x07)
#define CSL_NAND_ASYNCCFG_TAROUND_DEFAULT   (0x03)
#define CSL_NAND_ASYNCCFG_ASIZE_DEFAULT   (0x00)
#define CSL_EMIF_NCS2ECC1_LSB   (0)
 EMIF CSL Bit position macros.
#define CSL_EMIF_NCS2ECC1_MSB   (11)
#define CSL_EMIF_NCS2ECC2_LSB   (0)
#define CSL_EMIF_NCS2ECC2_MSB   (11)
#define CSL_EMIF_NCS3ECC1_LSB   (0)
#define CSL_EMIF_NCS3ECC1_MSB   (11)
#define CSL_EMIF_NCS3ECC2_LSB   (0)
#define CSL_EMIF_NCS3ECC2_MSB   (11)
#define CSL_EMIF_NCS4ECC1_LSB   (0)
#define CSL_EMIF_NCS4ECC1_MSB   (11)
#define CSL_EMIF_NCS4ECC2_LSB   (0)
#define CSL_EMIF_NCS4ECC2_MSB   (11)
#define CSL_EMIF_NCS5ECC1_LSB   (0)
#define CSL_EMIF_NCS5ECC1_MSB   (11)
#define CSL_EMIF_NCS5ECC2_LSB   (0)
#define CSL_EMIF_NCS5ECC2_MSB   (11)
#define CSL_NAND_WORD_ACCESS   (0)
#define CSL_NAND_HIGHBYTE_ACCESS   (1)
#define CSL_NAND_LOWBYTE_ACCESS   (2)
#define CSL_NAND_CHANGE_ACCESSTYPE(byte)   CSL_FINS(CSL_SYSCTRL_REGS->ESCR, SYS_ESCR_BYTEMODE, byte);
 NAND module specific errors.
#define CSL_NAND_E_TIMEOUT   (CSL_ENAND_FIRST - 0)
#define CSL_NAND_WRITEWORD(hNand, data)
#define CSL_NAND_READWORD(hNand, data)
#define CSL_NAND_WRITEBYTE(hNand,data)
#define CSL_NAND_READBYTE(hNand,addr)
#define CSL_NANDGETCOMMAND(hNand, cmd)   cmd = (*(CSL_VUint16*)hNand->bank.CExCLE); \
#define CSL_NANDGETADDRESS(hNand, addr)   addr = *(CSL_VUint16*)hNand->bank.CExALE; \
#define CSL_NANDGETWAITCFG(hNand, value)   value = (Uint32)((hNand->regs->AWCCR1) | (hNand->regs->AWCCR2 << 16));
#define CSL_NANDGETCS2ASYNCCFG(hNand, value)
#define CSL_NANDGETCS3ASYNCCFG(hNand, value)
#define CSL_NANDGETCS4ASYNC3CFG(hNand, value)
#define CSL_NANDGETCS5ASYNC4CFG(hNand, value)
#define CSL_NANDGETCTRL(hNand, value)   value = (Uint16)(CSL_FEXTR(hNand->regs->NANDFCR, 13, 0));
#define CSL_NANDGETINTRAW(hNand, intrStatus)   intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIRR, 5, 0));
#define CSL_NANDGETINTMASK(hNand, intrStatus)   intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMR, 5, 0));
#define CSL_NANDGETINTMASKSET(hNand, intrStatus)   intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMSR, 5, 0));
#define CSL_NANDGETINTMASKCLEAR(hNand, intrStatus)   intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMCR, 5, 0));

Define Documentation

#define CSL_EMIF_NCS2ECC1_LSB   (0)

EMIF CSL Bit position macros.

LSB bit position for CS2 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS2ECC1_MSB   (11)

MSB bit position for CS2 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS2ECC2_LSB   (0)

LSB bit position for CS2 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS2ECC2_MSB   (11)

MSB bit position for CS2 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS3ECC1_LSB   (0)

LSB bit position for CS3 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS3ECC1_MSB   (11)

MSB bit position for CS3 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS3ECC2_LSB   (0)

LSB bit position for CS3 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS3ECC2_MSB   (11)

MSB bit position for CS3 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS4ECC1_LSB   (0)

LSB bit position for CS4 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS4ECC1_MSB   (11)

MSB bit position for CS4 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS4ECC2_LSB   (0)

LSB bit position for CS4 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS4ECC2_MSB   (11)

MSB bit position for CS4 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS5ECC1_LSB   (0)

LSB bit position for CS5 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS5ECC1_MSB   (11)

MSB bit position for CS5 ECC1 register

Referenced by NAND_disableHwECC(), and NAND_readECC().

#define CSL_EMIF_NCS5ECC2_LSB   (0)

LSB bit position for CS5 ECC2 register

Referenced by NAND_readECC().

#define CSL_EMIF_NCS5ECC2_MSB   (11)

MSB bit position for CS5 ECC2 register

Referenced by NAND_readECC().

#define CSL_NAND_ASYNCCFG_ASIZE_DEFAULT   (0x00)

Default value for bus width

#define CSL_NAND_ASYNCCFG_RHOLD_DEFAULT   (0x07)

Default value for read hold cycles

#define CSL_NAND_ASYNCCFG_RSETUP_DEFAULT   (0x0F)

Default value for read setup cycles

#define CSL_NAND_ASYNCCFG_RSTROBE_DEFAULT   (0x3F)

Default value for read strobe cycles

#define CSL_NAND_ASYNCCFG_SELECTSTROBE_DEFAULT   (0x00)

Default values of NAND Async Config structure.

Default value for strobe mode select bit

#define CSL_NAND_ASYNCCFG_TAROUND_DEFAULT   (0x03)

Default value for turn around cycles

#define CSL_NAND_ASYNCCFG_WEMODE_DEFAULT   (0x00)

Default value for extended wait mode bit

#define CSL_NAND_ASYNCCFG_WHOLD_DEFAULT   (0x07)

Default value for write hold cycles

#define CSL_NAND_ASYNCCFG_WSETUP_DEFAULT   (0x0F)

Default value for write setup cycles

#define CSL_NAND_ASYNCCFG_WSTROBE_DEFAULT   (0x1F)

Default value for write strobe cycles

#define CSL_NAND_ASYNCWAITCFG_NANDPORT_DEFAULT   (0x00)

Default value for Nand port

#define CSL_NAND_ASYNCWAITCFG_WAITCYCLE_DEFAULT   (0x80)

Default value maximum exteneded wait cycles

#define CSL_NAND_ASYNCWAITCFG_WAITPOL_DEFAULT   (0x00)

Default values of NAND Async Wait Config structure.

Default value for wait polarity

#define CSL_NAND_BB_CACHE_PROG   (0x01u)

Big block NAND extra features.

Big-Block NAND has cache programming command/feature

Referenced by NAND_hasCacheProg().

#define CSL_NAND_BB_CMD_CACHE_PGRM_READY   (0x0020u)

NAND Ready for command after a cache operation

#define CSL_NAND_BB_CMD_CMD_STATUS_READY   (0x0040u)

NAND Ready for commands after an operation

#define CSL_NAND_BB_CMD_COPY_BACK_READ   (0x35u)

Command to perform a Copy-back read (Big block only command)

#define CSL_NAND_BB_CMD_PGRM_STATUS_PASS   (0x0000)

NAND Status Bit definitions - Big Block.

Program/erase operation passed

#define CSL_NAND_BB_CMD_RANDOM_PGRM_START   (0x85u)

Big block NAND extra commands.

Command to perform a random data input (Big block only command)

#define CSL_NAND_BB_CMD_RANDOM_READ_END   (0xE0u)

Command to end a random data output (Big block only command)

#define CSL_NAND_BB_CMD_RANDOM_READ_START   (0x05u)

Command to start a random data output (Big block only command)

#define CSL_NAND_BB_CMD_STATUS_READY
Value:
(CSL_NAND_BB_CMD_CMD_STATUS_READY | \
                                         CSL_NAND_BB_CMD_PGRM_STATUS_PASS)

Status check for any Big block NAND operation

#define CSL_NAND_BB_CMD_STATUS_SUCCESS   (CSL_NAND_BB_CMD_STATUS_READY)

BIg block nand command status success

Referenced by NAND_isStatusWriteProtected().

#define CSL_NAND_BB_CMD_WP_STATUS_OPEN   (0x0080u)

NAND device not write protected status

Referenced by NAND_isStatusWriteProtected().

#define CSL_NAND_BB_COPY_BACK   (0x02u)

Big-Block NAND has copy-back command/feature

Referenced by NAND_hasCopyBack().

#define CSL_NAND_BB_MLC_NAND   0x10

NAND options for Bigblock MLC NAND flash

#define CSL_NAND_BB_OPTIONS
Value:
(CSL_NAND_BB_CACHE_PROG       |\
                                               CSL_NAND_BB_COPY_BACK        |\
                                               CSL_NAND_BB_RANDOM_PAGE_READ |\
                                               CSL_NAND_BB_RANDOM_PAGE_WRITE )

Extra commands/options/features only for Big Block NAND devices

#define CSL_NAND_BB_PAGE_SIZE   (2048u)

Big block NAND page size

#define CSL_NAND_BB_RANDOM_PAGE_READ   (0x04u)

Big-Block NAND has random read/random output command/feature

Referenced by NAND_hasRandomRead().

#define CSL_NAND_BB_RANDOM_PAGE_WRITE   (0x08u)

Big-Block NAND has random write/random input command/feature

Referenced by NAND_hasRandomWrite().

#define CSL_NAND_BLOCK_SIZE_MASK   (0x30u)

Block size mask of extended ID

#define CSL_NAND_CHANGE_ACCESSTYPE (   byte)    CSL_FINS(CSL_SYSCTRL_REGS->ESCR, SYS_ESCR_BYTEMODE, byte);

NAND module specific errors.

Macro to enable disable byte access byte = 0 - Enables word access byte = 1 - Enables High byte access byte = 2 - Enables Low byte access

#define CSL_NAND_CMD_BLK_ERASE_CMD1   (0x60u)

Command to erase block

#define CSL_NAND_CMD_BLK_ERASE_CMD2   (0xD0u)

Command to erase block

#define CSL_NAND_CMD_DEVADD   (0x00u)

Command to access device address

#define CSL_NAND_CMD_DEVID   (0x90u)

Command to access device Id

#define CSL_NAND_CMD_PGRM_END   (0x10u)

Command to stop programming NAND

#define CSL_NAND_CMD_PGRM_START   (0x80u)

Command to start programming NAND

#define CSL_NAND_CMD_READ_END   (0x30u)

Command to read the end of NAND

#define CSL_NAND_CMD_READ_START   (0x00u)

Command to read the start of NAND

#define CSL_NAND_CMD_READY   (0x40u)

Command to put NAND in ready state

#define CSL_NAND_CMD_RESET   (0xFFu)

Command to perform a reset

#define CSL_NAND_CMD_SET   (0x00u)

Command to perform a set

#define CSL_NAND_CMD_STATUS   (0x70u)

Command to get the status of NAND

Referenced by NAND_isStatusWriteProtected().

#define CSL_NAND_DELAY   (100)

NAND general delay

Referenced by NAND_init(), and NAND_isStatusWriteProtected().

#define CSL_NAND_E_TIMEOUT   (CSL_ENAND_FIRST - 0)

NAND Time out Error

Referenced by NAND_checkCommandStatus().

#define CSL_NAND_ECC_BANK1_ENABLE   (0x100u)

ECC options for NAND Banks.

Enable ECC calculation for bank 1 - maps to CS2ECC

#define CSL_NAND_ECC_BANK2_ENABLE   (0x200u)

Enable ECC calculation for bank 2 - maps to CS3ECC

#define CSL_NAND_ECC_BANK3_ENABLE   (0x400u)

Enable ECC calculation for bank 3 - maps to CS4ECC

#define CSL_NAND_ECC_BANK4_ENABLE   (0x800u)

Enable ECC calculation for bank 4 - maps to CS5ECC

#define CSL_NAND_FLAG_FIRSTBITPOS   (0u)

First bit-position for NAND device flags

#define CSL_NAND_FLAG_LASTBITPOS   (1u)

Last bit-position for NAND device flags

#define CSL_NAND_HIGHBYTE_ACCESS   (1)

Enables NAND Low Byte Acces

#define CSL_NAND_INV_INTR_NUM   (0xFFFF)

NAND invalid interrupt number

Referenced by NAND_getIntrNum().

#define CSL_NAND_LOWBYTE_ACCESS   (2)

Enables NAND High Byte Acces

#define CSL_NAND_MAX_TIMEOUT   (0x7FFFFFFFu)

Maximum time-out for NAND

Referenced by NAND_checkCommandStatus().

#define CSL_NAND_MEDIA_WRITE_PROTECTED   ((1L) << (CSL_NAND_FLAG_FIRSTBITPOS + 0))

Write protected bit-flag

#define CSL_NAND_ORGANIZATION_MASK   (0x40u)

Organization (8/16 bit) mask of extended ID

#define CSL_NAND_PAGE_SIZE_MASK   (0x03u)

Extended ID masks.

Page size mask of extended ID

#define CSL_NAND_READ_STATUS_TIMEOUT   (100000u)

NAND read status time out

Referenced by NAND_isStatusWriteProtected().

#define CSL_NAND_READBYTE (   hNand,
  addr 
)
Value:
if(hNand->nandWidth == CSL_NAND_8_BIT)                          \
        {                                                               \
            *addr  = (*(CSL_VUint8*)hNand->bank.CExDATA);               \
        }                                                               \
        else                                                            \
        {                                                               \
            *addr = (*(CSL_VUint16*)hNand->bank.CExDATA);               \
        }

Macro for reading a byte from nand device

#define CSL_NAND_READWORD (   hNand,
  data 
)
Value:
if(hNand->nandWidth == CSL_NAND_8_BIT)                            \
        {                                                                 \
            data  = ((*(CSL_VUint8*)hNand->bank.CExDATA) & 0xFFu);        \
            data  = ((*(CSL_VUint8*)hNand->bank.CExDATA) | (data << 8));  \
        }                                                                 \
        else                                                              \
        {                                                                 \
            data = (*(CSL_VUint16*)hNand->bank.CExDATA);                  \
        }

Macro for reading a word from nand device

Referenced by NAND_isStatusWriteProtected(), and NAND_readNBytes().

#define CSL_NAND_RED_AREA_SIZE_MASK   (0x04u)

Redundant area size mask of extended ID

#define CSL_NAND_RESET_COUNT_VAL   (0x20)

NAND reset counter register value

Referenced by NAND_init().

#define CSL_NAND_SB_CMD_CMD_STATUS_READY   (0x0040u)

NAND Ready for commands after an operation

#define CSL_NAND_SB_CMD_HI_PAGE   (0x01u)

Command to access high page

#define CSL_NAND_SB_CMD_LO_PAGE   (0x00u)

NAND device standard commands.

Command to access low page

#define CSL_NAND_SB_CMD_PGRM_STATUS_PASS   (0x0000)

NAND Status Bit definitions - Small Block.

Program/erase operation passed

#define CSL_NAND_SB_CMD_SPARE_AREA   (0x50u)

Command to access spare area - not found in Big Block NANDs

#define CSL_NAND_SB_CMD_STATUS_READY
Value:
(CSL_NAND_SB_CMD_CMD_STATUS_READY | \
                                         CSL_NAND_SB_CMD_PGRM_STATUS_PASS)

Status check for any Small block NAND operation

#define CSL_NAND_SB_CMD_STATUS_SUCCESS   (CSL_NAND_SB_CMD_STATUS_READY)

Small block nand command status success

Referenced by NAND_isStatusWriteProtected().

#define CSL_NAND_SB_CMD_WP_STATUS_OPEN   (0x0080u)

Not write protected

#define CSL_NAND_WORD_ACCESS   (0)

Enables NAND Word Acces

#define CSL_NAND_WRITEBYTE (   hNand,
  data 
)
Value:
if(hNand->nandWidth == CSL_NAND_8_BIT)                          \
        {                                                               \
            *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)(data);          \
        }                                                               \
        else                                                            \
        {                                                               \
            *(CSL_VUint16*)hNand->bank.CExDATA = (Uint16)data;          \
        }

Macro for writing a byte to nand device

Referenced by NAND_writeNBytes().

#define CSL_NAND_WRITEWORD (   hNand,
  data 
)
Value:
if(hNand->nandWidth == CSL_NAND_8_BIT)                               \
        {                                                                    \
            *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)((data >> 8) & 0xFF); \
            *(CSL_VUint8*)hNand->bank.CExDATA = (Uint8)(data & 0xFFu);       \
        }                                                                    \
        else                                                                 \
        {                                                                    \
            *(CSL_VUint16*)hNand->bank.CExDATA = (Uint16)data;               \
        }

Macro for writing a word to nand device

Referenced by NAND_writeNBytes().

#define CSL_NANDGETADDRESS (   hNand,
  addr 
)    addr = *(CSL_VUint16*)hNand->bank.CExALE; \

Macro to read address from command latch address

#define CSL_NANDGETCOMMAND (   hNand,
  cmd 
)    cmd = (*(CSL_VUint16*)hNand->bank.CExCLE); \

Macro to read a command from command latch address

#define CSL_NANDGETCS2ASYNCCFG (   hNand,
  value 
)
Value:
value = (Uint32)(hNand->regs->ACS2CR1 |                        \
                          (hNand->regs->ACS2CR2 << 16));                \

Macro to read nand async 1 config register

#define CSL_NANDGETCS3ASYNCCFG (   hNand,
  value 
)
Value:
value = (Uint32)(hNand->regs->ACS3CR1 |                        \
                          (hNand->regs->ACS3CR2 << 16));                \

Macro to read nand async 2 config register

#define CSL_NANDGETCS4ASYNC3CFG (   hNand,
  value 
)
Value:
value = (Uint32)(hNand->regs->ACS4CR1 |                        \
                          (hNand->regs->ACS4CR2 << 16));                \

Macro to read nand async 3 config register

#define CSL_NANDGETCS5ASYNC4CFG (   hNand,
  value 
)
Value:
value = (Uint32)(hNand->regs->ACS5CR1 |                        \
                          (hNand->regs->ACS5CR2 << 16));                \

Macro to read nand async 4 config register

#define CSL_NANDGETCTRL (   hNand,
  value 
)    value = (Uint16)(CSL_FEXTR(hNand->regs->NANDFCR, 13, 0));

Macro to read nand control register

#define CSL_NANDGETINTMASK (   hNand,
  intrStatus 
)    intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMR, 5, 0));

Macro to read nand interrupt mask register

#define CSL_NANDGETINTMASKCLEAR (   hNand,
  intrStatus 
)    intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMCR, 5, 0));

Macro to read nand interrupt mask clear register

#define CSL_NANDGETINTMASKSET (   hNand,
  intrStatus 
)    intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIMSR, 5, 0));

Macro to read nand interrupt mask set register

#define CSL_NANDGETINTRAW (   hNand,
  intrStatus 
)    intrStatus = (Uint16)(CSL_FEXTR(hNand->regs->EIRR, 5, 0));

Macro to read nand interrupt raw register

#define CSL_NANDGETWAITCFG (   hNand,
  value 
)    value = (Uint32)((hNand->regs->AWCCR1) | (hNand->regs->AWCCR2 << 16));

Macro to read nand async wait config register

Generated on Thu Jun 23 2011 15:25:55 for C55XX CSL Version 2.50 by  doxygen 1.7.4