|
|
| #define CSL_UART_AFE (0x01u) |
This Macro is used to set the value of 'afeEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_BAUD_MULTIPLIER (16u) |
Each tranmitted/received bit lasts for 16 clk cycles,so baud rate multiplier is 16
| #define CSL_UART_CLK_DIVIDER | ( | baud | ) | ( Uint32 ) ( (Uint32)CSL_UART_BAUD_MULTIPLIER * (Uint32) ( baud) ) |
Macro to calculate the clock divider for the UART
Referenced by UART_setup(), and UART_setupBaudRate().
| #define CSL_UART_DISABLE_PARITY (0x00u) |
ST EPS PEN x x 0 Parity disabled: No PARITY bit is transmitted or checked 0 0 1 Odd parity selected: Odd number of logic 1s 0 1 1 Even parity selected: Even number of logic 1s 1 0 1 Stick parity selected with PARITY bit transmitted and checked as set 1 1 1 Stick parity selected with PARITY bit transmitted and checked as cleareddisable parity checking
Referenced by UART_setup().
| #define CSL_UART_EVEN_PARITY (0x02u) |
SP - 0, EPS-1, PEN-1 Even parity selected
Referenced by UART_setup().
| #define CSL_UART_FIFO_DISABLE CSL_FMKT(UART_FCR_FIFOEN,DISABLE) |
UART FIFO disabled
| #define CSL_UART_FIFO_DMA1_DISABLE_TRIG01 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,DISABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR1)
DMA MODE 1 disabled and trigger level 01
| #define CSL_UART_FIFO_DMA1_DISABLE_TRIG04 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,DISABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR4)
DMA MODE 1 disabled and trigger level 04
| #define CSL_UART_FIFO_DMA1_DISABLE_TRIG08 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,DISABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR8)
DMA MODE 1 disabled and trigger level 08
| #define CSL_UART_FIFO_DMA1_DISABLE_TRIG14 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,DISABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR14)
DMA MODE 1 disabled and trigger level 14
| #define CSL_UART_FIFO_DMA1_ENABLE_TRIG01 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,ENABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR1)
DMA MODE 1 enabled and trigger level 01
| #define CSL_UART_FIFO_DMA1_ENABLE_TRIG04 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,ENABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR4)
DMA MODE 1 enabled and trigger level 04
| #define CSL_UART_FIFO_DMA1_ENABLE_TRIG08 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,ENABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR8)
DMA MODE 1 enabled and trigger level 08
| #define CSL_UART_FIFO_DMA1_ENABLE_TRIG14 |
CSL_FMKT(UART_FCR_FIFOEN,ENABLE)|\
CSL_FMKT(UART_FCR_RXCLR,CLR)|CSL_FMKT(UART_FCR_TXCLR,CLR)|\
CSL_FMKT(UART_FCR_DMAMODE1,ENABLE)|CSL_FMKT(UART_FCR_RXFIFTL,CHAR14)
DMA MODE 1 enabled and trigger level 14
| #define CSL_UART_LOOPBACK (0x01u) |
This Macro is used to set the value of 'loopBackEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_MARK_PARITY (0x03u) |
SP - 1, EPS-0, PEN-1 Stick parity selected with parity bit transmitted and checked as set
Referenced by UART_setup().
| #define CSL_UART_NO_AFE (0x00u) |
This Macro is used to set the value of 'afeEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_NO_LOOPBACK (0x00u) |
This Macro is used to set the value of 'loopBackEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_NO_RTS (0x00u) |
This Macro is used to set the value of ' rtsEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_ODD_PARITY (0x01u) |
SP - 0, EPS-0, PEN-1 odd parity selected
Referenced by UART_setup().
| #define CSL_UART_RTS (0x01u) |
This Macro is used to set the value of ' rtsEnable' memeber of CSL_UartSetup strcuture.
| #define CSL_UART_SPACE_PARITY (0x04u) |
SP - 1, EPS-1, PEN-1 Stick parity selected with parity bit transmitted and checked as clear
Referenced by UART_setup().
| #define CSL_UART_WORD5 0x05 |
UART serial character word length 5
Referenced by UART_setup().
| #define CSL_UART_WORD6 0x06 |
UART serial character word length 6
Referenced by UART_setup().
| #define CSL_UART_WORD7 0x07 |
UART serial character word length 7
Referenced by UART_setup().
| #define CSL_UART_WORD8 0x08 |
UART serial character word length 8
Referenced by UART_setup().
| #define IIR FCR |
IIR & FCR have same offset
| #define RBR THR |
global variable RBR & THR have same offset
| #define UART_EVT_CTOI_IID 0x06 |
Character timeout interrupt identification value
Referenced by UART_setCallback().
| #define UART_EVT_LSI_IID 0x03 |
Receiver line status interrupt identification value
Referenced by UART_setCallback().
| #define UART_EVT_RBI_IID 0x02 |
Received data available interrupt identification value
Referenced by UART_setCallback().
| #define UART_EVT_TBEI_IID 0x01 |
Transmitter holding register empty interrupt identification value
Referenced by UART_setCallback().
1.7.4