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Defines | |
| #define | CSl_WDT_WDKCKLK_FIRST_SEQ 0x5555 |
| #define | CSl_WDT_WDKCKLK_SECOND_SEQ 0xAAAA |
| #define | CSl_WDT_WDSVLR_FIRST_SEQ 0x6666 |
| #define | CSl_WDT_WDSVLR_SECOND_SEQ 0xBBBB |
| #define | CSl_WDT_WDENLOK_FIRST_SEQ 0x7777 |
| #define | CSl_WDT_WDENLOK_SECOND_SEQ 0xCCCC |
| #define | CSl_WDT_WDENLOK_THIRD_SEQ 0xDDDD |
| #define | CSl_WDT_WDPSLR_FIRST_SEQ 0x5A5A |
| #define | CSl_WDT_WDPSLR_SECOND_SEQ 0xA5A5 |
| #define | CSl_WDT_WDKICK_RESET 0x0001 |
| #define CSl_WDT_WDENLOK_FIRST_SEQ 0x7777 |
Disable Lock register First unlock sequence
Referenced by WDTIM_start(), and WDTIM_stop().
| #define CSl_WDT_WDENLOK_SECOND_SEQ 0xCCCC |
Disable Lock register Second unlock sequence
Referenced by WDTIM_start(), and WDTIM_stop().
| #define CSl_WDT_WDENLOK_THIRD_SEQ 0xDDDD |
Disable Lock register Third unlock sequence
Referenced by WDTIM_start(), and WDTIM_stop().
| #define CSl_WDT_WDKCKLK_FIRST_SEQ 0x5555 |
Kick Lock register First unlock sequence
Referenced by WDTIM_service().
| #define CSl_WDT_WDKCKLK_SECOND_SEQ 0xAAAA |
Kick Lock register Second unlock sequence
Referenced by WDTIM_service().
| #define CSl_WDT_WDKICK_RESET 0x0001 |
Kick register Reset bit for service
Referenced by WDTIM_service().
| #define CSl_WDT_WDPSLR_FIRST_SEQ 0x5A5A |
Prescale Lock register First unlock sequence
Referenced by WDTIM_config().
| #define CSl_WDT_WDPSLR_SECOND_SEQ 0xA5A5 |
Prescale Lock register Second unlock sequence
Referenced by WDTIM_config().
| #define CSl_WDT_WDSVLR_FIRST_SEQ 0x6666 |
Counter Lock register First unlock sequence
Referenced by WDTIM_config().
| #define CSl_WDT_WDSVLR_SECOND_SEQ 0xBBBB |
Counter Lock register Second unlock sequence
Referenced by WDTIM_config().
1.7.4