PLL EXAMPLE

TEST DESCRIPTION:

This test code verifies the functionality of CSL PLL module. PLL module on the C5505/C5515 DSP is used to generate clock for CPU and peripherals. A 32KHz input clock is supplied to the PLL using which different system clock values are generated. Different system clock values are generated by configuring the PLL to different divider values.

During the test PLL module will be configured to the 60MHz clock frequency using PLL_config() API. Configured values are read back and verified using PLL_getConfig() APIs. All the values should match the configured values except the test lock mon value which will reflect on the registers only after the PLL is up. Values read from the PLL are displayed on the CCS "stdout" window. Manual inspection is required to verify the test success.

C5515 DSP PLL register bit fileds are little different than that of C5505 DSP. Use the 'PLL_Config' values defined 12.288MHz - 120MHz to verify PLL configuration.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5505/C5515 EVM)
• Open the project "CSL_PLL_Example.pjt" and build it
• Load the program on to the target
• Run the program and observe the test result
• Repeat the test in Release mode

TEST RESULT:

• All the CSL APIs should return success
• Configuration values read from the PLL should match with the actual configured values except the test lock mon value.