MEMORY EXAMPLE1 - DARAM RETENTION MODE TEST

TEST DESCRIPTION:

This test verifies the memory retention mode feature of the C5505/C5515 DARAM. Internal memory of the C5505/C5515 DSP can be placed into a low power memory retention while retaining the content stored in the memory. This low power mode is activated through the Sleep Mode Memory Control. When the memory is placed in this mode, no accesses can occur. When the memory retention mode is enabled, inline diodes will be added to reduce the local power supply to the on-chip RAM.Memory retention mode can be enabled/disabled for the DARAM and SARAM independently.

A data buffer is allocated in the DARAM is initialized with some data. CSL memory module is initialized and memory retention mode for DARAM is enabled using the CSL API MEM_enableRetentionMode(). Memory retention mode will be disabled after few CPU cycles by using the CSL API MEM_disableRetentionMode(). Data in the DARAM buffer is verified after few CPU cycles of delay. Buffer should contain the data with which it was initialized before enabling the memory retention mode. This proves that the data stored in the DARAM is retained when it is placed into memory retention mode and is accessible after disabling the memory retention mode.

NOTE: DURING MEMORY RETENTION MODE TEST FOR DARAM ALL THE PROGRAM SECTIONS SHOULD BE PLACED IN THE SARAM. ACCESSING THE DATA IN THE DARAM BY ANY WAY (CCS WATCH WINDOW, MEMORY WINDOW OR PLACING THE MOUSE POINTER ON THE DARAM DATA BUFFER TO VIEW THE VALUE) AFTER ENABLING THE MEMORY RETENTION MODE WILL CORRUPT ALL THE DATA IN DARAM.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5505/C5515 EVM)
• Open the project "CSL_MEMORY_DARAM_RetentionExample_Out.pjt" and build it
• Load the program on to the target
• Set the PLL frequency to 12.288MHz
• Run the program and observe the test result
• Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
• Repeat the test in Release mode

TEST RESULT:

• All the CSL APIs should return success
• DARAM buffer data verification after disabling the memory retention mode should be successful

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MEMORY EXAMPLE2 - SARAM RETENTION MODE TEST

TEST DESCRIPTION:

This test verifies the memory retention mode feature of the C5505/C5515 SARAM. Internal memory of the C5505/C5515 DSP can be placed into a low power memory retention while retaining the content stored in the memory. This low power mode is activated through the Sleep Mode Memory Control. When the memory is placed in this mode, no accesses can occur. When the memory retention mode is enabled, inline diodes will be added to reduce the local power supply to the on-chip RAM. Memory retention mode can be enabled/disabled for the DARAM and SARAM independently.

A data buffer is allocated in the SARAM is initialized with some data. CSL memory module is initialized and memory retention mode for SARAM is enabled using the CSL API MEM_enableRetentionMode(). Memory retention mode will be disabled after few CPU cycles by using the CSL API MEM_disableRetentionMode(). Data in the SARAM buffer is verified after few CPU cycles of delay. Buffer should contain the data with which it was initialized before enabling the memory retention mode. This proves that the data stored in the SARAM is retained when it is placed into memory retention mode and is accessible after disabling the memory retention mode.

NOTE: DURING MEMORY RETENTION MODE TEST FOR SARAM ALL THE PROGRAM SECTIONS SHOULD BE PLACED IN THE DARAM. ACCESSING THE DATA IN THE SARAM BY ANY WAY (CCS WATCH WINDOW, MEMORY WINDOW OR PLACING THE MOUSE POINTER ON THE SARAM DATA BUFFER TO VIEW THE VALUE) AFTER ENABLING THE MEMORY RETENTION MODE WILL CORRUPT ALL THE DATA IN SARAM.

NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5505/C5515 EVM)
• Open the project "CSL_MEMORY_SARAM_RetentionExample_Out.pjt" and build it
• Load the program on to the target
• Set the PLL frequency to 12.288MHz
• Run the program and observe the test result
• Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
• Repeat the test in Release mode

TEST RESULT:

• All the CSL APIs should return success
• SARAM buffer data verification after disabling the memory retention mode should be successful

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MEMORY EXAMPLE3 - DARAM PARTIAL RETENTION MODE TEST

TEST DESCRIPTION:

This test verifies the partial memory retention mode feature of the C5515 DARAM. Internal memory of the C5515 DSP can be placed into a low power memory retention while retaining the content stored in the memory. This low power mode is activated through the Sleep Mode Memory Control. When the memory is placed in this mode, no accesses can occur. When the memory retention mode is enabled, inline diodes will be added to reduce the local power supply to the on-chip RAM. Partial memory retention mode allows to enable sleep mode for a DARAM bank independent of other DARAM or SARAM memory banks.

During test, a data buffer allocated in the DARAM bank0 is initialized with data. CSL memory module is initialized and partial memory retention mode for DARAM bank 0 is enabled using the CSL API MEM_enablePartialRetentionMode(). Data in other DARAM banks is accessed to demonstrate that enabling partial retention mode for one memory bank will not effect rest of the banks. Memory retention mode will be disabled after few CPU cycles by using the CSL API MEM_disablePartialRetentionMode(). Data in the DARAM0 buffer is verified after few CPU cycles of delay. Buffer should contain the data with which it was initialized before enabling the memory retention mode. This proves that the data stored in the DARAM0 is retained when it is placed into memory retention mode and is accessible after disabling the memory retention mode. Same test is repeated for other DARAM banks.

NOTE: DURING MEMORY RETENTION MODE TEST FOR DARAM ALL THE PROGRAM SECTIONS SHOULD BE PLACED IN THE SARAM. ACCESSING THE DATA IN THE RETENTION MODE ENABLED DARAM BANK BY ANY MEANS(CCS WATCH WINDOW, MEMORY WINDOW OR PLACING THE MOUSE POINTER ON THE DARAM DATA BUFFER TO VIEW THE VALUE) WILL CORRUPT ALL THE DATA IN THAT BANK.

NOTE: PARTIAL MEMORY RETENTION MODE IS SUPPORTED ONLY ON CHIP 5515. THIS TEST IS NOT VALID FOR CHIP 5505. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5515 EVM)
• Open the project "CSL_MEMORY_DARAM_PartialRetentionExample_Out.pjt" and build it
• Load the program on to the target
• Set the PLL frequency to 12.288MHz
• Run the program and observe the test result
• Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
• Repeat the test in Release mode

TEST RESULT:

• All CSL APIs should return success
• DARAM buffer data verification after disabling the memory retention mode should be successful

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MEMORY EXAMPLE4 - SARAM PARTIAL RETENTION MODE TEST

TEST DESCRIPTION:

This test verifies the partial memory retention mode feature of the C5515 SARAM. Internal memory of the C5515 DSP can be placed into a low power memory retention while retaining the content stored in the memory. This low power mode is activated through the Sleep Mode Memory Control. When the memory is placed in this mode, no accesses can occur. When the memory retention mode is enabled, inline diodes will be added to reduce the local power supply to the on-chip RAM. Partial memory retention mode allows to enable sleep mode for a SARAM bank independent of other SARAM or DARAM memory banks.

During test, a data buffer allocated in the SARAM bank0 is initialized with data. CSL memory module is initialized and partial memory retention mode for SARAM bank 0 is enabled using the CSL API MEM_enablePartialRetentionMode(). Data in other SARAM banks is accessed to demonstrate that enabling partial retention mode for one memory bank will not effect rest of the banks. Memory retention mode will be disabled after few CPU cycles by using the CSL API MEM_disablePartialRetentionMode(). Data in the SARAM0 buffer is verified after few CPU cycles of delay. Buffer should contain the data with which it was initialized before enabling the memory retention mode. This proves that the data stored in the SARAM0 is retained when it is placed into memory retention mode and is accessible after disabling the memory retention mode. Same test is repeated for other SARAM banks.

NOTE: DURING MEMORY RETENTION MODE TEST FOR SARAM ALL THE PROGRAM SECTIONS SHOULD BE PLACED IN THE DARAM. ACCESSING THE DATA IN THE RETENTION MODE ENABLED SARAM BANK BY ANY MEANS(CCS WATCH WINDOW, MEMORY WINDOW OR PLACING THE MOUSE POINTER ON THE SARAM DATA BUFFER TO VIEW THE VALUE) WILL CORRUPT ALL THE DATA IN THAT BANK.

NOTE: PARTIAL MEMORY RETENTION MODE IS SUPPORTED ONLY ON CHIP 5515. THIS TEST IS NOT VALID FOR CHIP 5505. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5515 EVM)
• Open the project "CSL_MEMORY_SARAM_PartialRetentionExample_Out.pjt" and build it
• Load the program on to the target
• Set the PLL frequency to 12.288MHz
• Run the program and observe the test result
• Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
• Repeat the test in Release mode

TEST RESULT:

• All CSL APIs should return success
• SARAM buffer data verification after disabling the memory retention mode should be successful

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MEMORY EXAMPLE5 - MSDRAM CLOCK OUTPUT SWITCH TEST

TEST DESCRIPTION:

This test verifies switching the mSDRAM clock output switch ON and OFF.

During the test mSDRAM clock output switch is made ON using CSL API MEM_setmSDRAMClock().State of the switch is read using CSL API MEM_getmSDRAMClock and is verified. Same procedure is repeated for making the switch OFF.

NOTE: DURNING THE MSDRAM CLOCK OUTPUT SWITCH ON AND OFF IS SUPPORTED ONLY ON CHIP C5515. THIS TEST IS NOT VALID FOR CHIP C5505.MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.

TEST PROCEDURE:

• Open the CCS and connect the target (C5515 EVM)
• Open the project "CSL_MSDRAM_ClockSwitchExample_Out.pjt" and build it
• Load the program on to the target
• Set the PLL frequency to 12.288MHz
• Run the program and observe the test result
• Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
• Repeat the test in Release mode

TEST RESULT:

• All CSL APIs should return success
• MSDRAM clock output switch should be configurable to ON and OFF