.ALIASES
X_U1            U1(BST=N15079 EN=N14587 FB=N16139 GND=0 RT=N14969 SS=N14809 SW=N15050 VIN=N14587 ) CN
+@TPS62933PSPICE.SCHEMATIC1(sch_1):INS14311@TPS62933_TRANS.TPS62933_TRANS.Normal(chips)
V_V1            V1(+=N14587 -=0 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14408@SOURCE.VDC.Normal(chips)
C_C1            C1(1=N15050 2=N15075 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14449@ANALOG.C.Normal(chips)
C_C2            C2(1=0 2=N14587 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14465@ANALOG.C.Normal(chips)
C_C3            C3(1=0 2=N14587 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14481@ANALOG.C.Normal(chips)
C_C4            C4(1=N14809 2=0 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14497@ANALOG.C.Normal(chips)
C_C5            C5(1=0 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14513@ANALOG.C.Normal(chips)
C_C6            C6(1=0 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14529@ANALOG.C.Normal(chips)
C_C7            C7(1=0 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14545@ANALOG.C.Normal(chips)
C_C8            C8(1=0 2=N14587 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14571@ANALOG.C.Normal(chips)
R_R1            R1(1=N14969 2=0 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14856@ANALOG.R.Normal(chips)
R_R2            R2(1=N16135 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14872@ANALOG.R.Normal(chips)
R_R3            R3(1=N16139 2=N16135 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14888@ANALOG.R.Normal(chips)
R_R4            R4(1=0 2=N16139 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14904@ANALOG.R.Normal(chips)
R_RLOAD          RLOAD(1=0 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS14920@ANALOG.R.Normal(chips)
R_R7            R7(1=N15079 2=N15075 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS15034@ANALOG.R.Normal(chips)
L_L1            L1(1=N15050 2=N15400 ) CN @TPS62933PSPICE.SCHEMATIC1(sch_1):INS15193@ANALOG.L.Normal(chips)
_    _(GND_0=0)
.ENDALIASES
