void tlv320aic3x_register_init(void)
{
#if 0
// ========== Step 1: Software Reset ==========
    tlv320aic3x_write(0x00, 0x00);    // Page 0
    tlv320aic3x_write(0x01, 0x01);    // Software reset
    msleep(10);                      // Wait for reset to complete

    // ========== Step 2: Clock Configuration (Adjust according to your MCLK) ==========
    // Assume MCLK = 12.288MHz, target sampling rate 48kHz
    tlv320aic3x_write(0x00, 0x00);    // Page 0
    tlv320aic3x_write(0x0B, 0x81);    // NDAC = 1, divider power up
    tlv320aic3x_write(0x0C, 0x82);    // MDAC = 2, divider power up
    tlv320aic3x_write(0x0D, 0x00);    // DOSR MSB = 0
    tlv320aic3x_write(0x0E, 0x80);    // DOSR LSB = 128 (actual DOSR=128)
    tlv320aic3x_write(0x0F, 0x02);    // Reserved register
    tlv320aic3x_write(0x10, 0x00);    // Reserved
    tlv320aic3x_write(0x11, 0x08);    // Reserved
    tlv320aic3x_write(0x12, 0x81);    // NADC = 1, divider power up
    tlv320aic3x_write(0x13, 0x82);    // MADC = 2, divider power up
    tlv320aic3x_write(0x14, 0x80);    // AOSR = 128
    tlv320aic3x_write(0x19, 0x00);    // CODEC_CLKIN = MCLK
    tlv320aic3x_write(0x1B, 0x00);    // I2S slave mode, 16bit (adjust as needed)
    tlv320aic3x_write(0x1C, 0x00);    // Data offset = 0
    tlv320aic3x_write(0x1D, 0x06);    // BDIV_CLKIN = ADC_CLK
    tlv320aic3x_write(0x1E, 0x88);    // BCLK divider power up, divider value = 8

    // ========== Step 3: DAC Signal Processing Block Selection ==========
    tlv320aic3x_write(0x3C, 0x04);    // DAC PRB_P4 (select as needed)

    // ========== Step 4: DAC Digital Section Power Up ==========
    tlv320aic3x_write(0x3F, 0xD6);    // DAC power up, left/right channel data routing normal
    msleep(10);                     // Wait for DAC to stabilize

    // ========== Step 5: Switch to Page1 for Analog Section Configuration ==========
    tlv320aic3x_write(0x00, 0x01);    // Page 1

    // Power configuration
    tlv320aic3x_write(0x01, 0x08);    // Disable coarse AVDD generation
    tlv320aic3x_write(0x02, 0x00);    // Main analog power control enable
    tlv320aic3x_write(0x7B, 0x01);    // REF charging time 40ms
    msleep(50);                     // Wait for REF to stabilize

    // Soft stepping configuration (to reduce pop noise)
    tlv320aic3x_write(0x14, 0x25);    // HP soft stepping setting
    tlv320aic3x_write(0x15, 0x25);    // Same as above

    // Common mode voltage
    tlv320aic3x_write(0x0A, 0x00);    // 0.9V

    // ========== Step 6: Configure Output Routing ==========
    // Configure routing for HPL/HPR (J7) and LOL/LOR (J6) simultaneously
    tlv320aic3x_write(0x0C, 0x08);    // Left DAC -> HPL
    tlv320aic3x_write(0x0D, 0x08);    // Right DAC -> HPR
    tlv320aic3x_write(0x0E, 0x08);    // Left DAC -> LOL
    tlv320aic3x_write(0x0F, 0x08);    // Right DAC -> LOR

    // Output gain (0dB)
    tlv320aic3x_write(0x10, 0x00);    // HPL gain
    tlv320aic3x_write(0x11, 0x00);    // HPR gain
    tlv320aic3x_write(0x12, 0x00);    // LOL gain
    tlv320aic3x_write(0x13, 0x00);    // LOR gain

    // ========== Step 7: Power Up Output Drivers ==========
    tlv320aic3x_write(0x09, 0x3C);    // Power up HPL, HPR, LOL, LOR simultaneously

    // ========== Step 8: Wait for Soft Stepping to Complete ==========
    // Method 1: Fixed delay (simple)
    msleep(2500);                   // Soft stepping takes 2.5 seconds (adjust based on coupling capacitor)
    
    // Method 2: Poll status register (recommended)
    // Read Page1 Register 0x3F bits 7-6, when value is "11" indicates completion
    // However, for simplicity, a fixed delay is used

    // ========== Step 9: Configure ADC (if needed) ==========
    tlv320aic3x_write(0x00, 0x00);    // Page 0
    tlv320aic3x_write(0x3D, 0x01);    // ADC PRB_R1
    tlv320aic3x_write(0x51, 0xC0);    // ADC power up
    tlv320aic3x_write(0x52, 0x00);    // ADC digital volume unmute

    // Switch back to Page0
    tlv320aic3x_write(0x00, 0x00);

#else
printk("%s/L%d\n", __FUNCTION__, __LINE__);
 // Configure all Page 0 registers according to current table values
tlv320aic3x_write(0x00, 0x00);
tlv320aic3x_write(0x01, 0x00);
tlv320aic3x_write(0x02, 0x60);
tlv320aic3x_write(0x03, 0x00);
tlv320aic3x_write(0x04, 0x00);
tlv320aic3x_write(0x05, 0x11);
tlv320aic3x_write(0x06, 0x04);
tlv320aic3x_write(0x07, 0x00);
tlv320aic3x_write(0x08, 0x00);
tlv320aic3x_write(0x09, 0x00);
tlv320aic3x_write(0x0A, 0x00);
tlv320aic3x_write(0x0B, 0x81);
tlv320aic3x_write(0x0C, 0x84);
tlv320aic3x_write(0x0D, 0x00);
tlv320aic3x_write(0x0E, 0x40);
tlv320aic3x_write(0x0F, 0x02);
tlv320aic3x_write(0x10, 0x00);
tlv320aic3x_write(0x11, 0x08);
tlv320aic3x_write(0x12, 0x01);
tlv320aic3x_write(0x13, 0x01);
tlv320aic3x_write(0x14, 0x80);
tlv320aic3x_write(0x15, 0x01);
tlv320aic3x_write(0x16, 0x00);
tlv320aic3x_write(0x17, 0x04);
tlv320aic3x_write(0x18, 0x00);
tlv320aic3x_write(0x19, 0x00);
tlv320aic3x_write(0x1A, 0x01);
tlv320aic3x_write(0x1B, 0x00);
tlv320aic3x_write(0x1C, 0x00);
tlv320aic3x_write(0x1D, 0x00);
tlv320aic3x_write(0x1E, 0x01);
tlv320aic3x_write(0x1F, 0x00);
tlv320aic3x_write(0x20, 0x00);
tlv320aic3x_write(0x21, 0x00);
tlv320aic3x_write(0x22, 0x00);
tlv320aic3x_write(0x23, 0x00);
tlv320aic3x_write(0x24, 0x00);
tlv320aic3x_write(0x25, 0xEE);
tlv320aic3x_write(0x26, 0x11);
tlv320aic3x_write(0x27, 0x00);
tlv320aic3x_write(0x28, 0x00);
tlv320aic3x_write(0x29, 0x00);
tlv320aic3x_write(0x2A, 0xE0);
tlv320aic3x_write(0x2B, 0x00);
tlv320aic3x_write(0x2C, 0x0C);
tlv320aic3x_write(0x2D, 0x00);
tlv320aic3x_write(0x2E, 0x00);
tlv320aic3x_write(0x2F, 0x00);
tlv320aic3x_write(0x30, 0x00);
tlv320aic3x_write(0x31, 0x00);
tlv320aic3x_write(0x32, 0x00);
tlv320aic3x_write(0x33, 0x00);
tlv320aic3x_write(0x34, 0x00);
tlv320aic3x_write(0x35, 0x12);
tlv320aic3x_write(0x36, 0x03);
tlv320aic3x_write(0x37, 0x02);
tlv320aic3x_write(0x38, 0x02);
tlv320aic3x_write(0x39, 0x00);
tlv320aic3x_write(0x3A, 0x00);
tlv320aic3x_write(0x3B, 0x00);
tlv320aic3x_write(0x3C, 0x08);
tlv320aic3x_write(0x3D, 0x01);
tlv320aic3x_write(0x3E, 0x00);
tlv320aic3x_write(0x3F, 0xD6);
tlv320aic3x_write(0x40, 0x00);
tlv320aic3x_write(0x41, 0x00);
tlv320aic3x_write(0x42, 0x00);
tlv320aic3x_write(0x43, 0x00);
tlv320aic3x_write(0x44, 0x6F);
tlv320aic3x_write(0x45, 0x38);
tlv320aic3x_write(0x46, 0x00);
tlv320aic3x_write(0x47, 0x00);
tlv320aic3x_write(0x48, 0x00);
tlv320aic3x_write(0x49, 0x00);
tlv320aic3x_write(0x4A, 0x00);
tlv320aic3x_write(0x4B, 0xEE);
tlv320aic3x_write(0x4C, 0x10);
tlv320aic3x_write(0x4D, 0xD8);
tlv320aic3x_write(0x4E, 0x7E);
tlv320aic3x_write(0x4F, 0xE3);
tlv320aic3x_write(0x50, 0x00);
tlv320aic3x_write(0x51, 0x00);
tlv320aic3x_write(0x52, 0x88);
tlv320aic3x_write(0x53, 0x00);
tlv320aic3x_write(0x54, 0x00);
tlv320aic3x_write(0x55, 0x00);
tlv320aic3x_write(0x56, 0x00);
tlv320aic3x_write(0x57, 0x00);
tlv320aic3x_write(0x58, 0x7F);
tlv320aic3x_write(0x59, 0x00);
tlv320aic3x_write(0x5A, 0x00);
tlv320aic3x_write(0x5B, 0x00);
tlv320aic3x_write(0x5C, 0x00);
tlv320aic3x_write(0x5D, 0x00);
tlv320aic3x_write(0x5E, 0x00);
tlv320aic3x_write(0x5F, 0x00);
tlv320aic3x_write(0x60, 0x7F);
tlv320aic3x_write(0x61, 0x00);
tlv320aic3x_write(0x62, 0x00);
tlv320aic3x_write(0x63, 0x00);
tlv320aic3x_write(0x64, 0x00);
tlv320aic3x_write(0x65, 0x00);
tlv320aic3x_write(0x66, 0x00);
tlv320aic3x_write(0x67, 0x00);
tlv320aic3x_write(0x68, 0x00);
tlv320aic3x_write(0x69, 0x00);
tlv320aic3x_write(0x6A, 0x00);
tlv320aic3x_write(0x6B, 0x00);
tlv320aic3x_write(0x6C, 0x00);
tlv320aic3x_write(0x6D, 0x00);
tlv320aic3x_write(0x6E, 0x00);
tlv320aic3x_write(0x6F, 0x00);
tlv320aic3x_write(0x70, 0x00);
tlv320aic3x_write(0x71, 0x00);
tlv320aic3x_write(0x72, 0x00);
tlv320aic3x_write(0x73, 0x00);
tlv320aic3x_write(0x74, 0x00);
tlv320aic3x_write(0x75, 0x00);
tlv320aic3x_write(0x76, 0x00);
tlv320aic3x_write(0x77, 0x00);
tlv320aic3x_write(0x78, 0x00);
tlv320aic3x_write(0x79, 0x00);
tlv320aic3x_write(0x7A, 0x00);
tlv320aic3x_write(0x7B, 0x00);
tlv320aic3x_write(0x7C, 0x00);
tlv320aic3x_write(0x7D, 0x00);
tlv320aic3x_write(0x7E, 0x00);
tlv320aic3x_write(0x7F, 0x00);

#endif


}