*INA201 
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* (C) Copyright 2013 Texas Instruments Incorporated. All rights reserved.                                            
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** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of 
** merchantability or fitness for a particular purpose.  The model is
** provided solely on an "as is" basis.  The entire risk as to its quality
** and performance is with the customer.
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*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
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*
* Released by: Webench Design Center, Texas Instruments Inc.
* Part: INA201
* Date: 08MAR2013
* Model Type: ALL IN ONE
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SBOS374C NOVEMBER 2006REVISED OCTOBER 2010
*
* Model Version: 1.0
*
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*
* Updates:
*
* Version 1.0 : 
* Release to Web
*
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* OPERATING NOTES
*
* THIS MACROMODEL WILL GIVE RESULTS WHICH ARE CONSISTENT WITH THE DATASHEET FOR NORMAL CASE 1 OPERATION.
* THIS MODEL WAS NOT DEVELOPED TO MATCH BEHAVIOUR IN ANY LOW VSENSE CASE OR NORMAL CASE 2.
* 
* MODEL FEATURES
* THIS MODEL FEATURES CURRENT SHUNT MONITOR WITH PARAMETERS:
* INPUT RANGE, OUTPUT SWING, OUTPUT COMPLIANCE (V+=12V), BANDWIDTH,
* GAIN VS CL, CMRR VS FREQ, PSRR VS FREQ,
* SETTLING TIME, QUIESCENT CURRENT AND
* QUIESCENT CURRENT VERSUS OUTPUT VOLTAGE,
* OUTPUT CURRENT DRAWN THROUGH THE SUPPLY,
* OUTPUT IMPEDANCE, INPUT OFFSET, INPUT
* BIAS CURRENT, AND NOISE, SHORT CIRCUIT CURRENT LIMIT
* VERSUS SUPPLY VOLTAGE.
*
* THIS MODEL FEATURES COMPARATOR
* WITH PARAMETERS OFFSET VOLTAGE, HYSTERESIS, EXTERNAL THRESHOLD,
* BIAS CURRENTS, INPUT IMPEDANCE, LARGE SIGNAL DIFFERENTIAL GAIN, 
* RESPONSE TIME, PROPAGATION DELAY, HIGH LEVEL OUTPUT CURRENT,
* LOW LEVEL OUTPUT VOLTAGE.
* COMPARATO1 FEATURES RESET LATCHING FUNCTIONALITY.
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.SUBCKT INA201 OUT VS CMP_IN+ GND VIN- VIN+ CMP_OUT CMP_RESET_B
XU5         VIN- GND VIN+ VS OUT CSM_0
XU9         10 GND REFERENCE_0
XU4         10 CMP_RESET_B CMP_IN+ CMP_OUT Vs1 GND CMP1_0
EVCVS1      Vs1 GND VS GND  1
.ENDS INA201

.SUBCKT CSM_0 Vin- GND Vin+ Vs VOUT
V3          33 32 403.54U
V4          GND 34 400M
V1          VDD 47 150M
IS1         Vin- GND 9U
VCCVS4_in   17 GND
HCCVS4      18 GND VCCVS4_in   1
EVCVS9      19 GND VDD GND  5.6234U
C4          19 17 1.5915M 
R3          19 17 1 
VCCVS3_in   20 GND
HCCVS3      21 GND VCCVS3_in   1
C3          20 22 530.5U 
R9          20 22 1 
EVCVS8      22 GND IN+_Commonmode GND  1U
VCCVS2_in   23 GND
HCCVS2      24 GND VCCVS2_in   1
C1          25 23 106N 
R8          25 23 1 
EVCVS7      25 GND 26 GND  1
C2          26 GND 1N  
R7          27 26 R_RES_1 100 
EVCVS1      27 GND 28 GND  1
L4          29 30 400U  
XU1         IN+_Commonmode 31 32 IN+_Commonmode VCVS_LIMIT_0
C17         35 GND 1P  
C19         GND 36 1P  
R26         37 36 1 
R25         38 35 1 
R6          39 CL_clamp 10M 
SW2         39 37 36 GND  S_VSWITCH_1
SW1         38 39 GND 35  S_VSWITCH_2
XU22        40 Vimon 38 GND VCVS_LIMIT_1
XU21        34 Vimon 37 GND VCVS_LIMIT_1
EVCVS5      40 GND Vclim GND  1K
XU10        VDD GND Vclim GND VCCS_LIMIT_0
EVCVS6      42 GND 41 31  1
R11         43 44 R_RES_2 1MEG 
EVCVS4      43 GND VOUT GND  1
XU3         44 GND Vs GND VCCS_LIMIT_1
GVCCS4      Vs GND Vimon GND  1M
EVCVS3      VDD GND Vs GND  1
R1          Vclp GND 1T 
C7          VOUT GND 66P  
R15         45 30 300 
XR103       GND 46 RNOISE_FREE_0
XU13        46 28 0 28 VCCS_LIMIT_2
C6          28 0 500N  
R12         28 0 R_RES_3 10K 
XU12        41 33 noise_macro_0
XU23        Vimon GND 47 Vclp VCVS_LIMIT_2
XU11        CL_clamp GND 45 GND VCVS_LIMIT_3
R5          CL_clamp GND R_RES_4 1 
GVCCS2      CL_clamp GND 24 GND  -1
EVCVS2      48 GND Vclp GND  1
VCCVS1_in   30 VOUT
HCCVS1      Vimon 0 VCCVS1_in   1K
ROUT        45 29 R_RES_5 1.5 
R4          Vin- 31 R_RES_6 1U 
R2          Vin+ IN+_Commonmode R_RES_7 1U 
XU2         21 GND 49 50 VCVS_LIMIT_4
XU25        18 GND 49 42 VCVS_LIMIT_5
XU26        50 GND GND 46 48 VCCS_LIMIT_3
.MODEL R_RES_1 RES ( TCE=0 T_ABS=-300)
.MODEL S_VSWITCH_1 VSWITCH (RON=1 ROFF=1T VON=10 VOFF=-10)
.MODEL S_VSWITCH_2 VSWITCH (RON=1 ROFF=1T VON=10 VOFF=-10)
.MODEL R_RES_2 RES ( TCE=0 T_ABS=-300)
.MODEL R_RES_3 RES ( TCE=0 T_ABS=-300)
.MODEL R_RES_4 RES ( TCE=0 T_ABS=-300)
.MODEL R_RES_5 RES ( TCE=0 T_ABS=-300)
.MODEL R_RES_6 RES ( TCE=0 T_ABS=-300)
.MODEL R_RES_7 RES ( TCE=0 T_ABS=-300)
.ENDS

.SUBCKT noise_macro_0 + -
EVCVS1      + - 51 0  1
R1          51 0 R_RES_1 96.3K 
.MODEL R_RES_1 RES ( TCE=0 T_ABS=25)
.ENDS



.SUBCKT CMP1_0 IN- RESET_B IN+ VOUT Vs gnd
V2          58 0 1
V1          61 gnd 950M
IbiasPos    IN+ gnd 5P
R4          VOUT gnd  1.00000000000000E+0015 
XU9         RESET_B RESET_B1 RESETB_DEGLITCH_DELAY_0
XU8         CMP1_Gain_stage_op gnd 56 gnd Vs NORMALIZE_0
R3          RESETB_OUT gnd 100K 
XU7         IN+ INm gnd Vs CMP1_Gain_stage_op Gain_Stage_Hyst_0
XU4         OP_D gnd VOUT gnd RESISTANCE_0
C2          gnd VOUT 711.36P 
R2          IN+ gnd  1.00000000000000E+0015 
XU6         INm IN- VOS_0
EVCVS2      60 gnd OP_R gnd  1
XU1         62 61 OP_D COMP_HYST_POS_VIH_0
+ PARAMS: VDD=1 VEE=0 HYST=0.9 
XU5         IN+ INm 62 60 PSUPP_DCC_0_0
C1          62 gnd 1N  
XU3         gnd RESET_B1 RESETB_OUT RESET_DEGLITCH_DELAY_0
XU2         gnd RESETB_OUT 56 OP_D 58 OP_R RESET_LOGIC_0
R1          RESET_B gnd 2MEG 
.ENDS

.SUBCKT Gain_Stage_Hyst_0 IN+ IN- GND VS Vout
XU5         Vout VS IN- 63 HYST_GEN_0
XU2         IN+ 63 Vout GND VS VCVS_0
.ENDS


.SUBCKT RESET_DEGLITCH_DELAY_0 gnd RESETB_IN RESETB_OUT
R2          Vout 66 652 
EVCVS1      67 66 RESETB_OUT gnd  800M
XU2         68 RESETB_OUT INV_BASIC_GEN_SAN_0
+ PARAMS: VDD=1 VEE=0 VTH=0.5
XU1         67 68 INV_BASIC_GEN_SAN_0
+ PARAMS: VDD=1 VEE=0 VTH=0.9
C1          gnd 66 1N 
R1          RESETB_IN 69 652 
EVCVS14     VF2 69 Vout gnd  810M
XU16        70 Vout INV_BASIC_GEN_SAN_0
+ PARAMS: VDD=1 VEE=0 VTH=0.5
XU15        VF2 70 INV_BASIC_GEN_SAN_0
+ PARAMS: VDD=1 VEE=0 VTH=0.9
C7          gnd 69 1N 
.ENDS


.SUBCKT RESET_LOGIC_0 gnd RESETB IN OP_IN VDD OUT
XU2         IN 71 RESETB OUT MUX_0
XU1         IN OP_IN VDD gnd 71 OR_TANH_0
.ENDS




*REFERENCE

.SUBCKT REFERENCE_0  + -
EREF         + - VALUE = {0.6 + (48U)*(TEMP-25)}

.ENDS


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_0  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 50
.PARAM VPOS = 5.5M
.PARAM VNEG = 0
E1 VOUT+ VOUT-  VALUE={LIMIT(-.2759*V(VC+,VC-)+(5.5M),5.48M,-.0M)}

.ENDS VCVS_LIMIT_0 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_1  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 1000
.PARAM VPOS = 5000
.PARAM VNEG = -5000
E1 VOUT+ VOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),VPOS,VNEG)}
.ENDS VCVS_LIMIT_1 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCCS_LIMIT_0  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 5.5E-3
.PARAM IPOS = 27.5M
.PARAM INEG = 0
ESAT 1 0 VALUE={-54.54E-6*(TEMP) + 0.02981}
EOUT VOUT+ VOUT- VALUE={LIMIT((-23E-6*(TEMP) + 0.00859)*V(VC+,VC-) + (0.00003419*(TEMP) - 12.024E-3), V(1,0),INEG)}
.ENDS VCCS_LIMIT_0 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCCS_LIMIT_1  VC+ VC- IOUT+ IOUT-
*              
.PARAM GAIN = 0.05E-3
.PARAM IPOS = .5
.PARAM INEG = -.5 
E1 1 0 VALUE={LIMIT(1.25M+1M*V(VC+,VC-),1.5M,1.25M)}
E2 2 1 VALUE={LIMIT(.14358M*V(VC+,VC-) - .035875M,5M,0)}
R 2 0 1M
G1 IOUT+ IOUT- VALUE={V(2,0)}
.ENDS VCCS_LIMIT_1 


* NOISELESS RESISTOR
.SUBCKT RNOISE_FREE_0  1 2
*ROHMS = VALUE IN OHMS OF NOISELESS RESISTOR
.PARAM ROHMS=1E6
ERES 1 3 VALUE = { I(VSENSE) * ROHMS }
RDUMMY 30 3 1
VSENSE 30 2 DC 0V
.ENDS RNOISE_FREE_0 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCCS_LIMIT_2  VC+ VC- IOUT+ IOUT-
*              
.PARAM GAIN = 942.57M
.PARAM IPOS = .5
.PARAM INEG = -.5

G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),IPOS,INEG)}
.ENDS VCCS_LIMIT_2 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_2  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 10.6M
.PARAM VPOS = 2
.PARAM VNEG = 0
*E1 VOUT+ 1 VALUE={LIMIT((0.2343E-3*(TEMP) +78.46E-3)*V(VC+,VC-),VPOS,VNEG)}
E1 VOUT+ 1 VALUE={LIMIT((0.1696E-3*(TEMP) +48.786E-3)*V(VC+,VC-),VPOS,VNEG)}
*E2 VOUT+ VOUT- VALUE={(0.5+0.5*TANH((V(VC+,VC-)-17.5)*10E12))*LIMIT(EXP(0.3*(V(VC+,VC-)-17.5)),5,0)}
E2 1 VOUT- VALUE={LIMIT(EXP(.5*(V(VC+,VC-)-(-.051515*(TEMP)+24.94))),(V(VOUT+,0)-2),0)}
*(0.5+0.5*TANH((V(VC+,VC-)-17.5)*10E8))*
.ENDS VCVS_LIMIT_2 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_3  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 1
.PARAM VPOS = 18
.PARAM VNEG = 4M
E1 VOUT+ VOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),VPOS,VNEG)}
.ENDS VCVS_LIMIT_3 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_4  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = -1
.PARAM VPOS = 20M
.PARAM VNEG = -20M
E1 VOUT+ VOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),VPOS,VNEG)}
.ENDS VCVS_LIMIT_4 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCVS_LIMIT_5  VC+ VC- VOUT+ VOUT-
*              
.PARAM GAIN = 1
.PARAM VPOS = 20M
.PARAM VNEG = -20M
E1 VOUT+ VOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),VPOS,VNEG)}
.ENDS VCVS_LIMIT_5 


*VOLTAGE CONTROLLED SOURCE WITH LIMITS
.SUBCKT VCCS_LIMIT_3  VC+ VC- IOUT+ IOUT- VSAT
*              
.PARAM GAIN = 50U
.PARAM IPOS = 18U
.PARAM INEG = 0

G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),V(VSAT,0)*1U,INEG)}
.ENDS VCCS_LIMIT_3 


*DEGLITCH

.SUBCKT RESETB_DEGLITCH_DELAY_0  RESETB OUT

E_TH OUT1 0 VALUE={0.5+0.5*TANH((V(RESETB)-1.09)*1E6)}
E_VCVS OUT 0 OUT1 0 1

.ENDS



** 2:1 MUX**
.SUBCKT NORMALIZE_0  IN1 IN2 OUT1 OUT2 VS
E1 OUT1 OUT2 VALUE= { V(IN1,IN2)/V(VS) }
.ENDS



***DELAY VS TEMPERATURE AND OVERDRIVE VOLTAGE***
.SUBCKT RESISTANCE_0  IN1 IN2 O+ O- 

E_RVAL RVAL 0 VALUE={100N+120*V(IN1,IN2)}
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL)*1E9)}

.ENDS


***COMPARATOR OFFSET VARIATION***
.SUBCKT VOS_0  + -
E + - VALUE = {(2 - 2M*(TEMP - 25))*1M}
.ENDS


* POSITIVE COMPARATOR WITH HYSTERISIS
* INP -- +VE TERMINAL; INM -- -VE TERMINAL
* IF OUTPUT = VDD E_HYST VALUE = HYSTERISIS ELSE E_HYST VALUE = 0

.SUBCKT COMP_HYST_POS_VIH_0  INP INM OUT PARAMS: VDD=1 VEE=0 HYST=0.1 

E_HYST INM INM1 VALUE = {((HYST)/2)+((HYST)/2)*TANH(10E6*(V(OUT1)-((VDD+VEE)/2)))}

E_COMP OUT 0 VALUE = {((VDD+VEE)/2)+((VDD-VEE)/2)*TANH(1E6*(V(INP)-V(INM1)))}

R_DELAY OUT OUT1 1
C_DELAY OUT1 0 10N

.ENDS COMP_HYST_POS_VIH_0 


***DELAY VS TEMPERATURE AND OVERDRIVE VOLTAGE***
.SUBCKT PSUPP_DCC_0_0   IN1 IN2 O+ O-
EW W 0 VALUE={TANH(1E12*(V(IN1,IN2)*1K))}
E_DELAY DELAY 0 VALUE={100.76816*(1.071312)**(-V(IN1,IN2)*V(W)*1K)+114.59256 + 0.56*(TEMP-25)}
GOUT O+ O- VALUE = {(2.99573/V(DELAY))*V(O+,O-)}
ROUT O+ O- 1E15
.ENDS


***HYSTERESIS***
.SUBCKT HYST_GEN_0  VO VS + -

ETH VTH 0 VALUE = {0.01*(V(F1)) + 0.99*(1-(V(F1)))}
EF1 F1 0 VALUE = {(0.5 + 0.5*TANH(1E20*(V(VO)/V(VS)-V(VTH))))}
EHYST + - VALUE = {8M*V(F1)}

.ENDS



** 2:1 MUX**
.SUBCKT VCVS_0  IN1 IN2 OUT1 OUT2 VS
E1 OUT1 OUT2 VALUE= { LIMIT(2E5*V(IN1,IN2),V(VS),0) }
.ENDS



*INVERTER
.SUBCKT INV_BASIC_GEN_SAN_0  IN Y PARAMS: VDD=1 VEE=0 VTH=0.5 
E_ABM Y 0 VALUE = {((VDD+VEE)/2)-((VDD-VEE)/2)*TANH(10E12*(V(IN)-VTH))}
.ENDS INV_BASIC_GEN_SAN_0 



** 2:1 MUX**
.SUBCKT MUX_0  A B SEL OUT 
*E_TH VTH 0 VALUE={0.5+0.5*TANH((V(SEL)-1.09)*1E12)}
E1 OUT 0 VALUE= { ((V(B)-V(A))*V(SEL))+V(A)}
.ENDS




** OR_TANH**
.SUBCKT OR_TANH_0  A B VDD VEE OUT 
EVT VTH 0 VALUE={V(VDD)/2}
EA AI VEE VALUE={ (((V(VDD,0)-V(VEE,0))/2)*(TANH((V(A)-V(VTH))*(1000000))))+((V(VDD,0)+V(VEE,0))/2)}
EB BI VEE VALUE={ (((V(VDD,0)-V(VEE,0))/2)*(TANH((V(B)-V(VTH))*(1000000))))+((V(VDD,0)+V(VEE,0))/2)}
E1 OUT VEE VALUE={ (((V(VDD,0)-V(BI,0))*V(AI,0))+ V(BI,0))}
.ENDS
*$