#!/bin/sh # echo -e "\n LMFS=8212, HD=1, K=32, serial line rate = 6G, jesd204_coreclk = 150M\n" devmem 0x43c50000 32 0x03F380 # 00 # 87 , coarse_dac=1111 , fifo_error_zeros_data_ena=1 , sif_txenable=0 devmem 0x43c50004 32 0x022003 # 01 , dac_bitwidth=16 , zero_invalid_data , shorttest_ena , sif4_ena=0 , mixer_ena , mixer_gain , nco_ena=0 , twos=1 , sif_reset=1 # qmc_offsetab_ena , qmc_offsetcd_ena , qmc_corrab_ena , qmc_corrcd_ena , interp = 4x , # alarm_zeros_txenable_ena , outsum_ena , alarm_zeros_jesd_data_ena , alarm_out_ena=1 , alarm_out_pol=1 , pap_ena , inv_sinc_ab_ena , inv_sinc_cd_ena # devmem 0x43c50008 32 0x000218 # 02 , interp = 4x , # devmem 0x43c50008 32 0x00021B # 02 , interp = 4x , inv_sinc_ab_ena=1 , inv_sinc_cd_ena=1 # devmem 0x43c50008 32 0x00021F # 02 , interp = 4x , pap_ena=1 , inv_sinc_ab_ena=1 , inv_sinc_cd_ena=1 devmem 0x43c50008 32 0x000018 # 02 , interp = 1x , devmem 0x43c5000C 32 0x0100A3 # 03 , sfrac_ena_ab , sfrac_ena_cd , lfrac_ena_ab , lfrac_ena_cd , sfrac_sel_ab , sfrac_sel_cd , daca_compliment=1 , dacb_compliment=0 , dacc_compliment=1 , dacd_compliment=0 # devmem 0x43c50010 32 0x0400FF # 05 , alarms_mask(15:0) devmem 0x43c50010 32 0x040000 # 05 , alarms_mask(15:0) # devmem 0x43c50014 32 0x05FFFF # 06 , alarms_mask(31:16) devmem 0x43c50014 32 0x050000 # 06 , alarms_mask(31:16) # devmem 0x43c50018 32 0x06FFFF # 07 , alarms_mask(47:32) devmem 0x43c50018 32 0x060000 # 07 , alarms_mask(47:32) devmem 0x43c5001C 32 0x080000 # 08 , qmc_offseta devmem 0x43c50020 32 0x090000 # 09 , qmc_offsetb devmem 0x43c50024 32 0x0A0000 # 10 , qmc_offsetc devmem 0x43c50028 32 0x0B0000 # 11 , qmc_offsetd devmem 0x43c5002C 32 0x0C0400 # 12 , qmc_gaina=1.0 devmem 0x43c50030 32 0x0D0400 # 13 , cmix(fs/8 , fs/4 , fs/2 , fsm4) , qmc_gainb=1.0 devmem 0x43c50034 32 0x0E0400 # 14 , qmc_gainc=1.0 devmem 0x43c50038 32 0x0F0400 # 15 , output_delayab , output_delaycd , qmc_gaind=1.0 devmem 0x43c5003C 32 0x100000 # 16 , qmc_phaseab=0.0 devmem 0x43c50040 32 0x110000 # 17 , qmc_phasecd=0.0 devmem 0x43c50044 32 0x120000 # 18 , phaseoffsetab devmem 0x43c50048 32 0x130000 # 19 , phaseoffsetcd devmem 0x43c5004C 32 0x140000 # 20 , phaseaddab lower 16 bits devmem 0x43c50050 32 0x150000 # 21 , phaseaddab middle 16 bits devmem 0x43c50054 32 0x160000 # 22 , phaseaddab upper 16 bits devmem 0x43c50058 32 0x170000 # 23 , phaseaddcd lower 16 bits devmem 0x43c5005C 32 0x180000 # 24 , phaseaddcd middle 16 bits devmem 0x43c50060 32 0x190000 # 25 , phaseaddcd upper 16 bits devmem 0x43c50064 32 0x1A0020 # 26 , vbgr_sleep , biasopamp_sleep , tsense_sleep , pll_sleep=1 , clkrecv_sleep , daca_sleep , dacb_sleep , dacc_sleep , dacd_sleep # devmem 0x43c50068 32 0x1B0000 # 27 , extref_ena=0 , dtest_lane=0 , dtest=Test disabled=0000 , atest=0 devmem 0x43c50068 32 0x1B0100 # 27 # 45, extref_ena=0 , dtest_lane=0 , ***dtest=SERDES Block0 PLL clock/80=0001 , atest=0 # devmem 0x43c50068 32 0x1B0200 # 27 # 45, extref_ena=0 , dtest_lane=0 , ***dtest=SERDES Block1 PLL clock/80=0010 , atest=0 # devmem 0x43c50068 32 0x1B0600 # 27 # 45, extref_ena=0 , dtest_lane=0 , dtest=EQUNDER=0110 , atest=0 # devmem 0x43c50068 32 0x1B0700 # 27 # 45, extref_ena=0 , dtest_lane=0 , dtest=EQOVER=0111 , atest=0 devmem 0x43c5006C 32 0x1E1111 # 28 , syncsel_qmoffsetab=auto-sync , syncsel_qmoffsetcd=auto-sync , syncsel_qmcorrab=auto-sync , syncsel_qmcorrcd=auto-sync # devmem 0x43c50070 32 0x1F1140 # 29 , syncsel_mixerab=auto-sync , syncsel_mixercd=auto-sync , syncsel_nco=JESD , sif_sync devmem 0x43c50070 32 0x1F9980 # 29 , syncsel_mixerab=auto-sync/sif_sync , syncsel_mixercd=auto-sync/sif_sync , syncsel_nco=sif_sync , sif_sync=0 devmem 0x43c50074 32 0x200000 # 30 , syncsel_dither=0 , syncsel_pap=0 , syncsel_fir5a=0 devmem 0x43c50078 32 0x221B1B # 31 , patha_in_sel=path A , pathb_in_sel=path B , pathc_in_sel , pathd_in_sel , patha_out_sel=path A , pathb_out_sel=path B , pathc_out_sel , pathd_out_sel # devmem 0x43c5007C 32 0x23FFFF # 32 , sleep_cntl, DACB=0 devmem 0x43c5007C 32 0x23FFF0 # 32 , sleep_cntl, DACD/DACC/DACB/DACA to sleep=0 # devmem 0x43c50080 32 0x240000 # 33 , cdrvser_sysref_mode= Don’t use SYSREF pulse # devmem 0x43c50080 32 0x240010 # 33 , cdrvser_sysref_mode= Use all SYSREF pulses devmem 0x43c50080 32 0x240020 # 33 , cdrvser_sysref_mode= Use only the next SYSREF pulse # devmem 0x43c50080 32 0x240030 # 33 , cdrvser_sysref_mode= Skip one SYSREF pulse then use only the next one # devmem 0x43c50080 32 0x240040 # 33 , cdrvser_sysref_mode= = Skip one SYSREF pulse then use all pulses devmem 0x43c50084 32 0x256000 # 34 , clkjesd_div=div8 devmem 0x43c50088 32 0x260000 # 35 , dither_ena=0 , dither_mixer_ena , dither_sra_sel , dither_zero devmem 0x43c5008C 32 0x2D0000 # 36 , pap_dlylen_sel , pap_gain devmem 0x43c50090 32 0x2EFFFF # 37 , pap_vth devmem 0x43c50094 32 0x2F0004 # 38 , titest_dieid_read_ena=0 , sifdac_ena=0 devmem 0x43c50098 32 0x300000 # 39 , sifdc # pll devmem 0x43c5009C 32 0x310000 # 40 , lockdet_adj=narrow window , pll_reset , pll_ndivsync_ena , pll_ena=0 , pll_cp , pll_n , memin_pll_lfvolt devmem 0x43c500A0 32 0x320000 # 41 , PLL_M=0 , PLL_P=div by 2=0 devmem 0x43c500A4 32 0x330100 # 42 , pll_vcosel=5GHz VCO=0 , pll_vco , pll_vcoitune=9.8mA=10 , pll_cp_adj devmem 0x43c500A8 32 0x340000 # 43 , syncb_lvds_lopwrb , syncb_lvds_lopwra , syncb_lvds_lpsel , syncb_lvds_effuse_sel , syncb_lvds_sleep , syncb_lvds_sub_ena # serdes_pll # devmem 0x43c500AC 32 0x3B9800 # 44 , serdes_clk_sel= from the pins=1 , serdes_refclk_div= 3(plus one) devmem 0x43c500AC 32 0x3B1800 # 44 , serdes_clk_sel= from the pins=0 , serdes_refclk_div= 3(plus one) # devmem 0x43c500B0 32 0x3C0050 # 45 , rw_cfgpll(serdes) , ***ENDIVCLK=0 , LB=0-Medium , SLEEPPLL=0 , VRANGE=0 , MPY=10x=00101000 devmem 0x43c500B0 32 0x3C8050 # 45 # 27, rw_cfgpll(serdes) , ***ENDIVCLK=1 , LB=0-Medium , SLEEPPLL=0 , VRANGE=0 , MPY=10x=00101000 # devmem 0x43c500B4 32 0x3D0088 # 46 , rw_cfgrx0[30:16] , TESTPATT=disabled , ENOC=1 , EQHLD=enabled=0 , EQ_Boost=0 , EQ=Fully=01 , CDR=000 # devmem 0x43c500B4 32 0x3D00A8 # 46 , rw_cfgrx0[30:16] , TESTPATT=disabled , ENOC=1 , EQHLD=enabled=0 , EQ_Boost=1 , EQ=Fully=01 , CDR=000 # devmem 0x43c500B4 32 0x3D00A9 # 46 , rw_cfgrx0[30:16] , TESTPATT=disabled , ENOC=1 , EQHLD=enabled=0 , EQ_Boost=1 , EQ=Fully=01 , CDR=001 devmem 0x43c500B4 32 0x3D00AD # 46 , rw_cfgrx0[30:16] , TESTPATT=disabled , ENOC=1 , EQHLD=enabled=0 , EQ_Boost=1 , EQ=Fully=01 , CDR=101 # devmem 0x43c500B4 32 0x3D00A1 # 46 , rw_cfgrx0[30:16] , TESTPATT=disabled , ENOC=1 , EQHLD=enabled=0 , EQ_Boost=1 , EQ=No equalization=00 , CDR=001 # devmem 0x43c500B8 32 0x3E8128 # 47 , rw_cfgrx0[15:00] , LOS=1 , TERM=001 , RATE=Half=01 , BUSWIDTH=20bit=010 , SLEEPRX=0 devmem 0x43c500B8 32 0x3E8928 # 47 , rw_cfgrx0[15:00] , LOS=1 , align=01 , TERM=001 , RATE=Half=01 , BUSWIDTH=20bit=010 , SLEEPRX=0 devmem 0x43c500BC 32 0x3F0000 # 48 , invpair=0 devmem 0x43c500C0 32 0x490000 # 49 , link_assign , lane7-0=link0 devmem 0x43c500C4 32 0x4AFF1E # 50 # 86, lane_ena=11111111 , jesd_test_seq=0 , dual=0 , init_state=1111 , jesd_reset_n=0 # devmem 0x43c500C8 32 0x4B0400 # 51 , rbd_m1=5 , f_m1=1 # devmem 0x43c500C8 32 0x4B1500 # 51 , rbd_m1=22 , f_m1=1 devmem 0x43c500C8 32 0x4B1F00 # 51 , rbd_m1=32 , f_m1=1 devmem 0x43c500CC 32 0x4C1F07 # 52 , k_m1=32 , l_m1=8 # devmem 0x43c500CC 32 0x4C0707 # 52 , k_m1=8 , l_m1=8 devmem 0x43c500D0 32 0x4D0101 # 53 , m_m1=2 , s_m1=2 devmem 0x43c500D4 32 0x4E0F6F # 54 , nprime_m1=N'=16 , hd=1 , scrambler=1 , n_m1=N=16 # devmem 0x43c500D4 32 0x4E0F4F # 54 , nprime_m1=N'=16 , hd=1 , scrambler=0 , n_m1=N=16 devmem 0x43c500D8 32 0x4F1CC1 # 55 , match_data=K28.0=0x1C , match_specific=1 , match_ctrl=1 , no_lane_sync=0 , jesd_commaalign_ena=1 devmem 0x43c500DC 32 0x500000 # 56 , adjcnt_link0 , adjdir_link0 , bid_link0 , cf_link0 , cs_link0 devmem 0x43c500E0 32 0x5100FF # 57 , did_link0 , sync_request_ena_link0 devmem 0x43c500E4 32 0x5200FF # 58 , disable_err_report_link0 , phadj_link0 , error_ena_link0 devmem 0x43c500E8 32 0x530000 # 59 , adjcnt_link1 , adjdir_link1 , bid_link1 , cf_link1 , cs_link1 devmem 0x43c500EC 32 0x5400FF # 60 , did_link1 , sync_request_ena_link1 devmem 0x43c500F0 32 0x5500FF # 61 , disable_err_report_link1 , phadj_link1 , error_ena_link1 devmem 0x43c500F4 32 0x560000 # 62 , adjcnt_link2 , adjdir_link2 , bid_link2 , cf_link2 , cs_link2 devmem 0x43c500F8 32 0x5700FF # 63 , did_link2 , sync_request_ena_link2 devmem 0x43c500FC 32 0x5800FF # 64 , disable_err_report_link2 , phadj_link2 , error_ena_link2 devmem 0x43c50100 32 0x590000 # 65 , adjcnt_link3 , adjdir_link3 , bid_link3 , cf_link3 , cs_link3 devmem 0x43c50104 32 0x5A00FF # 66 , did_link3 , sync_request_ena_link3 devmem 0x43c50108 32 0x5B00FF # 67 , disable_err_report_link3 , phadj_link3 , error_ena_link3 # devmem 0x43c5010C 32 0x5C1111 # 68 , err_cnt_clr_link3 , sysref_mode_link3 , err_cnt_clr_link2 , sysref_mode_link2 , err_cnt_clr_link1=0 , sysref_mode_link1=001 , err_cnt_clr_link0=0 , sysref_mode_link0=001 # devmem 0x43c5010C 32 0x5C0000 # 68 , err_cnt_clr_link3 , sysref_mode_link3 , err_cnt_clr_link2 , sysref_mode_link2 , err_cnt_clr_link1=0 , sysref_mode_link1=000 , err_cnt_clr_link0=0 , sysref_mode_link0=000 devmem 0x43c5010C 32 0x5C3333 # 68 , err_cnt_clr_link3 , sysref_mode_link3 , err_cnt_clr_link2 , sysref_mode_link2 , err_cnt_clr_link1=0 , sysref_mode_link1=011 , err_cnt_clr_link0=0 , sysref_mode_link0=011 # devmem 0x43c50110 32 0x61000F # 69 , syncn_pol=0 , syncncd_sel=0000 , syncnab_sel=0000 , syncn_sel=1111 devmem 0x43c50110 32 0x610001 # 69 , syncn_pol=0 , syncncd_sel=0000 , syncnab_sel=0000 , syncn_sel=0001 devmem 0x43c50114 32 0x1F9982 # 70 , syncsel_mixerab=auto-sync/sif_sync , syncsel_mixercd=auto-sync/sif_sync , syncsel_nco=sif_sync , sif_sync=1 devmem 0x43c50118 32 0x6E0000 # 71 , sfrac_coef0_ab , sfrac_coef1_ab , sfrac_coef2_ab devmem 0x43c5011C 32 0x6F0000 # 72 , sfrac_coef3_ab devmem 0x43c50120 32 0x700000 # 73 , sfrac_coef4_ab(15:0) devmem 0x43c50124 32 0x710000 # 74 , sfrac_coef4_ab(18:16) , sfrac_coef5_ab devmem 0x43c50128 32 0x720000 # 75 , sfrac_coef6_ab devmem 0x43c5012C 32 0x730000 # 76 , sfrac_coef7_ab , sfrac_coef8_ab , sfrac_coef9_ab devmem 0x43c50130 32 0x740000 # 77 , sfrac_invgain_ab(15:0) devmem 0x43c50134 32 0x750000 # 78 , sfrac_invgain_ab(19:16) , lfras_coefsel_a , lfras_coefsel_b devmem 0x43c50138 32 0x760000 # 79 , sfrac_coef0_cd , sfrac_coef1_cd , sfrac_coef2_cd devmem 0x43c5013C 32 0x770000 # 80 , sfrac_coef3_cd devmem 0x43c50140 32 0x780000 # 81 , sfrac_coef4_cd(15:0) devmem 0x43c50144 32 0x790000 # 82 , sfrac_coef4_cd(18:16) , sfrac_coef5_cd devmem 0x43c50148 32 0x7A0000 # 83 , sfrac_coef6_cd devmem 0x43c5014C 32 0x7B0000 # 84 , sfrac_coef7_cd , sfrac_coef8_cd , sfrac_coef9_cd devmem 0x43c50150 32 0x7C0000 # 85 , sfrac_invgain_cd(15:0) devmem 0x43c50154 32 0x7D0000 # 86 , sfrac_invgain_cd(19:16) , lfras_coefsel_c , lfras_coefsel_d devmem 0x43c50158 32 0x1F9980 # 87 , syncsel_mixerab=auto-sync/sif_sync , syncsel_mixercd=auto-sync/sif_sync , syncsel_nco=sif_sync , sif_sync=0 devmem 0x43c5015C 32 0x4AFF01 # 88 # 50 , lane_ena=11111111 , jesd_test_seq=0 , dual=0 , init_state=0000 , jesd_reset_n=1 devmem 0x43c50160 32 0x03F381 # 89 # 04 , coarse_dac=1111 , fifo_error_zeros_data_ena=1 , sif_txenable=1 devmem 0x43c50164 32 0x640000 # 90 , write to clear , alarm_l_error(0) , alarm_fifo_flags(0) devmem 0x43c50168 32 0x650000 # 91 , write to clear , alarm_l_error(1) , alarm_fifo_flags(1) devmem 0x43c5016C 32 0x660000 # 92 , write to clear , alarm_l_error(2) , alarm_fifo_flags(2) devmem 0x43c50170 32 0x670000 # 93 , write to clear , alarm_l_error(3) , alarm_fifo_flags(3) devmem 0x43c50174 32 0x680000 # 94 , write to clear , alarm_l_error(4) , alarm_fifo_flags(4) devmem 0x43c50178 32 0x690000 # 95 , write to clear , alarm_l_error(5) , alarm_fifo_flags(5) devmem 0x43c5017C 32 0x6A0000 # 96 , write to clear , alarm_l_error(6) , alarm_fifo_flags(6) devmem 0x43c50180 32 0x6B0000 # 97 , write to clear , alarm_l_error(7) , alarm_fifo_flags(7) devmem 0x43c50184 32 0x6C0000 # 98 , write to clear , alarm_sysref_err , alarm_pap , alarm_rw0_pll , alarm_rw1_pll , alarm_from_pll devmem 0x43c50188 32 0x6D0000 # 99 , alarm_from_shorttest , memin_rw_losdct