/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2013
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
* ============================================================================
Example to show the performance of Multicore Navigator on KeyStone DSP
* ============================================================================
*/

#include <stdio.h>
#include <string.h>
#include <c6x.h>
#include <csl_cacheAux.h>
#include <csl_cache.h>
#include <csl_qm_queue.h>
#include "K2_common.h"
#include "K2_Board_Init.h"
#include "MNav_Test.h"

void main()
{   
	int i;

	//Configure L1 as 32KB cache, L2 cache 256KB
	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_32KCACHE);
	CACHE_setL2Size(CACHE_256KCACHE);

	TSC_init();
#if 0
	//DSP core speed= MAIN_PLL_REF_CLK_MHZ*MAIN_PLL_MULTIPLIER/MAIN_PLL_DIVISOR
	KeyStone_main_PLL_init(MAIN_PLL_REF_CLK_MHZ, MAIN_PLL_MULTIPLIER, MAIN_PLL_DIVISOR);

	//DDR configuration
	K2_DDR3A_config(NULL, NULL);
	K2_DDR3B_config(NULL, NULL);
#endif

	/*make other cores local memory cacheable and prefetchable*/
	for(i=16; i<24; i++)
		gCGEM_Regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);	

	/*make other space non-cacheable and non-prefetchable*/
	for(i=24; i<128; i++)
		gCGEM_Regs->MAR[i]=0;	

	/*make DDR cacheable and prefetchable*/
	for(i=128; i<256; i++)
		gCGEM_Regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);	

	QMSS_init();
	QMSS_PktDMA_init();

	/* Initialize Time stamp counter to measure cycles*/
	TSC_init();

	puts("test Packet DMA1 in QMSS");
    PktDmaTest();

	puts("Test complete");
	puts("DSP code exit");

	while(1);

    return;
}

