/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2013
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
Interrupts configuration for QMSS
 * =============================================================================
 *  Revision History
 *  ===============
 *  Feb 5, 2013 Brighton  file created
 * =============================================================================
 */

#include <stdio.h>
#include <c6x.h> 
#include <csl_cpintc.h>
#include "K2_common.h"

int uiQ_pend_host_event_num;
int uiLow_pri_Q_host_event_num;

void CIC_Init_QM(void)
{
	/* Disable Global host interrupts. */
	gCIC0_Regs->GLOBAL_ENABLE_HINT_REG= 0;

	uiQ_pend_host_event_num= 16;
	/*map Queue 662 pend interrupts events to CIC0 out16*/
	KeyStone_CIC_event_map(gCIC0_Regs, CSL_CIC0_QMSS_QUE_PEND_662, uiQ_pend_host_event_num);
#ifdef CSL_CIC0_QMSS_QUE_PEND_8854
	/*map Queue 8854 pend interrupts events to CIC0 out16*/
	KeyStone_CIC_event_map(gCIC0_Regs, CSL_CIC0_QMSS_QUE_PEND_8854, uiQ_pend_host_event_num);
#endif
	uiLow_pri_Q_host_event_num= 18;
	/*map INTD1 low priority queue channel 0 interrupt event to CIC0 out 18*/
	KeyStone_CIC_event_map(gCIC0_Regs, CSL_CIC0_QMSS_INTD_1_LOW_0, uiLow_pri_Q_host_event_num);
#ifdef CSL_CIC0_QMSS_INTD_2_LOW_0
	/*map INTD2 low priority queue channel 0 interrupt event to CIC0 out 19*/
	KeyStone_CIC_event_map(gCIC0_Regs, CSL_CIC0_QMSS_INTD_2_LOW_0, uiLow_pri_Q_host_event_num+1);
#endif

	/* Enable Global host interrupts. */
	gCIC0_Regs->GLOBAL_ENABLE_HINT_REG= 1;

}

void QM_Interrupts_Init(void)
{
	CIC_Init_QM();
	
	//map INTD1 high priority queue channel 0 interrupt to INT4
	//map INTD2 high priority queue channel 0 interrupt to INT5
	//map INTD1 low priority queues channel 0 interrupt to INT6
	//map INTD2 low priority queues channel 0 interrupt to INT7
	gCGEM_Regs->INTMUX1 = (CSL_C66X_COREPAC_QMSS_INTD_1_HIGH_N<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)|
		(CSL_C66X_COREPAC_QMSS_INTD_2_HIGH_N<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)|
		(CSL_C66X_COREPAC_CIC_OUT18<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT)|
		(CSL_C66X_COREPAC_CIC_OUT19<<CSL_CGEM_INTMUX1_INTSEL7_SHIFT);

	/*on K2K/K2H, CIC0 out16 event number are 32 on core,
	map this event 32 to INT8 */
	gCGEM_Regs->INTMUX2 = (CSL_C66X_COREPAC_CIC_OUT16<<CSL_CGEM_INTMUX2_INTSEL8_SHIFT);

	 /*Clear all DSP core events*/
	gCGEM_Regs->EVTCLR[0]= 	0xFFFFFFFF;
	gCGEM_Regs->EVTCLR[1]= 	0xFFFFFFFF;
	gCGEM_Regs->EVTCLR[2]= 	0xFFFFFFFF;
	gCGEM_Regs->EVTCLR[3]= 	0xFFFFFFFF;

	//clear DSP core interrupt flag
	ICR= IFR;

	//enable INT4, 5, 6
	IER = 3|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8);

	/*Interrupt Service Table Pointer to begining of LL2 memory*/
	ISTP= 0x800000;

	//enable GIE
	TSR = TSR|1;
}


