
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2013
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
* ============================================================================
Example to show the initialization of Multicore Navigator on KeyStone DSP
* =============================================================================
 *  Revision History
 *  ===============
 *  Feb 5, 2013 Brighton Feng   File Created
 * ============================================================================
 */

#include <stdio.h>
#include <string.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_qm_queue.h>
#include "MNav_init.h"
#ifdef _BIG_ENDIAN
#ifdef ACC_48_CHANNEL
#include <ti/drv/qmss/firmware/acc48_be_bin.h>
#else
#include <ti/drv/qmss/firmware/acc32_be_bin.h>
#include <ti/drv/qmss/firmware/acc16_be_bin.h>
#endif
#else
#ifdef ACC_48_CHANNEL
#include <ti/drv/qmss/firmware/acc48_le_bin.h>
#else
#include <ti/drv/qmss/firmware/acc32_le_bin.h>
#include <ti/drv/qmss/firmware/acc16_le_bin.h>
#endif
#endif

#if (TOTAL_LINKING_ENTRY_SIZE>NUM_INTERNAL_LINKING_ENTRY)
#pragma DATA_SECTION(linkingRAM1,"QMSS_Data.linkingRAM1")
#pragma DATA_ALIGN (linkingRAM1, 16)
unsigned long long linkingRAM1[LINKING_RAM1_SIZE];
#endif

#pragma DATA_SECTION(hostDescriptor_SL2,"QMSS_Data.Descriptor_SL2")
#pragma DATA_ALIGN (hostDescriptor_SL2, 128)
Uint8 hostDescriptor_SL2[SL2_HOST_DESCRIPTOR_NUM][HOST_DESCRIPTOR_SIZE];

#pragma DATA_SECTION(packetBuffer_SL2_Size0,"PacketData.buffer_SL2")
#pragma DATA_SECTION(packetBuffer_SL2_Size1,"PacketData.buffer_SL2")
#pragma DATA_SECTION(packetBuffer_SL2_Size2,"PacketData.buffer_SL2")
#pragma DATA_SECTION(packetBuffer_SL2_Size3,"PacketData.buffer_SL2")
Uint8 packetBuffer_SL2_Size0[SL2_SIZE0_PKT_BUF_NUM][SL2_PACKET_BUFFER_SIZE0];
Uint8 packetBuffer_SL2_Size1[SL2_SIZE1_PKT_BUF_NUM][SL2_PACKET_BUFFER_SIZE1];
Uint8 packetBuffer_SL2_Size2[SL2_SIZE2_PKT_BUF_NUM][SL2_PACKET_BUFFER_SIZE2];
Uint8 packetBuffer_SL2_Size3[SL2_SIZE3_PKT_BUF_NUM][SL2_PACKET_BUFFER_SIZE3];

#pragma DATA_SECTION(monoDescriptor_SL2,"QMSS_Data.Descriptor_SL2")
#pragma DATA_ALIGN (monoDescriptor_SL2, 128)
Uint8 monoDescriptor_SL2[SL2_MONO_DESCRIPTOR_NUM][L2_MONO_DESCRIPTOR_SIZE];

#pragma DATA_SECTION(hostDescriptor_LL2,"QMSS_Data.Descriptor_LL2")
#pragma DATA_ALIGN (hostDescriptor_LL2, 64)
Uint8 hostDescriptor_LL2[LL2_HOST_DESCRIPTOR_NUM][HOST_DESCRIPTOR_SIZE];

#pragma DATA_SECTION(packetBuffer_LL2_Size0,"PacketData.buffer_LL2")
#pragma DATA_SECTION(packetBuffer_LL2_Size1,"PacketData.buffer_LL2")
#pragma DATA_SECTION(packetBuffer_LL2_Size2,"PacketData.buffer_LL2")
#pragma DATA_SECTION(packetBuffer_LL2_Size3,"PacketData.buffer_LL2")
Uint8 packetBuffer_LL2_Size0[LL2_SIZE0_PKT_BUF_NUM][LL2_PACKET_BUFFER_SIZE0];
Uint8 packetBuffer_LL2_Size1[LL2_SIZE1_PKT_BUF_NUM][LL2_PACKET_BUFFER_SIZE1];
Uint8 packetBuffer_LL2_Size2[LL2_SIZE2_PKT_BUF_NUM][LL2_PACKET_BUFFER_SIZE2];
Uint8 packetBuffer_LL2_Size3[LL2_SIZE3_PKT_BUF_NUM][LL2_PACKET_BUFFER_SIZE3];

#pragma DATA_SECTION(monoDescriptor_LL2,"QMSS_Data.Descriptor_LL2")
#pragma DATA_ALIGN (monoDescriptor_LL2, 64)
Uint8 monoDescriptor_LL2[LL2_MONO_DESCRIPTOR_NUM][L2_MONO_DESCRIPTOR_SIZE];

#pragma DATA_SECTION(hostDescriptor_DDR,"QMSS_Data.Descriptor_DDR")
#pragma DATA_ALIGN (hostDescriptor_DDR, 128)
Uint8 hostDescriptor_DDR[DDR_HOST_DESCRIPTOR_NUM][HOST_DESCRIPTOR_SIZE];

#pragma DATA_SECTION(packetBuffer_DDR_Size0,"PacketData.buffer_DDR")
#pragma DATA_SECTION(packetBuffer_DDR_Size1,"PacketData.buffer_DDR")
#pragma DATA_SECTION(packetBuffer_DDR_Size2,"PacketData.buffer_DDR")
#pragma DATA_SECTION(packetBuffer_DDR_Size3,"PacketData.buffer_DDR")
Uint8 packetBuffer_DDR_Size0[DDR_SIZE0_PKT_BUF_NUM][DDR_PACKET_BUFFER_SIZE0];
Uint8 packetBuffer_DDR_Size1[DDR_SIZE1_PKT_BUF_NUM][DDR_PACKET_BUFFER_SIZE1];
Uint8 packetBuffer_DDR_Size2[DDR_SIZE2_PKT_BUF_NUM][DDR_PACKET_BUFFER_SIZE2];
Uint8 packetBuffer_DDR_Size3[DDR_SIZE3_PKT_BUF_NUM][DDR_PACKET_BUFFER_SIZE3];

#pragma DATA_SECTION(monoDescriptor_DDR,"QMSS_Data.Descriptor_DDR")
#pragma DATA_ALIGN (monoDescriptor_DDR, 128)
Uint8 monoDescriptor_DDR[DDR_MONO_DESCRIPTOR_NUM][DDR_MONO_DESCRIPTOR_SIZE];

/* descriptor memory region configuration.
descriptor Base address must be specified in ascending order,
no overlap is allowed between regions*/
Qmss_DescMemRegionCfg descMemRegionsCfg[]=
{   /*The base address of descriptor region     Size of each descriptor     Number of descriptors 
                                                16*n,1<=n<=8192             2^(5+n), 0<=n<=15*/
    {(Uint32)hostDescriptor_SL2,                HOST_DESCRIPTOR_SIZE,       SL2_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in SL2*/
    {(Uint32)monoDescriptor_SL2,                L2_MONO_DESCRIPTOR_SIZE,    SL2_MONO_DESC_LINK_ENTRY_NUM},/*Monolithic descriptor in SL2*/
    {((Uint32)hostDescriptor_LL2)+0x10000000,   HOST_DESCRIPTOR_SIZE,       LL2_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in Core0 LL2*/
    {((Uint32)monoDescriptor_LL2)+0x10000000,   L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESC_LINK_ENTRY_NUM},/*Monolithic descriptor in Core0 LL2*/
    {((Uint32)hostDescriptor_LL2)+0x11000000,   HOST_DESCRIPTOR_SIZE,       LL2_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in Core1 LL2*/
    {((Uint32)monoDescriptor_LL2)+0x11000000,   L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESC_LINK_ENTRY_NUM},/*Monolithic descriptor in Core1 LL2*/
    {((Uint32)hostDescriptor_LL2)+0x12000000,   HOST_DESCRIPTOR_SIZE,       LL2_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in Core2 LL2*/
    {((Uint32)monoDescriptor_LL2)+0x12000000,   L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESC_LINK_ENTRY_NUM},/*Monolithic descriptor in Core2 LL2*/
    {((Uint32)hostDescriptor_LL2)+0x13000000,   HOST_DESCRIPTOR_SIZE,       LL2_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in Core3 LL2*/
    {((Uint32)monoDescriptor_LL2)+0x13000000,   L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESC_LINK_ENTRY_NUM},/*Monolithic descriptor in Core3 LL2*/
    {(Uint32)hostDescriptor_DDR,                HOST_DESCRIPTOR_SIZE,       DDR_HOST_DESC_LINK_ENTRY_NUM},/*host descriptor in DDR*/
    {(Uint32)monoDescriptor_DDR,                DDR_MONO_DESCRIPTOR_SIZE,   DDR_MONO_DESC_LINK_ENTRY_NUM}/*Monolithic descriptor in DDR*/
};

FreeHostQueueCfg freeHostQueueCfgTable[]=
{
    /*free queue number*/       /*address of first descriptor*/                                         /*size of descriptor*/  /*number of descriptors*/   /*address of first buffer*/                     /*size of each buffer*/ 
    {SL2_HOST_SIZE0_FDQ,        (Uint32)&hostDescriptor_SL2[0][0],                                      HOST_DESCRIPTOR_SIZE,   SL2_SIZE0_PKT_BUF_NUM,      (Uint32)packetBuffer_SL2_Size0,                 SL2_PACKET_BUFFER_SIZE0},/*SL2 Size0 host Free Descriptor Queue*/
    {SL2_HOST_SIZE1_FDQ,        (Uint32)&hostDescriptor_SL2[SL2_SIZE1_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   SL2_SIZE1_PKT_BUF_NUM,      (Uint32)packetBuffer_SL2_Size1,                 SL2_PACKET_BUFFER_SIZE1},/*SL2 Size1 host Free Descriptor Queue*/
    {SL2_HOST_SIZE2_FDQ,        (Uint32)&hostDescriptor_SL2[SL2_SIZE2_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   SL2_SIZE2_PKT_BUF_NUM,      (Uint32)packetBuffer_SL2_Size2,                 SL2_PACKET_BUFFER_SIZE2},/*SL2 Size2 host Free Descriptor Queue*/
    {SL2_HOST_SIZE3_FDQ,        (Uint32)&hostDescriptor_SL2[SL2_SIZE3_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   SL2_SIZE3_PKT_BUF_NUM,      (Uint32)packetBuffer_SL2_Size3,                 SL2_PACKET_BUFFER_SIZE3},/*SL2 Size3 host Free Descriptor Queue*/
    {SL2_NO_BUF_HOST_FDQ,       (Uint32)&hostDescriptor_SL2[SL2_NO_BUF_DESC_START_IDX][0],              HOST_DESCRIPTOR_SIZE,   SL2_NO_BUF_DESCRIPTOR_NUM,  0,                                              0},         /*SL2 no buffer host Free Descriptor Queue*/

    {CORE0_LL2_HOST_SIZE0_FDQ,  ((Uint32)&hostDescriptor_LL2[0][0])+0x10000000,                         HOST_DESCRIPTOR_SIZE,   LL2_SIZE0_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size0)+0x10000000,    LL2_PACKET_BUFFER_SIZE0},/*CORE0 LL2 Size0 host Free Descriptor Queue*/
    {CORE0_LL2_HOST_SIZE1_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE1_DESC_START_IDX][0])+0x10000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE1_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size1)+0x10000000,    LL2_PACKET_BUFFER_SIZE1},/*CORE0 LL2 Size1 host Free Descriptor Queue*/
    {CORE0_LL2_HOST_SIZE2_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE2_DESC_START_IDX][0])+0x10000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE2_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size2)+0x10000000,    LL2_PACKET_BUFFER_SIZE2},/*CORE0 LL2 Size2 host Free Descriptor Queue*/
    {CORE0_LL2_HOST_SIZE3_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE3_DESC_START_IDX][0])+0x10000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE3_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size3)+0x10000000,    LL2_PACKET_BUFFER_SIZE3},/*CORE0 LL2 Size3 host Free Descriptor Queue*/
    {CORE0_LL2_NO_BUF_HOST_FDQ, ((Uint32)&hostDescriptor_LL2[LL2_NO_BUF_DESC_START_IDX][0])+0x10000000, HOST_DESCRIPTOR_SIZE,   LL2_NO_BUF_DESCRIPTOR_NUM,  0,                                              0},         /*CORE0 LL2 no buffer host Free Descriptor Queue*/

    {CORE1_LL2_HOST_SIZE0_FDQ,  ((Uint32)&hostDescriptor_LL2[0][0])+0x11000000,                         HOST_DESCRIPTOR_SIZE,   LL2_SIZE0_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size0)+0x11000000,    LL2_PACKET_BUFFER_SIZE0},/*CORE1 LL2 Size0 host Free Descriptor Queue*/
    {CORE1_LL2_HOST_SIZE1_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE1_DESC_START_IDX][0])+0x11000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE1_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size1)+0x11000000,    LL2_PACKET_BUFFER_SIZE1},/*CORE1 LL2 Size1 host Free Descriptor Queue*/
    {CORE1_LL2_HOST_SIZE2_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE2_DESC_START_IDX][0])+0x11000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE2_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size2)+0x11000000,    LL2_PACKET_BUFFER_SIZE2},/*CORE1 LL2 Size2 host Free Descriptor Queue*/
    {CORE1_LL2_HOST_SIZE3_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE3_DESC_START_IDX][0])+0x11000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE3_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size3)+0x11000000,    LL2_PACKET_BUFFER_SIZE3},/*CORE1 LL2 Size3 host Free Descriptor Queue*/
    {CORE1_LL2_NO_BUF_HOST_FDQ, ((Uint32)&hostDescriptor_LL2[LL2_NO_BUF_DESC_START_IDX][0])+0x11000000, HOST_DESCRIPTOR_SIZE,   LL2_NO_BUF_DESCRIPTOR_NUM,  0,                                              0},         /*CORE1 LL2 no buffer host Free Descriptor Queue*/

    {CORE2_LL2_HOST_SIZE0_FDQ,  ((Uint32)&hostDescriptor_LL2[0][0])+0x12000000,                         HOST_DESCRIPTOR_SIZE,   LL2_SIZE0_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size0)+0x12000000,    LL2_PACKET_BUFFER_SIZE0},/*CORE2 LL2 Size0 host Free Descriptor Queue*/
    {CORE2_LL2_HOST_SIZE1_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE1_DESC_START_IDX][0])+0x12000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE1_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size1)+0x12000000,    LL2_PACKET_BUFFER_SIZE1},/*CORE2 LL2 Size1 host Free Descriptor Queue*/
    {CORE2_LL2_HOST_SIZE2_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE2_DESC_START_IDX][0])+0x12000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE2_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size2)+0x12000000,    LL2_PACKET_BUFFER_SIZE2},/*CORE2 LL2 Size2 host Free Descriptor Queue*/
    {CORE2_LL2_HOST_SIZE3_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE3_DESC_START_IDX][0])+0x12000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE3_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size3)+0x12000000,    LL2_PACKET_BUFFER_SIZE3},/*CORE2 LL2 Size3 host Free Descriptor Queue*/
    {CORE2_LL2_NO_BUF_HOST_FDQ, ((Uint32)&hostDescriptor_LL2[LL2_NO_BUF_DESC_START_IDX][0])+0x12000000, HOST_DESCRIPTOR_SIZE,   LL2_NO_BUF_DESCRIPTOR_NUM,  0,                                              0},         /*CORE2 LL2 no buffer host Free Descriptor Queue*/

    {CORE3_LL2_HOST_SIZE0_FDQ,  ((Uint32)&hostDescriptor_LL2[0][0])+0x13000000,                         HOST_DESCRIPTOR_SIZE,   LL2_SIZE0_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size0)+0x13000000,    LL2_PACKET_BUFFER_SIZE0},/*CORE3 LL2 Size0 host Free Descriptor Queue*/
    {CORE3_LL2_HOST_SIZE1_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE1_DESC_START_IDX][0])+0x13000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE1_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size1)+0x13000000,    LL2_PACKET_BUFFER_SIZE1},/*CORE3 LL2 Size1 host Free Descriptor Queue*/
    {CORE3_LL2_HOST_SIZE2_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE2_DESC_START_IDX][0])+0x13000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE2_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size2)+0x13000000,    LL2_PACKET_BUFFER_SIZE2},/*CORE3 LL2 Size2 host Free Descriptor Queue*/
    {CORE3_LL2_HOST_SIZE3_FDQ,  ((Uint32)&hostDescriptor_LL2[LL2_SIZE3_DESC_START_IDX][0])+0x13000000,  HOST_DESCRIPTOR_SIZE,   LL2_SIZE3_PKT_BUF_NUM,      ((Uint32)packetBuffer_LL2_Size3)+0x13000000,    LL2_PACKET_BUFFER_SIZE3},/*CORE3 LL2 Size3 host Free Descriptor Queue*/
    {CORE3_LL2_NO_BUF_HOST_FDQ, ((Uint32)&hostDescriptor_LL2[LL2_NO_BUF_DESC_START_IDX][0])+0x13000000, HOST_DESCRIPTOR_SIZE,   LL2_NO_BUF_DESCRIPTOR_NUM,  0,                                              0},         /*CORE3 LL2 no buffer host Free Descriptor Queue*/

    {DDR_HOST_SIZE0_FDQ,        (Uint32)&hostDescriptor_DDR[0][0],                                      HOST_DESCRIPTOR_SIZE,   DDR_SIZE0_PKT_BUF_NUM,      (Uint32)packetBuffer_DDR_Size0,                 DDR_PACKET_BUFFER_SIZE0},/*DDR Size0 host Free Descriptor Queue*/
    {DDR_HOST_SIZE1_FDQ,        (Uint32)&hostDescriptor_DDR[DDR_SIZE1_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   DDR_SIZE1_PKT_BUF_NUM,      (Uint32)packetBuffer_DDR_Size1,                 DDR_PACKET_BUFFER_SIZE1},/*DDR Size1 host Free Descriptor Queue*/
    {DDR_HOST_SIZE2_FDQ,        (Uint32)&hostDescriptor_DDR[DDR_SIZE2_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   DDR_SIZE2_PKT_BUF_NUM,      (Uint32)packetBuffer_DDR_Size2,                 DDR_PACKET_BUFFER_SIZE2},/*DDR Size2 host Free Descriptor Queue*/
    {DDR_HOST_SIZE3_FDQ,        (Uint32)&hostDescriptor_DDR[DDR_SIZE3_DESC_START_IDX][0],               HOST_DESCRIPTOR_SIZE,   DDR_SIZE3_PKT_BUF_NUM,      (Uint32)packetBuffer_DDR_Size3,                 DDR_PACKET_BUFFER_SIZE3},/*DDR Size3 host Free Descriptor Queue*/
    {DDR_NO_BUF_HOST_FDQ,       (Uint32)&hostDescriptor_DDR[DDR_NO_BUF_DESC_START_IDX][0],              HOST_DESCRIPTOR_SIZE,   DDR_NO_BUF_DESCRIPTOR_NUM,  0,                                              0}          /*DDR no buffer host Free Descriptor Queue*/
};

FreeMonoQueueCfg freeMonoQueueCfgTable[]=
{
    /*free queue number*/       /*address of first descriptor*/                                 /*size of descriptor*/      /*number of descriptors*/
    {SL2_MONOLITHIC_FDQ,        (Uint32)monoDescriptor_SL2,                                     L2_MONO_DESCRIPTOR_SIZE,    SL2_MONO_DESCRIPTOR_NUM},/*SL2 monolithic Free Descriptor Queue*/
    {CORE0_LL2_MONOLITHIC_FDQ,  ((Uint32)monoDescriptor_LL2)+0x10000000,                        L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESCRIPTOR_NUM},/*CORE0_LL2 monolithic Free Descriptor Queue*/
    {CORE1_LL2_MONOLITHIC_FDQ,  ((Uint32)monoDescriptor_LL2)+0x11000000,                        L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESCRIPTOR_NUM},/*CORE1_LL2 monolithic Free Descriptor Queue*/
    {CORE2_LL2_MONOLITHIC_FDQ,  ((Uint32)monoDescriptor_LL2)+0x12000000,                        L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESCRIPTOR_NUM},/*CORE2_LL2 monolithic Free Descriptor Queue*/
    {CORE3_LL2_MONOLITHIC_FDQ,  ((Uint32)monoDescriptor_LL2)+0x13000000,                        L2_MONO_DESCRIPTOR_SIZE,    LL2_MONO_DESCRIPTOR_NUM},/*CORE3_LL2 monolithic Free Descriptor Queue*/
    {DDR_MONO_LINK_RAM0_FDQ,    (Uint32)monoDescriptor_DDR,                                     DDR_MONO_DESCRIPTOR_SIZE,   DDR_MONO_LINKING_RAM0_DESC_NUM},/*DDR monolithic Free Descriptor Queue*/
    {DDR_MONO_LINK_RAM1_FDQ,    (Uint32)&monoDescriptor_DDR[DDR_MONO_LINKING_RAM0_DESC_NUM][0], DDR_MONO_DESCRIPTOR_SIZE,   DDR_MONO_LINKING_RAM1_DESC_NUM}/*DDR monolithic Free Descriptor Queue*/
};

PktDma_RxFlowCfg flowCfgTable[]=
{
    /*dest_qnum*/   /*sop_offset*/  /*ps_loc*/  /*desc_type*/   /*error retry*/ /*psinfo*/  /*einfo*/   /*size_thresh0(1,2)_en*/    /*size_thresh0*/    /*size_thresh1*/    /*size_thresh2*/    /*fdq0_sz0_qnum*/       /*fdq0_sz1_qnum*/           /*fdq0_sz2_qnum*/           /*fdq0_sz3_qnum*/           /*fdq1_qnum*/           /*fdq2_qnum*/           /*fdq3_qnum*/   /*dest_tag_lo*/ /*dest_tag_hi*/ /*src_tag_lo*/  /*src_tag_hi*/  /*dest_tag_lo_sel*/ /*dest_tag_hi_sel*/ /*src_tag_lo_sel*/  /*src_tag_hi_sel*/
    {PKT_DMA_TEST_DST_Q,    0,      0,      Cppi_DescType_HOST,     0,          0,          0,          1, 1, 1,    LL2_PACKET_BUFFER_SIZE0, LL2_PACKET_BUFFER_SIZE1, LL2_PACKET_BUFFER_SIZE2, CORE3_LL2_HOST_SIZE0_FDQ, CORE3_LL2_HOST_SIZE1_FDQ, CORE3_LL2_HOST_SIZE2_FDQ, CORE3_LL2_HOST_SIZE3_FDQ, CORE3_LL2_HOST_SIZE3_FDQ, CORE3_LL2_HOST_SIZE3_FDQ, CORE3_LL2_HOST_SIZE3_FDQ,    0,      0,              0,              0,              0,                  0,                  0,                  0},
    {PKT_DMA_TEST_DST_Q,    0,      0,      Cppi_DescType_HOST,     0,          0,          0,          1, 1, 1,    SL2_PACKET_BUFFER_SIZE0, SL2_PACKET_BUFFER_SIZE1, SL2_PACKET_BUFFER_SIZE2, SL2_HOST_SIZE0_FDQ,          SL2_HOST_SIZE1_FDQ,     SL2_HOST_SIZE2_FDQ,         SL2_HOST_SIZE3_FDQ,         SL2_HOST_SIZE3_FDQ,     SL2_HOST_SIZE3_FDQ,     SL2_HOST_SIZE3_FDQ,         0,      0,              0,              0,              0,                  0,                  0,                  0},
    {PKT_DMA_TEST_DST_Q,    0,      0,      Cppi_DescType_HOST,     0,          0,          0,          1, 1, 1,    DDR_PACKET_BUFFER_SIZE0, DDR_PACKET_BUFFER_SIZE1, DDR_PACKET_BUFFER_SIZE2, DDR_HOST_SIZE0_FDQ,          DDR_HOST_SIZE1_FDQ,     DDR_HOST_SIZE2_FDQ,         DDR_HOST_SIZE3_FDQ,         DDR_HOST_SIZE3_FDQ,     DDR_HOST_SIZE3_FDQ,     DDR_HOST_SIZE3_FDQ,         0,      0,              0,              0,              0,                  0,                  0,                  0},
    {PKT_DMA_TEST_DST_Q,    12,     0,  Cppi_DescType_MONOLITHIC,   0,          0,          0,          0, 0, 0,                    0,                  0,                  0,              CORE3_LL2_MONOLITHIC_FDQ,   0,                          0,                          0,                      CORE3_LL2_MONOLITHIC_FDQ, CORE3_LL2_MONOLITHIC_FDQ, CORE3_LL2_MONOLITHIC_FDQ,   0,      0,              0,              0,              0,                  0,                  0,                  0},
    {PKT_DMA_TEST_DST_Q,    12,     0,  Cppi_DescType_MONOLITHIC,   0,          0,          0,          0, 0, 0,                    0,                  0,                  0,                  SL2_MONOLITHIC_FDQ,     0,                          0,                          0,                          SL2_MONOLITHIC_FDQ,     SL2_MONOLITHIC_FDQ,     SL2_MONOLITHIC_FDQ,         0,      0,              0,              0,              0,                  0,                  0,                  0},
    {PKT_DMA_TEST_DST_Q,    12,     0,  Cppi_DescType_MONOLITHIC,   0,          0,          0,          0, 0, 0,                    0,                  0,                  0,                  DDR_MONOLITHIC_FDQ,     0,                          0,                          0,                          DDR_MONOLITHIC_FDQ,     DDR_MONOLITHIC_FDQ,     DDR_MONOLITHIC_FDQ,         0,      0,              0,              0,              0,                  0,                  0,                  0}
};

Uint32 uiUsedDescRegionNum;
Uint32 uiInitialHostFdqNum;
Uint32 uiInitialMonoFdqNum;
Uint32 uiUsedRxFlowNum;

void QMSS_init()
{
	uiUsedDescRegionNum= sizeof(descMemRegionsCfg)/sizeof(Qmss_DescMemRegionCfg);
	uiInitialHostFdqNum= sizeof(freeHostQueueCfgTable)/sizeof(FreeHostQueueCfg);
	uiInitialMonoFdqNum= sizeof(freeMonoQueueCfgTable)/sizeof(FreeMonoQueueCfg);

	/*-----------------Queue manager configuration--------------------*/
	/*Two QM can be configured differently (split mode),
	for this test, the are configured same (shared mode)*/
#if (TOTAL_LINKING_ENTRY_SIZE>QMSS_NUM_INTERNAL_LINKING_ENTRY)
	KeyStone_QMSS_Linking_RAM_init(QMSS_QM1, QMSS_INTERNAL_LINKING_RAM_ADDRESS, 
		QMSS_NUM_INTERNAL_LINKING_ENTRY, (Uint32)linkingRAM1, LINKING_RAM1_SIZE);
	KeyStone_QMSS_Linking_RAM_init(QMSS_QM2, QMSS_INTERNAL_LINKING_RAM_ADDRESS, 
		QMSS_NUM_INTERNAL_LINKING_ENTRY, (Uint32)linkingRAM1, LINKING_RAM1_SIZE);
#else
	KeyStone_QMSS_Linking_RAM_init(QMSS_QM1, QMSS_INTERNAL_LINKING_RAM_ADDRESS, 
		QMSS_NUM_INTERNAL_LINKING_ENTRY, 0, 0);
	KeyStone_QMSS_Linking_RAM_init(QMSS_QM2, QMSS_INTERNAL_LINKING_RAM_ADDRESS, 
		QMSS_NUM_INTERNAL_LINKING_ENTRY, 0, 0);
#endif

	KeyStone_QMSS_Descriptor_Regions_init(QMSS_QM1, 0, 0, uiUsedDescRegionNum, descMemRegionsCfg);
	KeyStone_QMSS_Descriptor_Regions_init(QMSS_QM2, 0, 0, uiUsedDescRegionNum, descMemRegionsCfg);

	/*-----------------QMSS queue initialization------------------------*/
	KeyStone_Host_Descriptor_Queues_init(freeHostQueueCfgTable, uiInitialHostFdqNum);
	KeyStone_Mono_Descriptor_Queues_init(freeMonoQueueCfgTable, uiInitialMonoFdqNum);

	/*-----------------QMSS PDSP fireware configuration------------------*/
#ifdef _BIG_ENDIAN
#ifdef ACC_48_CHANNEL
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP1, &acc48_be, sizeof(acc48_be));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP3, &acc48_be, sizeof(acc48_be));
#else
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP1, &acc32_be, sizeof(acc32_be));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP2, &acc16_be, sizeof(acc16_be));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP3, &acc32_be, sizeof(acc32_be));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP4, &acc16_be, sizeof(acc16_be));
#endif
#else
#ifdef ACC_48_CHANNEL
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP1, &acc48_le, sizeof(acc48_le));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP3, &acc48_le, sizeof(acc48_le));
#else
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP1, &acc32_le, sizeof(acc32_le));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP2, &acc16_le, sizeof(acc16_le));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP3, &acc32_le, sizeof(acc32_le));
	KeyStone_Qmss_Download_Firmware(QMSS_PDSP4, &acc16_le, sizeof(acc16_le));
#endif
#endif
	gQM_INTD_Regs[0]->STATUS_CLR_REG0= 0xFFFFFFFF;
	gQM_INTD_Regs[0]->STATUS_CLR_REG1= 0xFFFF;
	gQM_INTD_Regs[1]->STATUS_CLR_REG0= 0xFFFFFFFF;
	gQM_INTD_Regs[1]->STATUS_CLR_REG1= 0xFFFF;

	KeyStone_Qmss_Config_Reclaim_Queue (QMSS_PDSP1, RECLAMATION_QUEUE);

}


void QMSS_PktDMA_init()
{
	int i;
	
	uiUsedRxFlowNum= sizeof(flowCfgTable)/sizeof(PktDma_RxFlowCfg);

	/*-----------------QMSS PktDMA configuration------------------*/
	KeyStone_pktDma_Global_Control(gQM_DMA_CfgRegs[0], 256, 5, 5);
	KeyStone_pktDma_Global_Control(gQM_DMA_CfgRegs[1], 256, 5, 5);

	for(i=0; i<8; i++)
	{
		KeyStone_pktDma_RxCh_enable(gQM_DMA_RxChCfgRegs[0], i);
		KeyStone_pktDma_TxCh_enable(gQM_DMA_TxChCfgRegs[0], i);
		KeyStone_pktDma_RxCh_enable(gQM_DMA_RxChCfgRegs[1], i);
		KeyStone_pktDma_TxCh_enable(gQM_DMA_TxChCfgRegs[1], i);
	}
	
	KeyStone_pktDma_configureRxFlow(
		gQM_DMA_RxFlowCfgRegs[0]->RX_FLOW_CONFIG, flowCfgTable, uiUsedRxFlowNum);
	KeyStone_pktDma_configureRxFlow(
		gQM_DMA_RxFlowCfgRegs[1]->RX_FLOW_CONFIG, flowCfgTable, uiUsedRxFlowNum);

}

void SRIO_PktDMA_init()
{
	int i;
	
	uiUsedRxFlowNum= sizeof(flowCfgTable)/sizeof(PktDma_RxFlowCfg);

	/*-----------------SRIO PktDMA configuration------------------*/
	KeyStone_pktDma_Global_Control(gSRIO_DMA_CfgRegs, 256, 5, 5);
	//set SRIO PktDMA in loopback mode for test
	gSRIO_DMA_CfgRegs->EMULATION_CONTROL_REG= 
		(Uint32)(1<<CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN_SHIFT);

	KeyStone_pktDma_RxCh_enable(gSRIO_DMA_RxChCfgRegs, 0);
	KeyStone_pktDma_TxCh_enable(gSRIO_DMA_TxChCfgRegs, 0);

	KeyStone_pktDma_configureRxFlow(
		gSRIO_DMA_RxFlowCfgRegs->RX_FLOW_CONFIG, flowCfgTable, uiUsedRxFlowNum);
}


void PA_PktDMA_init()
{
	int i;
	
	uiUsedRxFlowNum= sizeof(flowCfgTable)/sizeof(PktDma_RxFlowCfg);

	/*-----------------PA PktDMA configuration------------------*/
	KeyStone_pktDma_Global_Control(gNetCP_DMA_CfgRegs, 256, 5, 5);
	//set PA PktDMA in loopback mode for test
	gNetCP_DMA_CfgRegs->EMULATION_CONTROL_REG= 
		(Uint32)(1<<CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN_SHIFT);

	KeyStone_pktDma_RxCh_enable(gNetCP_DMA_RxChCfgRegs, 0);
	KeyStone_pktDma_TxCh_enable(gNetCP_DMA_TxChCfgRegs, 0);

	KeyStone_pktDma_configureRxFlow(
		gNetCP_DMA_RxFlowCfgRegs->RX_FLOW_CONFIG, flowCfgTable, uiUsedRxFlowNum);

}

/*check the descriptors in the queue, for debug purpose*/
void checkQueues()
{
	int i, j;
	Uint32 uiQuNum, uiEntryCount, uiDescriptorNumber, uiDescriptor;
	
	for(i=0; i<uiInitialHostFdqNum; i++)
	{
		uiQuNum= freeHostQueueCfgTable[i].uiFreeQuNum;
		uiEntryCount= gQueueStatusConfigRegs[uiQuNum].REG_A_EntryCount;
		uiDescriptorNumber= freeHostQueueCfgTable[i].uiDescriptorNumber;
		if(uiEntryCount!= uiDescriptorNumber)
		{
			printf("number of descriptors in host queue %d changed from %d to %d\n", 
				uiQuNum, uiDescriptorNumber, uiEntryCount);

			//printf some descriptors in the queue
			for(j= 0; j<uiEntryCount&&j<10; j++)
			{	
				uiDescriptor= gQueueManageRegs[uiQuNum].REG_D_Descriptor;
				printf("0x%x->", uiDescriptor);
				gQueueManageVBUSM[uiQuNum].REG_D_Descriptor= uiDescriptor;
			}
			if(j<10)
				puts("NULL");
			else
				puts("...");
		}
	}

	for(i=0; i<uiInitialMonoFdqNum; i++)
	{
		uiQuNum= freeMonoQueueCfgTable[i].uiFreeQuNum;
		uiEntryCount= gQueueStatusConfigRegs[uiQuNum].REG_A_EntryCount;
		uiDescriptorNumber= freeMonoQueueCfgTable[i].uiDescriptorNumber;
		if(uiEntryCount!= uiDescriptorNumber)
		{	
			printf("number of descriptors in mono queue %d changed from %d to %d\n", 
				uiQuNum, uiDescriptorNumber, uiEntryCount);

			//printf some descriptors in the queue
			for(j= 0; j<uiEntryCount&&j<10; j++)
			{	
				uiDescriptor= gQueueManageRegs[uiQuNum].REG_D_Descriptor;
				printf("0x%x->", uiDescriptor);
				gQueueManageVBUSM[uiQuNum].REG_D_Descriptor= uiDescriptor;
			}
			if(j<10)
				puts("NULL");
			else
				puts("...");
		}
	}

}



