ARM Cortex-A15 & DSP communication example on TCI6638EVM:

DSP will firstly initialize the PKTDMA and QMSS and wait the packets from ARM code by polling RX queue, ARM code will test for the memcopy and then fill the result in Descriptor¡¯s buffer and push the descriptor to the TX queue, then DSP will receive the packet and print out the ARM test results.

The ARM code compiled by CL470 compiler and DSP code compiled by C6000 CGT,  I compiled 2 projects in LE for the easy SoC bridge configuration and easy BCM configuration and execution on EVM.

The mainly execute procedures are:

1) Create TCI6638 EVM CCXML file with loading attached GEL file on DSP CoreX

2) Launch the debug session with this CCXML configuration file

3) Connect and load the DSP executable on DSP CoreX

4) Connect and Load the ARM executable on ARM Core0

5) Run the DSP executable first then run the ARM executable

The print info should as follow:
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[C66xx_0] test Packet DMA1 in QMSS
[CortexA15_1] MMU is enabled
------------ Non-cache VS Cache Cycle Test Begin ----------------
non-Dcacheable cycle is 286539
L1D-Cache Accesses = 4887
L2D-Cache Access = 137
L1D-Cache Read Misses = 25
L1D-Cache Write Misses = 26
L2D-Cache Read Misses = 41
L2D-Cache write Misses = 32
L1+L2 cacheable cycle is 7671
------------ Non-cache VS Cache Cycle Test End ----------------
Host descriptor address is 0x0C085400 
Host descriptor buffer ptr is 0x0C060000 
------------ Send test result from ARM to DSP ----------------
ARM code exit!
[C66xx_0] Receive descriptor address is 0x0C080000 
Receive to 0x0C000000 
Packet length is       28 
Bufer length is       28 
Descriptor type is        0 
Receive word 0 is 4887 
Receive word 1 is 137 
Receive word 2 is 25 
Receive word 3 is 26 
Receive word 4 is 41 
Receive word 5 is 32 
Receive word 6 is 7671 
Test complete
DSP code exit
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