/******************************************************************************
 *
 * SOC.h - SOC memory map header file
 *
 * Copyright (c) 2008-2013 Texas Instruments Incorporated.  All rights reserved.
 * Software License Agreement
 *
 * Texas Instruments (TI) is supplying this software for use solely and
 * exclusively on TI devices. The software is owned by TI and/or its
 * suppliers, and is protected under applicable patent and copyright laws.
 *
 * You may not combine this software with any open-source software if such
 * combination would cause this software to become subject to any of the
 * license terms applicable to such open source software.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 * DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************
 */
#ifndef _SOC_H_
#define _SOC_H_

#ifdef __cplusplus
extern "C"
{
#endif

/*  \brief Base address of AINTC memory mapped registers */
#define SOC_AINTC_REGS                       (0x48200000u)
#define SOC_MPUSS_CONF_BASE                  (0x48240000u)

/*  \brief Control module base address */
#define PADCTRL_BASE                         (0x48140000u)

/*  \brief PRCM Base Address */
#define PRCM_BASE                            (0x48180000u)

/*  \brief Base address of I2C memory mapped registers */
#define SOC_I2C1_BASE                        (0x48028000u)
#define SOC_I2C2_BASE                        (0x4802A000u)
#define SOC_I2C3_BASE                        (0x4819C000u)
#define SOC_I2C4_BASE                        (0x4819E000u)

/*  \brief Base address of UART memory mapped registers */
#define SOC_UART1_BASE                       (0x48020000u)
#define SOC_UART2_BASE                       (0x48022000u)
#define SOC_UART3_BASE                       (0x48024000u)
#define SOC_UART4_BASE                       (0x481A6000u)
#define SOC_UART5_BASE                       (0x481A8000u)
#define SOC_UART6_BASE                       (0x481AA000u)

/*  \brief Base address of MCSPI memory mapped registers */
#define SOC_MCSPI1_BASE                      (0x48030000u)
#define SOC_MCSPI2_BASE                      (0x481A0000u)
#define SOC_MCSPI3_BASE                      (0x481A2000u)
#define SOC_MCSPI4_BASE                      (0x481A4000u)

/*
 *   \brief Base address of MCSPI memory mapped registers
 *   Defined again to keep the interface same
 */
#define SOC_MCSPI0_REGS                      (0x48030000u)
#define SOC_MCSPI1_REGS                      (0x481A0000u)
#define SOC_MCSPI2_REGS                      (0x481A2000u)
#define SOC_MCSPI3_REGS                      (0x481A4000u)

/*  \brief Base address of Mailbox memory mapped registers */
#define SOC_SYSTEM_MAILBOX                   (0x480C8000u)

/*  \brief Base addresses of GPIO memory mapped registers */
#define SOC_GPIO1_BASE                       (0x48032000u)
#define SOC_GPIO2_BASE                       (0x4804C000u)
#define SOC_GPIO3_BASE                       (0x481AC000u)
#define SOC_GPIO4_BASE                       (0x481AE000u)

/*  \brief Base addresses of EDMA memory mapped registers  */
#define SOC_EDMA_TPCC_BASE                   (0x49000000u)

/*  \brief Base addresses of DSP MMU memory mapped registers */
#define SOC_DSP1_MMU0CFG_BASE                (0x48010000u)

/* \brief DSP L2 RAM base*/
#define SOC_DSP_L2_RAM_BASE                  (0x40800000u)

/* \brief DSP L1P RAM base*/
#define SOC_DSP_L1P_CACHE_RAM_BASE           (0x40E00000u)

/* \brief DSP L1D RAM base*/
#define SOC_DSP_L1D_CACHE_RAM_BASE           (0x40F00000u)

/*  \brief Base address of Channel controller  memory mapped registers */
#define SOC_EDMA30CC_0_REGS                  (0x49000000u)

#define SOC_MCASP0_CFG_BASE                  (0x48038000u)
#define SOC_MCASP0_BASE                      (0x46000000u)
#define SOC_MCASP1_CFG_BASE                  (0x4803C000u)
#define SOC_MCASP1_BASE                      (0x46400000u)
#define SOC_MCASP2_CFG_BASE                  (0x48050000u)
#define SOC_MCASP2_BASE                      (0x46800000u)
#define SOC_MCASP3_CFG_BASE                  (0x4A1A2000u)
#define SOC_MCASP3_BASE                      (0x4A1A5000u)
#define SOC_MCASP4_CFG_BASE                  (0x4A1A8000u)
#define SOC_MCASP4_BASE                      (0x4A1AB000u)
#define SOC_MCASP5_CFG_BASE                  (0x4A1AE000u)
#define SOC_MCASP5_BASE                      (0x4A1B1000u)

/*  \brief Base address of Timer memory mapped registers */
#define SOC_TIMER1_BASE                     (0x4802E000u)
#define SOC_TIMER2_BASE                     (0x48040000u)
#define SOC_TIMER3_BASE                     (0x48042000u)
#define SOC_TIMER4_BASE                     (0x48044000u)
#define SOC_TIMER5_BASE                     (0x48046000u)
#define SOC_TIMER6_BASE                     (0x48048000u)
#define SOC_TIMER7_BASE                     (0x4804A000u)
#define SOC_TIMER8_BASE                     (0x481C1000u)

/*  \brief Base address of MMCSD memory mapped registers */
#define SOC_MMC1_BASE                       (0x48060000u)
#define SOC_MMC2_BASE                       (0x481D8000u)
#define SOC_MMC3_BASE                       (0x47810000u)

/*
 *  \brief Base address of MMCSD memory mapped registers.
 *  Defined again to keep the interface same
 */
#define SOC_MMCHS_0_REGS                    (0x48060000u)
#define SOC_MMCHS_1_REGS                    (0x481D8000u)
#define SOC_MMCHS_2_REGS                    (0x47810000u)

/*  \brief Base address of PCIe memory mapped registers  */
#define SOC_PCIE_APP_BASE                   (0x51000000u)
#define SOC_PCIE_LOCAL_CONF_BASE            (0x51001000u)
#define SOC_PCIE_REMOTE_CONF_BASE           (0x51002000u)
#define SOC_PCIE_REMOTE_IO_BASE             (0x51003000u)

/*  \brief PCIe memory space base address */
#define SOC_PCIE_BASE                       (0x20000000u)

/*  \brief EDMA TPTC registers */
#define SOC_EDMA_TC0_BASE                   (0x49800000u)
#define SOC_EDMA_TC1_BASE                   (0x49900000u)
#define SOC_EDMA_TC2_BASE                   (0x49A00000u)
#define SOC_EDMA_TC3_BASE                   (0x49B00000u)

/* \brief GPMC region */
#define SOC_GPMC_BASE                       (0x0u)

/* \brief GPMC memory mapped registers */
#define SOC_GPMC_CONF_BASE                  (0x50000000u)

/* \brief OCMC RAM Base address */
#define SOC_OCMC_RAM_BASE                   (0x40300000u)

/* \brief McBSP region */
#define SOC_MCBSP_BASE                      (0x47000000u)

/* \brief HDMI region */
#define SOC_HDMI_BASE                       (0x46C00000u)

/* \brief USB Base address */
#define SOC_USB_BASE                        (0x47400000u)

/* \brief Media controller base address */
#define SOC_MEDIA_CONTROL_BASE              (0x55000000u)

/* \brief SGX530 base address*/
#define SOC_SGX530_SOC                      (0x56000000u)

/* \brief HDVICP2 Configuration base address*/
#define SOC_HDVICP2_CONF_BASE               (0x58000000u)

/* \brief HDVICP2 SL2 base address*/
#define SOC_HDVICP2_SL2_BASE                (0x59000000u)

/* \brief ISS base address*/
#define SOC_ISS_BASE                        (0x5C000000u)

/* \brief EMAC memory mapped register base */
#define SOC_EMAC_SW_BASE                    (0x4A100000u)

/* \brief SATA memory mapped register base */
#define SOC_DWC_AHSATA_BASE                 (0x4A140000u)

/* \brief DEMMU memory mapped register base */
#define SOC_DEMMU_BASE                      (0x48010000u)

/* \brief ELM memory mapped register base */
#define SOC_ELM_BASE                        (0x48080000u)

/* \brief RTC memory mapped register base*/
#define SOC_RTC_SS_BASE                     (0x480C0000u)

/* \brief SPINLOCK memory mapped register base*/
#define SOC_SPINLOCK_BASE                   (0x480CA000u)

/* \brief HDVPSS memory mapped register base*/
#define SOC_HDVPSS_BASE                     (0x48100000u)

/* \brief HDMI memory mapped register base*/
#define SOC_HDMI_CONF_BASE                  (0x48122000u)

/* \brief Smart reflex memory mapped register base*/
#define SOC_SMARTREFLEX1_BASE               (0x48188000u)
#define SOC_SMARTREFLEX2_BASE               (0x4818A000u)
#define SOC_SMARTREFLEX3_BASE               (0x48190000u)
#define SOC_SMARTREFLEX4_BASE               (0x48192000u)

/* \brief OCP Watchpoint memory mapped register base */
#define SOC_OCP_WATCHPOINT_BASE             (0x4818C000u)

/* \brief Sync timer memory mapped register base */
#define SOC_SYNCTIMER32K_BASE               (0x481C3000u)

/* \brief PLLSS memory mapped register base */
#define SOC_PLLSS_BASE                      (0x481C5000u)

/* \brief Watch dog timer memory mapped register base */
#define SOC_WATCHDOGTIMER_BASE              (0x481C7000u)

/* \brief DCAN memory mapped register base */
#define SOC_DCAN1_BASE                      (0x481CC000u)
#define SOC_DCAN2_BASE                      (0x481D0000u)

#ifdef __cplusplus
}
#endif
#endif /* _SOC_H_ */

