/*
 *  ======== config.bld ========
 *  Build configuration script for HDVPSS drivers
 */

/* load the required modules for the configuration */

var M3 = xdc.useModule('ti.targets.arm.elf.M3');
var C674 = xdc.useModule('ti.targets.elf.C674');

var buildReleaseConfig = true;

/* configure  the options for the M3 targets     */

/* M3 compiler directory path                    */
M3.rootDir = java.lang.System.getenv("CGTOOLS");

/* linker options */

M3.lnkOpts.suffix += " --zero_init=off ";
M3.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options                                */
M3.ccOpts.suffix += " --gcc -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0 -DUTILS_ASSERT_ENABLE";

/* set default platform and list of all interested
 * platforms for M3
 */
M3.platforms = [
                        "ti.platforms.evmTI816X:core0",
                        "ti.platforms.evmTI816X:core1",
               ];

/* Select the default platform
 *
 * Making core1 as defualt core configuration to be used
 *  Core 0 ==    Ducati.M3.VIDEO
 *  Core 1 ==    Ducati.M3.VPS
 */
M3.platform = M3.platforms[1];

/* configure  the options for the C674 targets     */

/* C674 compiler directory path                    */
C674.rootDir = java.lang.System.getenv("CGTOOLS_DSP");

/* linker options */

C674.lnkOpts.suffix += " --zero_init=off ";
C674.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options                                */
C674.ccOpts.suffix += " -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0";

C674.platforms = ["ti.platforms.evmTI816X:plat"];
C674.platform = C674.platforms[0];

/* list interested targets in Build.targets array  */
Build.targets = [
                    M3,
                    C674,
                ];

var KB=1024;
var MB=KB*KB;
var GB=KB*KB*KB;

var DDR3_ADDR                  = 0x80000000;
var DDR3_SIZE                  = 2048*MB;

var ETH_OFFLOAD_ADDR           = 0x40300000;
var ETH_OFFLOAD_SIZE           = 64*KB;

var OCMC0_ADDR                 = ETH_OFFLOAD_ADDR + ETH_OFFLOAD_SIZE;
var OCMC1_ADDR                 = 0x40400000;
var OCMC0_RUN_ADDR             = OCMC0_ADDR - 0x40000000;
var OCMC1_RUN_ADDR             = OCMC1_ADDR - 0x40000000;

var OCMC0_SIZE                 = 256*KB - ETH_OFFLOAD_SIZE;
var OCMC1_SIZE                 = 256*KB;

var L2_SRAM_ADDR               = 0x55024000;
var L2_SRAM_SIZE               = 128*KB;
var L2_SRAM_RUN_ADDR           = 0x20004000;

var DUCATI_WB_WA_ADDR          = 0x20000000;

var TOTAL_MEM_SIZE             = 2048*MB;


/* FIRST + SECOND 512MB */
var SR1_SIZE                   = 278 * MB;
var VIDEO_M3_CODE_SIZE         = 3   * MB;
var VIDEO_M3_BSS_SIZE          = 15  * MB;
var VIDEO_M3_DATA_SIZE         = 3   * MB;
var DSS_M3_CODE_SIZE           = 2   * MB;
var DSS_M3_BSS_SIZE            = 20  * MB;
var DSS_M3_DATA_SIZE           = 6   * MB;
var DSP_CODE_SIZE              = 1   * MB;
var DSP_DATA_SIZE              = 24  * MB;
var SR2_FRAME_BUFFER_SIZE      = 600  * MB;
var CMEM_SIZE                   =40*MB;
var VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;
var VPSS_M3_EXCEPTION_CTX_SIZE  = 128*KB;
var SR0_SIZE                    = 22 * MB + 768 * KB;
var HDVPSS_DESC_SIZE            = 2  * MB;
var HDVPSS_SHARED_SIZE          = 2  * MB;
var NOTIFY_SHARED_SIZE          = 2  * MB;
var REMOTE_DEBUG_SIZE           = 1  * MB;
var SHARED_MEMORY_SIZE          = 2  * MB;

/* THIRD 512MB */
var TILER_SIZE                  = 256 * MB;
var SR3_FRAME_BUFFER_EXTRA_SIZE     = 256 * MB;

/* LAST 512MB */
var LINUX_SIZE                  = 512 * MB;


/* first and second 512MB */
var SR1_ADDR                   = DDR3_ADDR;
var VIDEO_M3_CODE_ADDR         = SR1_ADDR                        + SR1_SIZE;
var VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR				 + VIDEO_M3_CODE_SIZE;
var VIDEO_M3_BSS_ADDR          = VIDEO_M3_DATA_ADDR				 + VIDEO_M3_DATA_SIZE;
var VIDEO_M3_BSS_MAPPED_ADDR   = (VIDEO_M3_BSS_ADDR - DDR3_ADDR) + DUCATI_WB_WA_ADDR;
var DSS_M3_CODE_ADDR           = VIDEO_M3_BSS_ADDR				 + VIDEO_M3_BSS_SIZE;
var DSS_M3_DATA_ADDR           = DSS_M3_CODE_ADDR				 + DSS_M3_CODE_SIZE;
var DSS_M3_BSS_ADDR            = DSS_M3_DATA_ADDR				 + DSS_M3_DATA_SIZE;
var DSS_M3_BSS_MAPPED_ADDR     = (DSS_M3_BSS_ADDR - DDR3_ADDR)	 + DUCATI_WB_WA_ADDR;
var DSP_CODE_ADDR              = DSS_M3_BSS_ADDR				 + DSS_M3_BSS_SIZE;
var DSP_DATA_ADDR              = DSP_CODE_ADDR					 + DSP_CODE_SIZE;
var SR2_FRAME_BUFFER_ADDR      = DSP_DATA_ADDR                    + DSP_DATA_SIZE;
var CMEM_ADDR                   = SR2_FRAME_BUFFER_ADDR                    + SR2_FRAME_BUFFER_SIZE;
var VIDEO_M3_EXCEPTION_CTX_ADDR = CMEM_ADDR         + CMEM_SIZE;
var VPSS_M3_EXCEPTION_CTX_ADDR  = VIDEO_M3_EXCEPTION_CTX_ADDR   + VIDEO_M3_EXCEPTION_CTX_SIZE;
var SR0_ADDR                    = VPSS_M3_EXCEPTION_CTX_ADDR    + VPSS_M3_EXCEPTION_CTX_SIZE;
var HDVPSS_DESC_ADDR            = SR0_ADDR                      + SR0_SIZE;
var HDVPSS_SHARED_ADDR          = HDVPSS_DESC_ADDR              + HDVPSS_DESC_SIZE;
var NOTIFY_SHARED_ADDR          = HDVPSS_SHARED_ADDR            + HDVPSS_SHARED_SIZE;
var REMOTE_DEBUG_ADDR           = NOTIFY_SHARED_ADDR            + NOTIFY_SHARED_SIZE;
var SHARED_MEMORY_ADDR          = REMOTE_DEBUG_ADDR             + REMOTE_DEBUG_SIZE;

//var LINUX_ADDR                  = DDR3_ADDR                     + 1 * GB;

var LINUX_ADDR                    =DDR3_ADDR                     + 1 * GB;
var SR3_FRAME_BUFFER_EXTRA_ADDR = LINUX_ADDR                    + LINUX_SIZE;
var TILER_ADDR                  = SR3_FRAME_BUFFER_EXTRA_ADDR   + SR3_FRAME_BUFFER_EXTRA_SIZE;

if ((SHARED_MEMORY_ADDR + SHARED_MEMORY_SIZE) > TILER_ADDR)
{
  throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                           "\nRegion End: " + "0x" + java.lang.Long.toHexString(TILER_ADDR) + 
                           "\nActual End: " + "0x" + java.lang.Long.toHexString(SHARED_MEMORY_ADDR + SHARED_MEMORY_SIZE ));
}

if ((SR3_FRAME_BUFFER_EXTRA_ADDR + SR3_FRAME_BUFFER_EXTRA_SIZE) > DDR3_ADDR + DDR3_SIZE)
{
  throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                           "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_ADDR + DDR3_SIZE) + 
                           "\nActual End: " + "0x" + java.lang.Long.toHexString(SR3_FRAME_BUFFER_EXTRA_ADDR + SR3_FRAME_BUFFER_EXTRA_SIZE)
						  );
}

Build.platformTable["ti.platforms.evmTI816X:core1"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC1_SIZE
        }],
        ["VIDEO_M3_BSS_MAPPED_MEM", {
            comment : "VIDEO_M3_BSS_MAPPED_MEM",
            name    : "VIDEO_M3_BSS_MAPPED_MEM",
            base    : VIDEO_M3_BSS_MAPPED_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_BSS_MAPPED_MEM", {
            comment : "DSS_M3_BSS_MAPPED_MEM",
            name    : "DSS_M3_BSS_MAPPED_MEM",
            base    : DSS_M3_BSS_MAPPED_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_FRAME_BUFFER_EXTRA", {
            comment : "SR3_FRAME_BUFFER_EXTRA",
            name    : "SR3_FRAME_BUFFER_EXTRA",
            base    : SR3_FRAME_BUFFER_EXTRA_ADDR,
            len     : SR3_FRAME_BUFFER_EXTRA_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["VIDEO_M3_BSS_MEM", {
            comment : "VIDEO_M3_BSS_MEM",
            name    : "VIDEO_M3_BSS_MEM",
            base    : VIDEO_M3_BSS_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["VIDEO_M3_BSS_MAPPED_MEM", {
            comment : "VIDEO_M3_BSS_MAPPED_MEM",
            name    : "VIDEO_M3_BSS_MAPPED_MEM",
            base    : VIDEO_M3_BSS_MAPPED_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSS_M3_BSS_MEM", {
            comment : "DSS_M3_BSS_MEM",
            name    : "DSS_M3_BSS_MEM",
            base    : DSS_M3_BSS_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["DSS_M3_BSS_MAPPED_MEM", {
            comment : "DSS_M3_BSS_MAPPED_MEM",
            name    : "DSS_M3_BSS_MAPPED_MEM",
            base    : DSS_M3_BSS_MAPPED_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DSP_DATA_MEM",
            name    : "DSP_DATA_MEM",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len:  0x00004000
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC1_SIZE
        }],
        ["OCMC1_RAM_MAPPED", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM_MAPPED",
            base: OCMC1_RUN_ADDR,
            len:  OCMC1_SIZE
        }],
    ]
};

Build.platformTable["ti.platforms.evmTI816X:core0"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC0_SIZE
        }],
        ["VIDEO_M3_BSS_MAPPED_MEM", {
            comment : "VIDEO_M3_BSS_MAPPED_MEM",
            name    : "VIDEO_M3_BSS_MAPPED_MEM",
            base    : VIDEO_M3_BSS_MAPPED_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_BSS_MAPPED_MEM", {
            comment : "DSS_M3_BSS_MAPPED_MEM",
            name    : "DSS_M3_BSS_MAPPED_MEM",
            base    : DSS_M3_BSS_MAPPED_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["L2_SRAM", {
            comment: "L2_SRAM",
            name: "L2_SRAM",
            base: L2_SRAM_ADDR,
            len:  L2_SRAM_SIZE
        }],
        ["L2_SRAM_RUN", {
            comment: "L2_SRAM_RUN",
            name: "L2_SRAM_RUN",
            base: L2_SRAM_RUN_ADDR,
            len:  L2_SRAM_SIZE
        }],
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_FRAME_BUFFER_EXTRA", {
            comment : "SR3_FRAME_BUFFER_EXTRA",
            name    : "SR3_FRAME_BUFFER_EXTRA",
            base    : SR3_FRAME_BUFFER_EXTRA_ADDR,
            len     : SR3_FRAME_BUFFER_EXTRA_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["DDR_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["VIDEO_M3_BSS_MEM", {
            comment : "VIDEO_M3_BSS_MEM",
            name    : "VIDEO_M3_BSS_MEM",
            base    : VIDEO_M3_BSS_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["VIDEO_M3_BSS_MAPPED_MEM", {
            comment : "VIDEO_M3_BSS_MAPPED_MEM",
            name    : "VIDEO_M3_BSS_MAPPED_MEM",
            base    : VIDEO_M3_BSS_MAPPED_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DSS_M3_BSS_MEM", {
            comment : "DSS_M3_BSS_MEM",
            name    : "DSS_M3_BSS_MEM",
            base    : DSS_M3_BSS_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["DSS_M3_BSS_MAPPED_MEM", {
            comment : "DSS_M3_BSS_MAPPED_MEM",
            name    : "DSS_M3_BSS_MAPPED_MEM",
            base    : DSS_M3_BSS_MAPPED_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["DSS_M3_DATA_MEM", {
            comment : "DSS_M3_DATA_MEM",
            name    : "DSS_M3_DATA_MEM",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DSP_DATA_MEM",
            name    : "DSP_DATA_MEM",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["L2_SRAM", {
            comment: "L2_SRAM",
            name: "L2_SRAM",
            base: L2_SRAM_ADDR,
            len:  L2_SRAM_SIZE
        }],
        ["L2_SRAM_RUN", {
            comment: "L2_SRAM_RUN",
            name: "L2_SRAM_RUN",
            base: L2_SRAM_RUN_ADDR,
            len:  L2_SRAM_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len:  0x00004000
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC0_SIZE
        }],
        ["OCMC0_RAM_MAPPED", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM_MAPPED",
            base: OCMC0_RUN_ADDR,
            len:  OCMC0_SIZE
        }],
    ]
};

Build.platformTable["ti.platforms.evmTI816X:plat"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC0_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC1_SIZE
        }],
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_FRAME_BUFFER_EXTRA", {
            comment : "SR3_FRAME_BUFFER_EXTRA",
            name    : "SR3_FRAME_BUFFER_EXTRA",
            base    : SR3_FRAME_BUFFER_EXTRA_ADDR,
            len     : SR3_FRAME_BUFFER_EXTRA_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["VIDEO_M3_BSS_MEM", {
            comment : "VIDEO_M3_BSS_MEM",
            name    : "VIDEO_M3_BSS_MEM",
            base    : VIDEO_M3_BSS_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DSS_M3_DATA_MEM", {
            comment : "DSS_M3_DATA_MEM",
            name    : "DSS_M3_DATA_MEM",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSS_M3_BSS_MEM", {
            comment : "DSS_M3_BSS_MEM",
            name    : "DSS_M3_BSS_MEM",
            base    : DSS_M3_BSS_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC0_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC1_SIZE
        }],
        ["DSP_L2_RAM", {
            comment: "DSP_L2_RAM",
            name: "DSP_L2_RAM",
            base: 0x10800000,
            len:  0x00020000
        }],            
        ["ETH_OFFLOAD", {
            comment: "ETH_OFFLOAD",
            name: "ETH_OFFLOAD",
            base: ETH_OFFLOAD_ADDR,
            len:  ETH_OFFLOAD_SIZE
        }],

    ],
    l1PMode: "32k",
    l1DMode: "32k",
    l2Mode:  "128k"
};

var addrFileGenerated = false;
if (addrFileGenerated == false)
{
    var GenAddr = xdc.loadCapsule("genaddrinfo.xs");
    GenAddr.GenAddrFile();
    print ("Memory Map - 2GB DDR");
    GenAddr.printBox(SR1_SIZE,"(SR1) Bitstream buffer {Cached on A8. Cached on M3, although access by DMAs}");
    
    GenAddr.printBox(VIDEO_M3_CODE_SIZE,"Video M3 Code");
    GenAddr.printBox(VIDEO_M3_BSS_SIZE,"Video M3 BSS");
    GenAddr.printBox(VIDEO_M3_DATA_SIZE,"Video M3 Data");
    GenAddr.printBox(DSS_M3_CODE_SIZE,"VPSS M3 Code");
    GenAddr.printBox(DSS_M3_BSS_SIZE,"VPSS M3 BSS");
    GenAddr.printBox(DSS_M3_DATA_SIZE,"VPSS M3 Data");
    GenAddr.printBox(DSP_CODE_SIZE,"DSP Code");
    GenAddr.printBox(DSP_DATA_SIZE,"DSP Data");
    GenAddr.printBox(SR2_FRAME_BUFFER_SIZE,"(SR2) Frame Buffer Region {VPSS - Video M3 Frame Buf}");
    GenAddr.printBox(CMEM_SIZE,"CMEM");
    GenAddr.printBox(VIDEO_M3_EXCEPTION_CTX_SIZE,"Video M3 exception context");
    GenAddr.printBox(VPSS_M3_EXCEPTION_CTX_SIZE,"VPSS M3 exception context");
    GenAddr.printBox(SR0_SIZE,"(SR0) Syslink MsgQ/IPC List MP - <Non-cached on M3>");
    GenAddr.printBox(HDVPSS_DESC_SIZE,"VPSS M3 - VPDMA Descriptor");
    GenAddr.printBox(HDVPSS_SHARED_SIZE,"VPSS M3 - FBDev Shared Memory");
    GenAddr.printBox(NOTIFY_SHARED_SIZE,"Host - VPSS M3 Notify(For FBDev)");
    GenAddr.printBox(REMOTE_DEBUG_SIZE,"Remote Debug Print");
    GenAddr.printBox(SHARED_MEMORY_SIZE,"Shared Memory application inter process communication on A8");
    GenAddr.printBox(LINUX_SIZE,"Linux");
    GenAddr.printBox(SR3_FRAME_BUFFER_EXTRA_SIZE,"SR3_FRAME_BUFFER_EXTRA - Extra heap for video frame buffers.Not mapped on M3");
    GenAddr.printBoxFinal(TILER_SIZE,"Tiled 8-bit + 16-bit region");

    addrFileGenerated = true;
}