-heap 0x4000
-stack 0x4000

MEMORY
{
  VECTORS_MEM: origin = 0x00800000 length = 0x00000400
  /*Local addresses*/
  BOOT_MEM: origin = 0x00800400 length = 0x00001C00
  TEXT_MEM: origin = 0x00802000 length = 0x0007e000
  DATA_MEM: origin = 0x00880000 length = 0x00040000
  
  DATA_ALIAS_L2_MEM: origin = 0x40000000 lenght = 00100000h
 
  /* SL2 RAM */
  MSMCSRAM0: origin = 0x00C000000 length = 00100000h /* 1MB */
  MSMCSRAM1: origin = 0x00C100000 length = 00100000h /* 1MB */

  /* SL2 alias Address*/
  MSMCSRAMALIAS_CACHABLE:    origin = 0x30000000 length = 00100000h /* 1MB */
  MSMCSRAMALIAS_NONCACHABLE: origin = 0x31000000 length = 00100000h /* 1MB */

  /* DDR alias Address*/
  DDR2:    origin = 0x80000000 length = 10000000h /* 1MB */
}

SECTIONS
{
  .csl_vect: 			> 			VECTORS_MEM

  /* Boot Memory Sections */
  .boot: 					> 			BOOT_MEM

  /* Text Memory Sections */
  .text: 					> 			TEXT_MEM

  /* Data Memory Sections */
  .data: 					> 			DATA_MEM

  .fasttext:  		>       TEXT_MEM
  .cinit:     		>       TEXT_MEM
  .stack:     		>       TEXT_MEM
  .bss:       		>       TEXT_MEM
  .const:     		>       TEXT_MEM
  .far:       		>       TEXT_MEM
  .switch:    		>       TEXT_MEM
  .sysmem:    		>       TEXT_MEM
  .cio:       		>       TEXT_MEM
  .heap:       		>       TEXT_MEM
  .fardata:    		>       TEXT_MEM
  .neardata:   		>       TEXT_MEM
  .rodata:     		>       TEXT_MEM
  
   /* real address */
  .mydata:          >       MSMCSRAM0
  .mydata1          >       MSMCSRAM1
  
   /* alias address */
  .mycachable:      >		MSMCSRAMALIAS_CACHABLE
  .mynoncachable:   >       MSMCSRAMALIAS_NONCACHABLE
  .myconst:                 load= MSMCSRAM1, run = MSMCSRAMALIAS_NONCACHABLE
  
  .ddrdata:         >       DDR2
  
}
