
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2011
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
* ============================================================================
Example to show the initialization of Multicore Navigator on Keystone DSP
* =============================================================================
 *  Revision History
 *  ===============
 *  May 5, 2011 Brighton Feng   File Created
 * ============================================================================
 */
#ifndef _MULTICORE_NAVIGATOR_INIT_H_
#define _MULTICORE_NAVIGATOR_INIT_H_

#include "KeyStone_Navigator_init_drv.h"

#define ACC_48_CHANNEL

/*size of descriptor must be multiple of 16B*/
#define HOST_DESCRIPTOR_SIZE 		32
#define L2_MONO_DESCRIPTOR_SIZE 	(8192+16)
#define DDR_MONO_DESCRIPTOR_SIZE 	(8192+16)

/*the linking RAM entry size for each descriptor region 
must be power of 2, and no less than 32.
Actual descriptor number may less than linking entry size, this may 
leave hole in linking RAM*/
#define SL2_HOST_DESCRIPTOR_NUM 		(2*1024)
#define SL2_HOST_DESC_LINK_ENTRY_NUM 	(2*1024)
#define SL2_MONO_DESCRIPTOR_NUM 		(8)
#define SL2_MONO_DESC_LINK_ENTRY_NUM 	(32) 	/*only 8 of 32 is used for the 8 descriptors*/
#define LL2_HOST_DESCRIPTOR_NUM 		(1024)
#define LL2_HOST_DESC_LINK_ENTRY_NUM 	(1024)
#define LL2_MONO_DESCRIPTOR_NUM 		(8)
#define LL2_MONO_DESC_LINK_ENTRY_NUM 	(32) 	/*only 8 of 32 is used for the 8 descriptors*/
#define DDR_HOST_DESCRIPTOR_NUM 		(8*1024)
#define DDR_HOST_DESC_LINK_ENTRY_NUM 	(8*1024)
#define DDR_MONO_DESCRIPTOR_NUM 		(8*1024)
#define DDR_MONO_DESC_LINK_ENTRY_NUM 	(8*1024)

#define TOTAL_LINKING_ENTRY_SIZE 		(SL2_HOST_DESC_LINK_ENTRY_NUM+\
										SL2_MONO_DESC_LINK_ENTRY_NUM+\
										LL2_HOST_DESC_LINK_ENTRY_NUM*4+\
										LL2_MONO_DESC_LINK_ENTRY_NUM*4+\
										DDR_HOST_DESC_LINK_ENTRY_NUM+\
										DDR_MONO_DESC_LINK_ENTRY_NUM)

/*there is only 16K entries in QMSS internal linking RAM. So, part of 
DDR mono descriptors will use external linking RAM in this test*/
#if (TOTAL_LINKING_ENTRY_SIZE>16*1024)
#define LINKING_RAM1_SIZE 				(TOTAL_LINKING_ENTRY_SIZE-16*1024)
#define DDR_MONO_LINKING_RAM1_DESC_NUM 	LINKING_RAM1_SIZE
#define DDR_MONO_LINKING_RAM0_DESC_NUM 	(DDR_MONO_DESCRIPTOR_NUM-DDR_MONO_LINKING_RAM1_DESC_NUM)
#endif

#define SL2_PACKET_BUFFER_SIZE0 	(256)
#define SL2_PACKET_BUFFER_SIZE1 	(1024)
#define SL2_PACKET_BUFFER_SIZE2 	(4*1024)
#define SL2_PACKET_BUFFER_SIZE3 	(8*1024)
#define SL2_SIZE0_PKT_BUF_NUM 		(256)
#define SL2_SIZE1_PKT_BUF_NUM 		(64)
#define SL2_SIZE2_PKT_BUF_NUM 		(16)
#define SL2_SIZE3_PKT_BUF_NUM 		(8)
#define SL2_SIZE1_DESC_START_IDX 	(SL2_SIZE0_PKT_BUF_NUM)
#define SL2_SIZE2_DESC_START_IDX 	(SL2_SIZE1_DESC_START_IDX+SL2_SIZE1_PKT_BUF_NUM)
#define SL2_SIZE3_DESC_START_IDX 	(SL2_SIZE2_DESC_START_IDX+SL2_SIZE2_PKT_BUF_NUM)
#define SL2_NO_BUF_DESC_START_IDX 	(SL2_SIZE3_DESC_START_IDX+SL2_SIZE3_PKT_BUF_NUM)
#define SL2_NO_BUF_DESCRIPTOR_NUM 	(SL2_HOST_DESCRIPTOR_NUM-SL2_NO_BUF_DESC_START_IDX)

#define LL2_PACKET_BUFFER_SIZE0 	(256)
#define LL2_PACKET_BUFFER_SIZE1 	(1024)
#define LL2_PACKET_BUFFER_SIZE2 	(4*1024)
#define LL2_PACKET_BUFFER_SIZE3 	(8*1024)
#define LL2_SIZE0_PKT_BUF_NUM 		(32)
#define LL2_SIZE1_PKT_BUF_NUM 		(16)
#define LL2_SIZE2_PKT_BUF_NUM 		(8)
#define LL2_SIZE3_PKT_BUF_NUM 		(8)
#define LL2_SIZE1_DESC_START_IDX 	(LL2_SIZE0_PKT_BUF_NUM)
#define LL2_SIZE2_DESC_START_IDX 	(LL2_SIZE1_DESC_START_IDX+LL2_SIZE1_PKT_BUF_NUM)
#define LL2_SIZE3_DESC_START_IDX 	(LL2_SIZE2_DESC_START_IDX+LL2_SIZE2_PKT_BUF_NUM)
#define LL2_NO_BUF_DESC_START_IDX 	(LL2_SIZE3_DESC_START_IDX+LL2_SIZE3_PKT_BUF_NUM)
#define LL2_NO_BUF_DESCRIPTOR_NUM 	(LL2_HOST_DESCRIPTOR_NUM-LL2_NO_BUF_DESC_START_IDX)

#define DDR_PACKET_BUFFER_SIZE0 	(256)
#define DDR_PACKET_BUFFER_SIZE1 	(2*1024)
#define DDR_PACKET_BUFFER_SIZE2 	(16*1024)
#define DDR_PACKET_BUFFER_SIZE3 	(128*1024)
#define DDR_SIZE0_PKT_BUF_NUM 		(512)
#define DDR_SIZE1_PKT_BUF_NUM 		(128)
#define DDR_SIZE2_PKT_BUF_NUM 		(32)
#define DDR_SIZE3_PKT_BUF_NUM 		(8)
#define DDR_SIZE1_DESC_START_IDX 	(DDR_SIZE0_PKT_BUF_NUM)
#define DDR_SIZE2_DESC_START_IDX 	(DDR_SIZE1_DESC_START_IDX+DDR_SIZE1_PKT_BUF_NUM)
#define DDR_SIZE3_DESC_START_IDX 	(DDR_SIZE2_DESC_START_IDX+DDR_SIZE2_PKT_BUF_NUM)
#define DDR_NO_BUF_DESC_START_IDX 	(DDR_SIZE3_DESC_START_IDX+DDR_SIZE3_PKT_BUF_NUM)
#define DDR_NO_BUF_DESCRIPTOR_NUM 	(DDR_HOST_DESCRIPTOR_NUM-DDR_NO_BUF_DESC_START_IDX)

#define TEST_QUEUE_BASE 			2000

#define SL2_MONOLITHIC_FDQ 			(TEST_QUEUE_BASE+0 )
#define SL2_HOST_SIZE0_FDQ 			(TEST_QUEUE_BASE+1 )
#define SL2_HOST_SIZE1_FDQ 			(TEST_QUEUE_BASE+2 )
#define SL2_HOST_SIZE2_FDQ 			(TEST_QUEUE_BASE+3 )
#define SL2_HOST_SIZE3_FDQ 			(TEST_QUEUE_BASE+4 )
#define SL2_NO_BUF_HOST_FDQ 		(TEST_QUEUE_BASE+5 )

#define DDR_MONOLITHIC_FDQ 			(TEST_QUEUE_BASE+6 )
#define DDR_MONO_LINK_RAM0_FDQ 		(DDR_MONOLITHIC_FDQ)
#define DDR_HOST_SIZE0_FDQ 			(TEST_QUEUE_BASE+7 )
#define DDR_HOST_SIZE1_FDQ 			(TEST_QUEUE_BASE+8 )
#define DDR_HOST_SIZE2_FDQ 			(TEST_QUEUE_BASE+9 )
#define DDR_HOST_SIZE3_FDQ 			(TEST_QUEUE_BASE+10)
#define DDR_NO_BUF_HOST_FDQ 		(TEST_QUEUE_BASE+11)

#define CORE0_LL2_MONOLITHIC_FDQ 	(TEST_QUEUE_BASE+12)
#define CORE0_LL2_HOST_SIZE0_FDQ 	(TEST_QUEUE_BASE+13)
#define CORE0_LL2_HOST_SIZE1_FDQ 	(TEST_QUEUE_BASE+14)
#define CORE0_LL2_HOST_SIZE2_FDQ 	(TEST_QUEUE_BASE+15)
#define CORE0_LL2_HOST_SIZE3_FDQ 	(TEST_QUEUE_BASE+16)
#define CORE0_LL2_NO_BUF_HOST_FDQ 	(TEST_QUEUE_BASE+17)

#define CORE1_LL2_MONOLITHIC_FDQ 	(TEST_QUEUE_BASE+18)
#define CORE1_LL2_HOST_SIZE0_FDQ 	(TEST_QUEUE_BASE+19)
#define CORE1_LL2_HOST_SIZE1_FDQ 	(TEST_QUEUE_BASE+20)
#define CORE1_LL2_HOST_SIZE2_FDQ 	(TEST_QUEUE_BASE+21)
#define CORE1_LL2_HOST_SIZE3_FDQ 	(TEST_QUEUE_BASE+22)
#define CORE1_LL2_NO_BUF_HOST_FDQ 	(TEST_QUEUE_BASE+23)

#define CORE2_LL2_MONOLITHIC_FDQ 	(TEST_QUEUE_BASE+24)
#define CORE2_LL2_HOST_SIZE0_FDQ 	(TEST_QUEUE_BASE+25)
#define CORE2_LL2_HOST_SIZE1_FDQ 	(TEST_QUEUE_BASE+26)
#define CORE2_LL2_HOST_SIZE2_FDQ 	(TEST_QUEUE_BASE+27)
#define CORE2_LL2_HOST_SIZE3_FDQ 	(TEST_QUEUE_BASE+28)
#define CORE2_LL2_NO_BUF_HOST_FDQ 	(TEST_QUEUE_BASE+29)

#define CORE3_LL2_MONOLITHIC_FDQ 	(TEST_QUEUE_BASE+30)
#define CORE3_LL2_HOST_SIZE0_FDQ 	(TEST_QUEUE_BASE+31)
#define CORE3_LL2_HOST_SIZE1_FDQ 	(TEST_QUEUE_BASE+32)
#define CORE3_LL2_HOST_SIZE2_FDQ 	(TEST_QUEUE_BASE+33)
#define CORE3_LL2_HOST_SIZE3_FDQ 	(TEST_QUEUE_BASE+34)
#define CORE3_LL2_NO_BUF_HOST_FDQ 	(TEST_QUEUE_BASE+35)

#define PKT_DMA_TEST_DST_Q 			(TEST_QUEUE_BASE+36)
#define EMPTY_FDQ 					(TEST_QUEUE_BASE+37)
#define EMPTY_DST_Q 				(TEST_QUEUE_BASE+38)

#define RECLAMATION_QUEUE 			(TEST_QUEUE_BASE+39)

#define DDR_MONO_LINK_RAM1_FDQ 		(TEST_QUEUE_BASE+40)

#define RX_FLOW_LL2_HOST 			0
#define RX_FLOW_SL2_HOST 			1
#define RX_FLOW_DDR_HOST 			2
#define RX_FLOW_LL2_MONO 			3
#define RX_FLOW_SL2_MONO 			4
#define RX_FLOW_DDR_MONO 			5

extern Uint32 uiUsedDescRegionNum;
extern Uint32 uiInitialHostFdqNum;
extern Uint32 uiInitialMonoFdqNum;
extern Uint32 uiUsedRxFlowNum;

extern void QMSS_init();
extern void PktDMA_init();
extern void checkQueues();

#endif
