/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2011
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
Interrupts configuration for QMSS
 * =============================================================================
 *  Revision History
 *  ===============
 *  8-May-2011 Brighton  file created
 * =============================================================================
 */

#include <stdio.h>
#include <c6x.h> 
#include <csl_cpintc.h>
#include "KeyStone_common.h"

int uiQ662_pend_event_num;

void CP_INTC_Init_QM(void)
{
	TDSP_Type dspType;

	/* Disable Global host interrupts. */
	cpIntc0Regs->GLOBAL_ENABLE_HINT_REG= 0;

	/* Configure no nesting support in the CPINTC Module. */
	cpIntc0Regs->CONTROL_REG= ((cpIntc0Regs->CONTROL_REG&
		~CSL_CPINTC_CONTROL_REG_NEST_MODE_MASK)|
		(CPINTC_NO_NESTING<<CSL_CPINTC_CONTROL_REG_NEST_MODE_SHIFT));

	dspType= Get_dsp_type();
	if(TCI6616==dspType||TCI6618==dspType||TCI6614==dspType)
	{	
		/*map Queue 662 pend interrupts events (134) to INTC0 out64*/
		uiQ662_pend_event_num= 134;
		
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(134)]= 64;

		/*clear Queue 662 pend interrupts events (134)*/
		cpIntc0Regs->STATUS_CLR_INDEX_REG= 134; 

		/*enable Queue 662 pend interrupts events (134)*/
		cpIntc0Regs->ENABLE_SET_INDEX_REG= 134;

		/*enable INTC out64*/
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 64;
	}
	else if(TCI6608==dspType)
	{	
		/*map Queue 662 pend interrupts events (156) to INTC0 out33*/
		uiQ662_pend_event_num= 156;

		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(156)]= 33;

		/*clear Queue 662 pend interrupts events (156)*/
		cpIntc0Regs->STATUS_CLR_INDEX_REG= 156; 

		/*enable Queue 662 pend interrupts events (156)*/
		cpIntc0Regs->ENABLE_SET_INDEX_REG= 156;

		/*enable INTC out44*/
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 33;
	}
	else
	{
		puts("Unknown DSP type!");
		return;
	}	

	/* Enable Global host interrupts. */
	cpIntc0Regs->GLOBAL_ENABLE_HINT_REG= 1;

}

void QM_Interrupts_Init(void)
{
	CP_INTC_Init_QM();
	
	//map high priority queue channel 0 interrupt to INT4
	//map low priority queues channel 0 interrupt to INT5
	/*on Nyquist, INTC0 out64 event number are 22 on core 0		
	on Shannon, INTC0 out33 event number are 22 on core0		
	map this event 22 to INT6 */
	CGEM_regs->INTMUX1 = (CSL_GEM_QM_INT_HIGH_N<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)|
		(CSL_GEM_QM_INT_LOW_0<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)|
		(22<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT);

	 /*Clear all DSP core events*/
	CGEM_regs->EVTCLR[0]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[1]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[2]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[3]= 	0xFFFFFFFF;

	//clear DSP core interrupt flag
	ICR= IFR;

	//enable INT4, 5, 6
	IER = 3|(1<<4)|(1<<5)|(1<<6);

	/*Interrupt Service Table Pointer to begining of LL2 memory*/
	ISTP= 0x800000;

	//enable GIE
	TSR = TSR|1;
}


