TPCC1的配置： 全局参数： /* EDMA3 INSTANCE# 1 */ /** Total number of DMA Channels supported by the EDMA3 Controller */ 64u, /** Total number of QDMA Channels supported by the EDMA3 Controller */ 8u, /** Total number of TCCs supported by the EDMA3 Controller */ 64u, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ 512u, /** Total number of Event Queues in the EDMA3 Controller */ 4u, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ 4u, /** Number of Regions on this EDMA3 controller */ 8u, /** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 1u, /** Existence of memory protection feature */ 1u, /** Global Register Region of CC Registers */ (void *)0x02720000u, /** Transfer Controller (TC) Registers */ { (void *)0x02770000u, (void *)0x02778000u, (void *)0x02780000u, (void *)0x02788000u, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ 8u, /** Interrupt no. for CC Error */ 0u, /** Interrupt no. for TCs Error */ { 2u, 3u, 4u, 5u, 0u, 0u, 0u, 0u, }, /** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0u, 1u, 2u, 3u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16u, 16u, 16u, 16u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 8u, 8u, 8u, 8u, 0u, 0u, 0u, 0u }, /** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u }, /** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP }, /** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { 0x3FFF3FFFu, 0x3FFF3FFFu } }, TPCC1的资源配置：我们使用的方法是：核0使用region3,核1使用region4 /* Resources owned/reserved by region 0 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x0000FF3Fu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x0000FF3Fu, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000003u}, /* ownTccs */ /* 31 0 63 32 */ {0x0000FF3Fu, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00003F3Fu, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00003F3Fu, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00003F3Fu, 0x00000000u}, }, /* Resources owned/reserved by region 1 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFF0000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x0000000Cu}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFF0000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x3FFF0000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x3FFF0000u, 0x00000000u}, }, /* Resources owned/reserved by region 2 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x0000FFFFu}, /* ownQdmaChannels */ /* 31 0 */ {0x00000030u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x0000FFFFu}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00003FFFu}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00003FFFu}, }, /* Resources owned/reserved by region 3 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000040u, 0xFFFF0000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000040u, 0xFFFF0000u}, /* ownQdmaChannels */ /* 31 0 */ {0x000000C0u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000040u, 0xFFFF0000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000040u, 0x3FFF0000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000040u, 0x3FFF0000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x3FFF0000u}, }, /* Resources owned/reserved by region 4 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000080u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000080u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000080u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000080u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000080u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 5 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 6 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, /* Resources owned/reserved by region 7 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000u}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, }, 通道配置： EDMA3_DRV_Result Drv_Edma3q2q_Init(EDMA3_DRV_Handle hEdma,UINT8 ucCoreID) { EDMA3_DRV_Result tResult = EDMA3_DRV_SOK; /*分配通道和TCC*/ gudTcc = EDMA3_DRV_TCC_ANY; gudChId = (DRV_EDMA_CHANNEL_EVENT_6 + ucCoreID);//Core0:chanel 6,Core1:chanel 7 /* Request DMA channel and any TCC */ if (tResult == EDMA3_DRV_SOK) { #if 1 /*又中断回调*/ tResult = EDMA3_DRV_requestChannel (hEdma, &gudChId, &gudTcc, (EDMA3_RM_EventQueue)2, (EDMA3_RM_TccCallback)&Edmaq2q_RecCallBack, NULL); #else /*无中断回调*/ tResult = EDMA3_DRV_requestChannel (hEdma, &gudChId, &gudTcc, (EDMA3_RM_EventQueue)0, NULL, NULL); #endif } #if 1 /*置IPR/IPRH位*/ edma3IntrParamsLoc[gudTcc].tccCb = (EDMA3_RM_TccCallback)&Edmaq2q_RecCallBack; edma3IntrParamsLoc[gudTcc].cbData = NULL; if (gudTcc < 32u) allocatedTCCsLoc[0u] |= (0x1u << gudTcc); else allocatedTCCsLoc[1u] |= (0x1u << (gudTcc - 32u)); #endif return tResult; }