#ifndef MEM_SHARING_H
#define MEM_SHARING_H

#include <tistdtypes.h>

#define EDMA_TC_NUM 		10

/*Bandwith information for CPU and EDMA*/
typedef struct _EdmaBandwidthInfo
{
	volatile Uint32 	enabled;
	volatile Uint32 	priority; 	/*0~7, >7 means the master should be disabled for this test*/
	volatile Uint32 	srcAddr;
	volatile Uint32 	dstAddr;
	volatile Uint32 	ACnt;
	volatile Uint32 	BCnt;
	volatile Uint32 	EDMA_number; 	/*0, 1, 2, EDMA moudle number*/
	/*TC and channel number, for this test channel 0 use TC 0, channel 1 use TC 1, and so on*/
	volatile Uint32 	TC_channel; 	
	volatile Uint32 	averageBandwidth;
	volatile Uint32 	testTimes;
	volatile Uint32 	running;
	volatile Uint32 	reStat; 	/*re-statistic after re-configuration*/
	volatile unsigned long long 	start_TSC; 	/*time stamp when test start*/
	volatile unsigned long long 	last_TSC; 	/*time stamp when last test completion*/
}EdmaTestInfo;

typedef struct _CoreBandwidthInfo
{
	volatile Uint32 	enabled;
	volatile Uint32 	priority; 	/*0~7, >7 means the master should be disabled for this test*/
	volatile Uint32 	srcAddr;
	volatile Uint32 	dstAddr;
	volatile Uint32 	size;
	volatile Uint32 	repeatCount; 	
	volatile Uint32 	L1dCacheSize;
	volatile Uint32 	L2CacheSize;
	volatile Uint32 	averageBandwidth;
	volatile Uint32 	testTimes;
	volatile Uint32 	reStat; 	/*re-statistic after re-configuration*/
	volatile unsigned long long 	start_TSC; 	/*time stamp when test start*/
	volatile unsigned long long 	last_TSC; 	/*time stamp when last test completion*/
}CoreTestInfo;

typedef struct _TestConfig
{
	Bool bEDMA_Test; 	 	/*0:DSP core test; 1:EDMA test*/
	Bool bDDR_Test; 	 	/*0:SL2 test; 1:DDR test*/
	Bool bAccessDifBank; 	/*0:Access same bank; 1:Access different bank*/
	unsigned int uiDDR_PRI_RAISE_CNT; /*DDR priority raise count*/
}TestConfig;

extern EdmaTestInfo 	edmaTestInfo[];
extern CoreTestInfo 	coreTestInfo[];
extern TestConfig testCases[];
extern volatile Uint32 	readyFlag;
extern Uint32 masterNumber;


#endif
