/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2010
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
* ============================================================================
Example to show the performance of DSP core access memory on KeyStone DSP
* =============================================================================
 *  Revision History
 *  ===============
 *  7-Dec-2010 Brighton Feng   File Created
 * ============================================================================
 */

#include <stdio.h>
#include <string.h>
#include <c6x.h>
#include "KeyStone_common.h"
#include "KeyStone_DDR_Init.h"

/*memory protection and address extension configuration table*/
#pragma DATA_SECTION(MPAX_cfg_table,".far:Core_MPAX")
MPAX_Config MPAX_cfg_table[]=
{
    /*BADDR         RADDR           SegementSize      AccessPermisionMask
    32-bit virtual  36-bit physical in byte, must     Access types allowed
    base address    address right   be power of 2     in this address range
                    shift by 4                                            */
    {0,             0,              2*1024*1024*1024,   MP_SR|MP_SW|MP_UR|MP_UW},/*change memory attribute of the default memory segement 0, 1 to read/write, not for execution, to catch runaway code*/
    {0x80000000,    0x80000000,     2*1024*1024*1024,   MP_SR|MP_SW|MP_UR|MP_UW},
    {0x21000000,    0x10000000,     4*1024,             MP_SR|MP_SW|MP_UR|MP_UW},/*map DDR2 configuration registers at physical address 0x1:00000000 to logical address 0x21000000*/
    {0x18000000,    0x00C00000,     16*1024*1024,       MP_SR|MP_SW|MP_UR|MP_UW}/*remap Shared L2 to 0x18000000 for read/write*/
};

extern void	MemCopyTest();
extern void	LoadStoreCycleTest();
extern void	edma_test();
extern void IDMA1_test();

void main()
{   
	TDSP_Board_Type DSP_Board_Type;
	DDR_ECC_Config DDR_ECC_cfg;

	/* Initialize Time stamp counter to measure cycles*/
	TSC_init();

	memset((void *)&DDR_ECC_cfg, 0, sizeof(DDR_ECC_cfg));

	DSP_Board_Type= KeyStone_Get_dsp_board_type();
	if(C6678_EVM==DSP_Board_Type)
	{
		//DSP core speed: 100*10/1=1000MHz
		KeyStone_main_PLL_init(100, 10, 1); 
	}
	else if(TCI6614_EVM==DSP_Board_Type
		||DUAL_NYQUIST_EVM==DSP_Board_Type
		||C6670_EVM==DSP_Board_Type)
	{
		//DSP core speed: 122.88*236/29= 999.9889655MHz
		KeyStone_main_PLL_init(122.88, 236, 29);

		/*DDR ECC is supported on TCI6614 EVM*/
		if(TCI6614_EVM == DSP_Board_Type)
		{
			DDR_ECC_cfg.addressRange[0].startAddr= 0x00000000;
			DDR_ECC_cfg.addressRange[0].byteCnt=   0x40000000;
			DDR_ECC_cfg.rangeMode= EN_ECC_WITHIN_DEFINED_RANGES;
		}
	}
	else
	{
		puts("Unknown DSP board type!");
		return;
	}

	//DDR init 66.667*20/1= 1333
	KeyStone_DDR_init (66.667, 20, 1, &DDR_ECC_cfg);

	/*enable L1P ED and scrub whole L1P*/
	L1P_EDC_setup();

   	/*enable LL2 EDC and scrub whole LL2*/
	LL2_EDC_setup();

	/*Enable MSMC EDC and setup scrubbing cycle counter= 255*1024*/
	KeyStone_SL2_EDC_enable(255);

	/*XMC memory address extension/mapping and memory protection*/
	KeyStone_XMC_MPAX_setup(MPAX_cfg_table, 0,
		sizeof(MPAX_cfg_table)/sizeof(MPAX_Config));
	
	MemCopyTest();

	//LoadStoreCycleTest();

	edma_test();

	IDMA1_test();

	puts("Test complete");
    
    return;
}
