/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2010
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
* ============================================================================
Example to show the performance of DSP core access memory
* =============================================================================
 *  Revision History
 *  ===============
 *  7-Dec-2010 Brighton Feng   File Created
 *  Updated on March 30 2011 for C6678 EVM
 * ============================================================================
 */

#include <csl_cacheAux.h>
#include <stdio.h>
#include <c6x.h>
#include "KeyStone_common.h"
#include "KeyStone_DDR_Init.h"

#define 	LOAD_STORE_TIMES 	(512)

#define 	L2_TEST_BASE_ADDR 	(0x820000)
#define 	L2_END_ADDR 		(0x880000)
#define 	MAX_L2_CACHE 		(256*1024)
#define 	L2_COPY_SIZE 		((L2_END_ADDR-MAX_L2_CACHE-L2_TEST_BASE_ADDR)/2)
#define 	L2_LOAD_STORE_SIZE 	(L2_END_ADDR-L2_TEST_BASE_ADDR)

#define 	L1D_TEST_BASE_ADDR 	(0xf00000)
#define 	L1D_COPY_SIZE 		(8*1024)

#define 	CORE1_L2_TEST_BASE_ADDR	(0x11800000)

#define 	ORIGIN_SL2_TEST_BASE_ADDR 	(0x0C080000)
#define 	REMAP_SL2_TEST_BASE_ADDR 	(0x18080000)
#define 	SL2_LOAD_STORE_SIZE 		(1024*1024)
#define 	SL2_COPY_SIZE 		L2_COPY_SIZE

#define 	DDR_TEST_ADDR 		(0x88000000)
#define 	DDR_LOAD_STORE_SIZE (128*1024*1024)
#define 	DDR2_PAGE_SIZE 		(1024*8)

#define 	LD_ST_TEST_OVER_HEAD 	40

extern void MemCopy8(long long * restrict dst, long long * restrict src, Uint32 uiCount);

void MemCopy8Test(long long * srcBuff, long long * dstBuff, Uint32 uiSize)
{
	unsigned int cycles;
	Uint32 iBandWidth;

	//Clear cache
	CACHE_wbInvAllL1d(CACHE_WAIT);
	CACHE_invAllL1p(CACHE_WAIT);
	printf("copy %d bytes from 0x%x to 0x%x ", uiSize, srcBuff, dstBuff);
	cycles= TSCL;
	MemCopy8(dstBuff, srcBuff, uiSize/8);
	cycles= TSC_count_cycle_from(cycles);
	iBandWidth= (unsigned long long)uiSize*DSP_Core_Clock_KHz/cycles/1000;
	printf("consumes %ld cycles, %d MB/s\n", cycles, iBandWidth);
}

void MemCopyTest()
{
	//Configure L1P as 32KB cache, set L1D as 16KB for test
	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_16KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L1D->L1D");
	MemCopy8Test((long long *)L1D_TEST_BASE_ADDR,(long long *)(L1D_TEST_BASE_ADDR+L1D_COPY_SIZE), L1D_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: LL2->L1D");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)(L1D_TEST_BASE_ADDR), L1D_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L1D->LL2");
	MemCopy8Test((long long *)L1D_TEST_BASE_ADDR,(long long *)(L2_TEST_BASE_ADDR), L1D_COPY_SIZE);


	//Configure L1 as 32KB cache
	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_32KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->L2");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)(L2_TEST_BASE_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	//make OTHER_CorePac_L2 nonprefetchable, noncacheable
	CGEM_regs->MAR[CORE1_L2_TEST_BASE_ADDR/16/1024/1024]=0;

	puts("\n\nDSP core 8 bytes aligned Memory Copy test: L2->Other CorePac L2, nonprefetchable, noncacheable");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)CORE1_L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->L2, nonprefetchable, noncacheable");
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->Other CorePac L2, nonprefetchable, noncacheable");
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)(CORE1_L2_TEST_BASE_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	//make OTHER_CorePac_L2 prefetchable, cacheable, use L1D only
	CGEM_regs->MAR[CORE1_L2_TEST_BASE_ADDR/16/1024/1024]=1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);	
	CACHE_setL2Size(CACHE_0KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->Other CorePac L2, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)CORE1_L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->L2, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->Other CorePac L2, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)(CORE1_L2_TEST_BASE_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	//use L1D and L2
	CACHE_setL2Size(CACHE_256KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->Other CorePac L2, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)CORE1_L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->L2, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: Other CorePac L2->Other CorePac L2, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)CORE1_L2_TEST_BASE_ADDR,(long long *)(CORE1_L2_TEST_BASE_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);


	//test SL2 through prefetchable cacheable memory window
	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->SL2, prefetchable, cacheable");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)ORIGIN_SL2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: SL2->L2, prefetchable, cacheable");
	MemCopy8Test((long long *)ORIGIN_SL2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: SL2->SL2, prefetchable, cacheable");
	MemCopy8Test((long long *)ORIGIN_SL2_TEST_BASE_ADDR,(long long *)(ORIGIN_SL2_TEST_BASE_ADDR+SL2_COPY_SIZE), SL2_COPY_SIZE);

	//make remapped SL2 noncacheable, nonprefetchable
	CGEM_regs->MAR[(REMAP_SL2_TEST_BASE_ADDR/16/1024/1024)]=0;	

	//test SL2 through non-prefetchable non-cacheable remapped memory window
	puts("\n\nDSP core 8 bytes aligned Memory Copy test: L2->remapped SL2, non-prefetchable, non-cacheable");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)REMAP_SL2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: remapped SL2->L2, non-prefetchable, non-cacheable");
	MemCopy8Test((long long *)REMAP_SL2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: remapped SL2->remapped SL2, non-prefetchable, non-cacheable");
	MemCopy8Test((long long *)REMAP_SL2_TEST_BASE_ADDR,(long long *)(REMAP_SL2_TEST_BASE_ADDR+SL2_COPY_SIZE), SL2_COPY_SIZE);

	//make remapped SL2 cacheable, prefetchable
	CGEM_regs->MAR[(REMAP_SL2_TEST_BASE_ADDR/16/1024/1024)]=1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);	
	//use L1D only
	CACHE_setL2Size(CACHE_0KCACHE);
	
	//test SL2 through remapped prefetchable cacheable memory window
	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->remapped SL2, prefetchable, cacheable");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)REMAP_SL2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: remapped SL2->L2, prefetchable, cacheable");
	MemCopy8Test((long long *)REMAP_SL2_TEST_BASE_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: remapped SL2->remapped SL2, prefetchable, cacheable");
	MemCopy8Test((long long *)REMAP_SL2_TEST_BASE_ADDR,(long long *)(REMAP_SL2_TEST_BASE_ADDR+SL2_COPY_SIZE), SL2_COPY_SIZE);


	//make external memory noncacheable, nonprefetchable
	CGEM_regs->MAR[(DDR_TEST_ADDR/16/1024/1024)]=0;	

	puts("\n\nDSP core 8 bytes aligned Memory Copy test: L2->DDR, noncacheable, nonprefetchable");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)DDR_TEST_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->L2, noncacheable, nonprefetchable");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR same bank, noncacheable, nonprefetchable");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR different bank, noncacheable, nonprefetchable");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE+DDR2_PAGE_SIZE), L2_COPY_SIZE);

	//make external memory prefetchable cacheable, use L1D cache only
	CGEM_regs->MAR[(DDR_TEST_ADDR/16/1024/1024)]=1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);	
	CACHE_setL2Size(CACHE_0KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->DDR, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)DDR_TEST_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->L2, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR same bank, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR different bank, prefetchable, 32KB L1D cache only");
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE+DDR2_PAGE_SIZE), L2_COPY_SIZE);

	//use both L1D and L2 cache
	CACHE_setL2Size(CACHE_256KCACHE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: L2->DDR, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)L2_TEST_BASE_ADDR,(long long *)DDR_TEST_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->L2, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)L2_TEST_BASE_ADDR, L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR same bank, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE), L2_COPY_SIZE);

	puts("\nDSP core 8 bytes aligned Memory Copy test: DDR->DDR different bank, prefetchable, 32KB L1D and 256KB L2 cache");
	//Clear cache
	CACHE_wbInvAllL2(CACHE_WAIT);
	MemCopy8Test((long long *)DDR_TEST_ADDR,(long long *)(DDR_TEST_ADDR+L2_COPY_SIZE+DDR2_PAGE_SIZE), L2_COPY_SIZE);
}

void LDDWTest(Uint8 * srcBuff, Uint32 uiSize)
{
	unsigned int cycles;
	Uint32 		uiIndex;

	printf("Memory access performance test at 0x%x\n", srcBuff);
	uiIndex=0;
	while(uiIndex*8*LOAD_STORE_TIMES<uiSize)
	{
		CACHE_wbInvAllL1d(CACHE_WAIT);
		CACHE_wbInvAllL2(CACHE_WAIT);

		cycles= TSCL;
		Asm_LDDW_Test(srcBuff, uiIndex, LOAD_STORE_TIMES);
		cycles= TSC_count_cycle_from(cycles)-LD_ST_TEST_OVER_HEAD;
		printf("Index=%4d  Cycles/LDDW= %.2f\n", uiIndex, (float)cycles/(LOAD_STORE_TIMES));
		if(uiIndex<8)
			uiIndex++;
		else if(uiIndex<32)
			uiIndex+=2;
		else if(uiIndex<64)
			uiIndex+=8;
		else if(uiIndex<128)
			uiIndex+=32;
		else if(uiIndex<256)
			uiIndex+=64;
		else if(uiIndex<512)
			uiIndex+=128;
		else if(uiIndex<1024)
			uiIndex+=256;
		else if(uiIndex<2048)
			uiIndex+=512;
		else if(uiIndex<4096)
			uiIndex+=1024;
		else if(uiIndex<8192)
			uiIndex+=2048;
		else 
			uiIndex+=4096;
	}
}

void STDWTest(Uint8 * srcBuff, Uint32 uiSize)
{
	unsigned int cycles;
	Uint32 		uiIndex;

	printf("Memory access performance test at 0x%x\n", srcBuff);
	uiIndex=0;
	while(uiIndex*8*LOAD_STORE_TIMES<uiSize)
	{
		CACHE_wbInvAllL1d(CACHE_WAIT);
		CACHE_wbInvAllL2(CACHE_WAIT);

		cycles= TSCL;
		Asm_STDW_Test(srcBuff, uiIndex, LOAD_STORE_TIMES);
		cycles= TSC_count_cycle_from(cycles)-LD_ST_TEST_OVER_HEAD;
		printf("Index=%4d  Cycles/STDW= %.2f\n", uiIndex, (float)cycles/(LOAD_STORE_TIMES));
		if(uiIndex<8)
			uiIndex++;
		else if(uiIndex<32)
			uiIndex+=2;
		else if(uiIndex<64)
			uiIndex+=8;
		else if(uiIndex<128)
			uiIndex+=32;
		else if(uiIndex<256)
			uiIndex+=64;
		else if(uiIndex<512)
			uiIndex+=128;
		else if(uiIndex<1024)
			uiIndex+=256;
		else if(uiIndex<2048)
			uiIndex+=512;
		else if(uiIndex<4096)
			uiIndex+=1024;
		else if(uiIndex<8192)
			uiIndex+=2048;
		else 
			uiIndex+=4096;
	}
}

void LoadStoreCycleTest()
{
	Int32 i;
	
	//Configure L1 as 32KB cache
	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_0KCACHE);

	//L2 memory test
	CACHE_setL2Size(CACHE_0KCACHE);
	puts("\nLL2 LDDW test: 0KB L1D cahce");
	LDDWTest((Uint8 *)(L2_TEST_BASE_ADDR), L2_LOAD_STORE_SIZE);
	puts("\nLL2 STDW test: 0KB L1D cahce");
	STDWTest((Uint8 *)(L2_TEST_BASE_ADDR), L2_LOAD_STORE_SIZE);

	//Configure L1 as 32KB cache
	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_32KCACHE);

	//L2 memory test
	CACHE_setL2Size(CACHE_0KCACHE);
	puts("\nLL2 LDDW test: 32KB L1D cahce");
	LDDWTest((Uint8 *)(L2_TEST_BASE_ADDR), L2_LOAD_STORE_SIZE);
	puts("\nLL2 STDW test: 32KB L1D cahce");
	STDWTest((Uint8 *)(L2_TEST_BASE_ADDR), L2_LOAD_STORE_SIZE);

	//make original SL2 noncacheable, nonprefetchable
	CACHE_setL1DSize(CACHE_L1_0KCACHE);
	CGEM_regs->MAR[(ORIGIN_SL2_TEST_BASE_ADDR/16/1024/1024)]= 1|
		(0<<CSL_CGEM_MAR0_PFX_SHIFT);		

	//test SL2 nonprefetchable noncacheable
	puts("\nSL2 LDDW test: nonprefetchable, noncacheable");
	LDDWTest((Uint8 *)(ORIGIN_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	puts("\nSL2 STDW test: nonprefetchable, noncacheable");
	STDWTest((Uint8 *)(ORIGIN_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);

	//make original SL2 cacheable, prefetchable
	CACHE_setL1DSize(CACHE_L1_32KCACHE);
	CGEM_regs->MAR[(ORIGIN_SL2_TEST_BASE_ADDR/16/1024/1024)]= 1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);		

	//test SL2 through prefetchable cacheable memory window
	puts("\nSL2 LDDW test: prefetchable, cacheable");
	LDDWTest((Uint8 *)(ORIGIN_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	puts("\nSL2 STDW test: prefetchable, cacheable");
	STDWTest((Uint8 *)(ORIGIN_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);

	//make remapped SL2 noncacheable, nonprefetchable
	CGEM_regs->MAR[(REMAP_SL2_TEST_BASE_ADDR/16/1024/1024)]=0;	

	//test SL2 through non-prefetchable, non-cacheable memory window
	puts("\nremapped SL2 LDDW test: non-prefetchable, non-cacheable");
	LDDWTest((Uint8 *)(REMAP_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	puts("\nremapped SL2 STDW test: non-prefetchable, non-cacheable");
	STDWTest((Uint8 *)(REMAP_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	
	//make remapped SL2 cacheable, prefetchable
	CGEM_regs->MAR[(REMAP_SL2_TEST_BASE_ADDR/16/1024/1024)]=1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);	
	//use L1D only
	CACHE_setL2Size(CACHE_0KCACHE);
	
	//test SL2 through prefetchable, cacheable memory window
	puts("\nremapped SL2 LDDW test: prefetchable, cacheable");
	LDDWTest((Uint8 *)(REMAP_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	puts("\nremapped SL2 STDW test: prefetchable, cacheable");
	STDWTest((Uint8 *)(REMAP_SL2_TEST_BASE_ADDR), SL2_LOAD_STORE_SIZE);
	

	//make external memory nonprefetchable, noncacheable
	for(i=0; i< (DDR_LOAD_STORE_SIZE/(16*1024*1024)); i++)
		CGEM_regs->MAR[(DDR_TEST_ADDR/16/1024/1024)+i]=0;	

	puts("\nDDR LDDW test: nonprefetchable, noncacheable");
	LDDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	puts("\nDDR STDW test: nonprefetchable, noncacheable");
	STDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	
	//make external memory prefetchable, cacheable
	for(i=0; i< (DDR_LOAD_STORE_SIZE/(16*1024*1024)); i++)
		CGEM_regs->MAR[(DDR_TEST_ADDR/16/1024/1024)+i]= 1|
		(1<<CSL_CGEM_MAR0_PFX_SHIFT);	 	
	CACHE_setL2Size(CACHE_0KCACHE);

	puts("\nDDR LDDW test: prefetchable, 32KB L1D cahce");
	LDDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	puts("\nDDR STDW test: prefetchable, 32KB L1D cahce");
	STDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	
	//set 256KB L2 cache
	CACHE_setL2Size(CACHE_256KCACHE);

	puts("\nDDR LDDW test: prefetchable, 32KB L1D, 256KB L2 cahce");
	LDDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	puts("\nDDR STDW test: prefetchable, 32KB L1D, 256KB L2 cahce");
	STDWTest((Uint8 *)(DDR_TEST_ADDR), DDR_LOAD_STORE_SIZE);
	
}

