/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2011
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** ============================================================================
 *   @n This is an example to benchmark the EDMA3 performance
 */
 
/* =============================================================================
 *  Revision History
 *  ===============
 *  09-Jan-2010 Brighton Feng   File Created
 *  Updated on March 30 2011 for C6678 EVM
 * ============================================================================
 */

#include <stdio.h>
#include <csl_cacheAux.h>
#include <csl_edma3.h>
#include <cslr_device.h>
#include "KeyStone_common.h"

#define 	TEST_CHANNEL 	(0)
#define 	DEFAULT_TEST_TC 	(3)
#define 	A_COUNT 	(1024)

#define 	C1_L1D_TEST_SRC (0x11f00000)
#define 	C1_L1D_TEST_DST (0x11f02000)
#define 	L1D_TEST_BCNT 	((C1_L1D_TEST_DST-C1_L1D_TEST_SRC)/A_COUNT)

#define 	C1_L1P_TEST_SRC (0x11e00000)
#define 	C1_L1P_TEST_DST (0x11e02000)
#define 	L1P_TEST_BCNT 	((C1_L1P_TEST_DST-C1_L1P_TEST_SRC)/A_COUNT)

#define 	C1_LL2_TEST_SRC (0x11820000)
#define 	C1_LL2_TEST_DST (0x11840000)
#define 	C2_LL2_TEST_DST (0x12840000)
#define 	LL2_TEST_SIZE 	(C1_LL2_TEST_DST-C1_LL2_TEST_SRC)
#define 	LL2_TEST_BCNT 	(LL2_TEST_SIZE/A_COUNT)

#define 	SL2_TEST_SRC 	(0x0C080000)
#define 	SL2_TEST_DST 	(0x0C140000)
//#define 	SL2_TEST_SIZE 	(SL2_TEST_DST-SL2_TEST_SRC)
#define 	SL2_TEST_SIZE 	LL2_TEST_SIZE
#define 	SL2_TEST_BCNT 	(SL2_TEST_SIZE/A_COUNT)

#define 	DDR_TEST_SRC 	(0x88000000)
#define 	DDR_TEST_DST 	(0x88100000)
#define 	DDR_PAGE_SIZE 	(1024*2*8)
//#define 	DDR_TEST_BCNT 	((DDR_TEST_DST-DDR_TEST_SRC)/A_COUNT)
#define 	DDR_TEST_BCNT 	LL2_TEST_BCNT

void edma_Throughput_Test (Uint32 src, Uint32 dst, Uint32 uiACount, 
	Uint32 uiBCount, Uint32 uiIndex, CSL_TpccRegs*  EDMACCRegs, Uint32 TC_channel)
{
	unsigned int cycles;
	Uint32 loopIndex;
	Uint32 *srcBuff=(Uint32 *)src;
	Uint32 *dstBuff=(Uint32 *)dst;

	/* Initialize data buffers */
	for (loopIndex = 0; loopIndex < uiACount*uiBCount/4; loopIndex++) {
		srcBuff[loopIndex] = dst+loopIndex*4;
		dstBuff[loopIndex] = 0xaaaaaaaa;
	}      

	//Clear cache    
	CACHE_wbInvAllL1d(CACHE_WAIT);
	CACHE_wbInvAllL2(CACHE_WAIT);

	//clear completion flag
	EDMACCRegs->TPCC_ICR=(1<<TC_channel); 

	EDMACCRegs->PARAMSET[TC_channel].OPT= 
		CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, 
			CSL_EDMA3_TCCH_DIS, 
			CSL_EDMA3_ITCINT_DIS, 
			CSL_EDMA3_TCINT_EN,
			TC_channel,
			CSL_EDMA3_TCC_NORMAL,
			CSL_EDMA3_FIFOWIDTH_NONE, 
			CSL_EDMA3_STATIC_DIS, 
			CSL_EDMA3_SYNC_AB, 
			CSL_EDMA3_ADDRMODE_INCR, 
			CSL_EDMA3_ADDRMODE_INCR);
	EDMACCRegs->PARAMSET[TC_channel].SRC= src;
	EDMACCRegs->PARAMSET[TC_channel].A_B_CNT= (uiBCount<<16)|uiACount;
	EDMACCRegs->PARAMSET[TC_channel].DST= dst;
	EDMACCRegs->PARAMSET[TC_channel].SRC_DST_BIDX= (uiIndex<<16)|uiIndex;
	EDMACCRegs->PARAMSET[TC_channel].LINK_BCNTRLD= (uiBCount<<16)|0xFFFF;
	EDMACCRegs->PARAMSET[TC_channel].SRC_DST_CIDX= 0;
	EDMACCRegs->PARAMSET[TC_channel].CCNT= 1;

	/*Manually trigger the EDMA*/
	EDMACCRegs->TPCC_ESR= 1<<(TC_channel);

	cycles = TSCL; 	/*record start time*/
	/* Wait for completion */
	while ((EDMACCRegs->TPCC_IPR&(1<<(TC_channel))) ==0);
	cycles= TSC_count_cycle_from(cycles);

	printf("transfer %4d * %5d Bytes with index=%5d from 0x%8x to 0x%8x, ", uiBCount, uiACount, uiIndex, src, dst);
	printf("consumes %6d cycles, achieve bandwidth %5lld MB/s\n", cycles, (unsigned long long)uiACount*uiBCount*DSP_Core_Clock_KHz/cycles/1000);

	//clear completion flag
	EDMACCRegs->TPCC_ICR=(1<<TC_channel); 

	CSL_XMC_invalidatePrefetchBuffer();
	/* Verify data transfered */
	if((dst&0xffffff)>=0xe00000&&(dst&0xffffff)<0xf00000)
		return; 	//L1P can't be verified by following codes
	if(uiIndex!=uiACount)
		return; 	//non-linear transfer, do not verify it
	for (loopIndex = 0; loopIndex < uiACount*uiBCount/4; loopIndex++) {
		if(dstBuff[loopIndex] != (dst+loopIndex*4))
		{
			printf("EDMA data transfer failed at 0x%x\n", dstBuff+loopIndex);
			break;
		}
	}
	return;  

}

void edma_3D_Test (Uint32 src, Uint32 dst, Uint32 uiACount, 
	Uint32 uiBCount, Uint32 uiCCount, Uint32 uiBIndex, Uint32 uiCIndex, 
	CSL_TpccRegs*  EDMACCRegs, Uint32 TC_channel)
{
	unsigned int cycles;
	Uint32 i, j, k;
	Uint32 *srcBuff=(Uint32 *)src+uiCIndex*(uiCCount-1);
	Uint32 *dstBuff=(Uint32 *)dst+uiCIndex*(uiCCount-1);

	/* Initialize data buffers */
	for (i = 0; i < uiCCount; i++) 
	{
		for (j = 0; j < uiBCount; j++) 
		{
			srcBuff=(Uint32 *)(src+uiCIndex*i+uiBIndex*j);
			dstBuff=(Uint32 *)(dst+uiCIndex*i+uiBIndex*j);
			for (k = 0; k < uiACount/4; k++) 
			{
				srcBuff[k] = (Uint32)(dstBuff+k);
				dstBuff[k] = 0xaaaaaaaa;
			}      
		}
	}

	//Clear cache    
	CACHE_wbInvAllL2(CACHE_WAIT);
	CACHE_wbInvAllL1d(CACHE_WAIT);

	//clear completion flag
	EDMACCRegs->TPCC_ICR=(1<<TC_channel); 

	EDMACCRegs->PARAMSET[TC_channel].OPT= 
		CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_EN, 	/*chaining*/ 
			CSL_EDMA3_TCCH_DIS, 
			CSL_EDMA3_ITCINT_DIS, 
			CSL_EDMA3_TCINT_EN,
			TC_channel, 	/*chaining to self to achieve SYNC_ABC*/
			CSL_EDMA3_TCC_NORMAL,
			CSL_EDMA3_FIFOWIDTH_NONE, 
			CSL_EDMA3_STATIC_DIS, 
			CSL_EDMA3_SYNC_AB, 
			CSL_EDMA3_ADDRMODE_INCR, 
			CSL_EDMA3_ADDRMODE_INCR);
	EDMACCRegs->PARAMSET[TC_channel].SRC= src;
	EDMACCRegs->PARAMSET[TC_channel].A_B_CNT= (uiBCount<<16)|uiACount;
	EDMACCRegs->PARAMSET[TC_channel].DST= dst;
	EDMACCRegs->PARAMSET[TC_channel].SRC_DST_BIDX= (uiBIndex<<16)|uiBIndex;
	EDMACCRegs->PARAMSET[TC_channel].LINK_BCNTRLD= (uiBCount<<16)|0xFFFF;
	EDMACCRegs->PARAMSET[TC_channel].SRC_DST_CIDX= (uiCIndex<<16)|uiCIndex;
	EDMACCRegs->PARAMSET[TC_channel].CCNT= uiCCount;

	/*Manually trigger the EDMA*/
	EDMACCRegs->TPCC_ESR= 1<<(TC_channel);

	cycles = TSCL; 	/*record start time*/
	/* Wait for completion */
	while ((EDMACCRegs->TPCC_IPR&(1<<(TC_channel))) ==0);
	cycles= TSC_count_cycle_from(cycles);

	printf("transfer %4d * %4d * %5d Bytes with CIDX=%5d BIDX=%5d from 0x%8x to 0x%8x, ", 
		uiCCount, uiBCount, uiACount, uiCIndex, uiBIndex, src, dst);
	printf("consumes %7d cycles, achieve bandwidth %5lld MB/s\n", cycles, (unsigned long long)uiACount*uiBCount*uiCCount*DSP_Core_Clock_KHz/cycles/1000);

	//clear completion flag
	EDMACCRegs->TPCC_ICR=(1<<TC_channel); 

	/* Verify data transfered */
	if((dst&0xffffff)>=0xe00000&&(dst&0xffffff)<0xf00000)
		return; 	//L1P can't be verified by following codes

	CSL_XMC_invalidatePrefetchBuffer();
	for (i = 0; i < uiCCount; i++) 
	{
		for (j = 0; j < uiBCount; j++) 
		{
			srcBuff=(Uint32 *)(src+uiCIndex*i+uiBIndex*j);
			dstBuff=(Uint32 *)(dst+uiCIndex*i+uiBIndex*j);
			for (k = 0; k < uiACount/4; k++) 
			{
				if(dstBuff[k] != (Uint32)(dstBuff+k))
				{
					printf("EDMA data transfer failed at 0x%x\n", dstBuff+k);
					return;
				}
			}
		}	
	}
	return;  

}

void DDR_page_miss_test(Uint32 uiEDMA, Uint32 uiTC, 
	Uint32 uiBCnt)
{
	int uiACnt;
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];

	printf("Test DDR page miss penalty with EDMA%d TC%d\n", uiEDMA, uiTC);

	puts("source and destination in different banks");
	for(uiACnt=8; uiACnt<=DDR_PAGE_SIZE; uiACnt*=2)
	{
		/*make each ACNT access to a new page*/
		edma_3D_Test(DDR_TEST_SRC, DDR_TEST_SRC+0x8000000+DDR_PAGE_SIZE, uiACnt, 
		//edma_3D_Test(0x11800000, 0x12800000, uiACnt, 
			uiBCnt, 1, DDR_PAGE_SIZE, 0,
			EDMACCRegs, uiTC);
	}

	puts("source and destination in same bank");
	for(uiACnt=8; uiACnt<=DDR_PAGE_SIZE; uiACnt*=2)
	{
		/*make each ACNT access to a new page*/
		edma_3D_Test(DDR_TEST_SRC, DDR_TEST_SRC+0x8000000, uiACnt, 
		//edma_3D_Test(0x11800000, 0x12800000, uiACnt, 
			uiBCnt, 1, DDR_PAGE_SIZE, 0,
			EDMACCRegs, uiTC);
	}
}

void edma_overhead_test(Uint32 uiEDMA, Uint32 uiTC)
{   
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];

	printf("Overhead test with EDMA%d TC%d\n", uiEDMA, uiTC);
	//L1D->L1D
	edma_Throughput_Test (C1_L1D_TEST_SRC, C1_L1D_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//L1D->LL2
	edma_Throughput_Test (C1_L1D_TEST_SRC, C2_LL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//L1D->SL2
	edma_Throughput_Test (C1_L1D_TEST_SRC, SL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//L1D->DDR
	edma_Throughput_Test (C1_L1D_TEST_SRC, DDR_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);

	//LL2->L1D
	edma_Throughput_Test (C1_LL2_TEST_SRC, C1_L1D_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//LL2->LL2
	edma_Throughput_Test (C1_LL2_TEST_SRC, C2_LL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//LL2->SL2
	edma_Throughput_Test (C1_LL2_TEST_SRC, SL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//LL2->DDR
	edma_Throughput_Test (C1_LL2_TEST_SRC, DDR_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);

	//SL2->L1D
	edma_Throughput_Test (SL2_TEST_SRC, C1_L1D_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//SL2->LL2
	edma_Throughput_Test (SL2_TEST_SRC, C2_LL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//SL2->SL2
	edma_Throughput_Test (SL2_TEST_SRC, SL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//SL2->DDR
	edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);

	//DDR->L1D
	edma_Throughput_Test (DDR_TEST_SRC, C1_L1D_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//DDR->LL2
	edma_Throughput_Test (DDR_TEST_SRC, C2_LL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//DDR->SL2
	edma_Throughput_Test (DDR_TEST_SRC, SL2_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
	//DDR->DDR
	edma_Throughput_Test (DDR_TEST_SRC, DDR_TEST_DST, 8, 1, 0, EDMACCRegs, uiTC);
}

void edma_performance_test(Uint32 uiEDMA, Uint32 uiTC)
{   
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];

	printf("Throughput test with EDMA%d TC%d\n", uiEDMA, uiTC);
	//C1L2->C1L2
	edma_Throughput_Test (C1_LL2_TEST_SRC, C1_LL2_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//C1L2->C2L2
	edma_Throughput_Test (C1_LL2_TEST_SRC, C2_LL2_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L2->SL2
	edma_Throughput_Test (C1_LL2_TEST_SRC, SL2_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//SL2->L2
	edma_Throughput_Test (SL2_TEST_SRC, C2_LL2_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//SL2->SL2
	edma_Throughput_Test (SL2_TEST_SRC, SL2_TEST_DST, A_COUNT, SL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L1D->L1D
	edma_Throughput_Test (C1_L1D_TEST_SRC, C1_L1D_TEST_DST, A_COUNT, L1D_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L2->L1D
	edma_Throughput_Test (C1_LL2_TEST_SRC, C1_L1D_TEST_DST, A_COUNT, L1D_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L1D->L2
	edma_Throughput_Test (C1_L1D_TEST_SRC, C1_LL2_TEST_DST, A_COUNT, L1D_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L2->L1P
	edma_Throughput_Test (C1_LL2_TEST_SRC, C1_L1P_TEST_DST, A_COUNT, L1P_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L1D->L1P
	edma_Throughput_Test (C1_L1D_TEST_SRC, C1_L1P_TEST_DST, A_COUNT, L1P_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L1D->DDR
	edma_Throughput_Test (C1_L1D_TEST_SRC, DDR_TEST_DST, A_COUNT, L1D_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//DDR->L1D
	edma_Throughput_Test (DDR_TEST_SRC, C1_L1D_TEST_SRC, A_COUNT, L1D_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//L2->DDR
	edma_Throughput_Test (C1_LL2_TEST_SRC, DDR_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//DDR->L2
	edma_Throughput_Test (DDR_TEST_SRC, C2_LL2_TEST_DST, A_COUNT, LL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//DDR->DDR
	edma_Throughput_Test (DDR_TEST_SRC, DDR_TEST_DST, A_COUNT, DDR_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//DDR->DDR, src/dst in different bank
	edma_Throughput_Test (DDR_TEST_SRC, DDR_TEST_DST+DDR_PAGE_SIZE, A_COUNT, DDR_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//SL2->DDR
	edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, A_COUNT, SL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
	//DDR->SL2
	edma_Throughput_Test (DDR_TEST_SRC, SL2_TEST_DST, A_COUNT, SL2_TEST_BCNT, A_COUNT, EDMACCRegs, uiTC);
   
    return;
}

void edma_ACNT_Test(Uint32 uiEDMA, Uint32 uiTC, Uint32 uiSrc, Uint32 uiDst)
{   
	Int32 aCnt;
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];
	
	printf("EDMA ACNT test with EDMA%d TC%d\n", uiEDMA, uiTC);
	aCnt= 1;
	while(aCnt<=(24*1024))
	{
		//SL2->DDR
		edma_Throughput_Test (uiSrc, uiDst, aCnt, 1, aCnt, EDMACCRegs, uiTC);
		if(aCnt<16)
			aCnt++;
		else if(aCnt<256)
			aCnt+=16;
		else if(aCnt< 512)
			aCnt+=32;
		else if(aCnt< 1024)
			aCnt+=64;
		else if(aCnt< 2048)
			aCnt+=128;
		else if(aCnt< 4096)
			aCnt+=256;
		else if(aCnt< 8096)
			aCnt+=512;
		else
			aCnt+=1024;
	}
	return;
}

void edma_ACNTxBCNT_Test(Uint32 uiEDMA, Uint32 uiTC)
{   
	Int32 bCnt,aCnt;
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];
	
	printf("EDMA ACNTxBCNT test with EDMA%d TC%d\n", uiEDMA, uiTC);
	for(bCnt=1; bCnt<= 4; bCnt++)
	{
		aCnt=1;
		while(aCnt<=(24*1024))
		{
			//SL2->DDR
			edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, aCnt, bCnt, aCnt, EDMACCRegs, uiTC);
			if(aCnt<16)
				aCnt++;
			else if(aCnt<256)
				aCnt+=16;
			else if(aCnt< 512)
				aCnt+=32;
			else if(aCnt< 1024)
				aCnt+=64;
			else if(aCnt< 2048)
				aCnt+=128;
			else if(aCnt< 4096)
				aCnt+=256;
			else if(aCnt< 8096)
				aCnt+=512;
			else
				aCnt+=1024;
		}
	}   
	return;
}
void edma_Index_Test(Uint32 uiEDMA, Uint32 uiTC)
{   
	Int32 index,aCnt, bCnt;
	CSL_TpccRegs*  EDMACCRegs= gEDMACCRegs[uiEDMA];
	
	printf("EDMA Index test with EDMA%d TC%d\n", uiEDMA, uiTC);
	aCnt=1;
	while(aCnt<=(8*1024))
	{
		bCnt=SL2_TEST_SIZE/aCnt;
		if(bCnt>1024)
			bCnt=1024;
		//L2->DDR
		edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, aCnt, bCnt, 0, EDMACCRegs, uiTC);
		if(aCnt<16)
			aCnt++;
		else if(aCnt<256)
			aCnt+=16;
		else if(aCnt< 512)
			aCnt+=64;
		else if(aCnt< 1024)
			aCnt+=256;
		else
			aCnt+=512;
	}
	aCnt=1;
	while(aCnt<=(8*1024))
	{
		bCnt=SL2_TEST_SIZE/aCnt;
		if(bCnt>1024)
			bCnt=1024;
		//L2->DDR
		edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, aCnt, bCnt, aCnt, EDMACCRegs, uiTC);
		if(aCnt<16)
			aCnt++;
		else if(aCnt<256)
			aCnt+=16;
		else if(aCnt< 512)
			aCnt+=64;
		else if(aCnt< 1024)
			aCnt+=256;
		else
			aCnt+=512;
	}
	for(index=1; index<= 128; index*=4)
	{
		aCnt=1;
		while(aCnt<=(8*1024))
		{
			bCnt=SL2_TEST_SIZE/(aCnt+index);
			if(bCnt>1024)
				bCnt=1024;
			//L2->DDR
			edma_Throughput_Test (SL2_TEST_SRC, DDR_TEST_DST, aCnt, bCnt, aCnt+index, EDMACCRegs, uiTC);
			if(aCnt<16)
				aCnt++;
			else if(aCnt<256)
				aCnt+=16;
			else if(aCnt< 512)
				aCnt+=64;
			else if(aCnt< 1024)
				aCnt+=256;
			else
				aCnt+=512;
		}
	}   
	return;
}


void edma_test(void)
{  
	int i;
	
	//Configure L1D as 16KB cache, 16K RAM for test
	CACHE_setL1PSize(CACHE_L1_16KCACHE);
	CACHE_setL1DSize(CACHE_L1_16KCACHE);
	CACHE_setL2Size(CACHE_64KCACHE);

	edma_Init();

#if 1
	for(i=0; i<CSL_EDMA3_TPCC0_NUM_TC; i++)
		edma_overhead_test(0, i);
	for(i=0; i<CSL_EDMA3_TPCC1_NUM_TC; i++)
		edma_overhead_test(1, i);
	for(i=0; i<CSL_EDMA3_TPCC2_NUM_TC; i++)
		edma_overhead_test(2, i);
#endif

	for(i=0; i<CSL_EDMA3_TPCC0_NUM_TC; i++)
		edma_performance_test(0, i);
	for(i=0; i<CSL_EDMA3_TPCC1_NUM_TC; i++)
		edma_performance_test(1, i);
	for(i=0; i<CSL_EDMA3_TPCC2_NUM_TC; i++)
		edma_performance_test(2, i);
	
#if 0
	edma_ACNT_Test(0, 0, C1_LL2_TEST_SRC, C2_LL2_TEST_DST);
	edma_ACNT_Test(0, 0, C1_LL2_TEST_SRC, SL2_TEST_DST);
	edma_ACNT_Test(0, 0, C1_LL2_TEST_SRC, DDR_TEST_DST);
	edma_ACNT_Test(0, 0, SL2_TEST_SRC, C2_LL2_TEST_DST);
	edma_ACNT_Test(0, 0, SL2_TEST_SRC, DDR_TEST_DST);
	edma_ACNT_Test(0, 0, DDR_TEST_SRC, C2_LL2_TEST_DST);
	edma_ACNT_Test(0, 0, DDR_TEST_SRC, SL2_TEST_DST);

	edma_ACNTxBCNT_Test(0, 0);
	//edma_ACNTxBCNT_Test(1, 0);
	//edma_ACNTxBCNT_Test(2, 0);

	edma_Index_Test(0, 0);
	//edma_Index_Test(1, 0);
	//edma_Index_Test(2, 0);
#endif
	
	//DDR_page_miss_test(1, 1, 128);

	puts("EDMA test complete");
    return;
}

