/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2011
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
Interrupts configuration for EDMA and Timer
 * =============================================================================
 *  Revision History
 *  ===============
 *  14-Jan-2011 Brighton  file created
 * =============================================================================
 */

#include <stdio.h>
#include <c6x.h> 
#include <csl_cpintc.h>
#include "KeyStone_common.h"

Uint32 uiEdma_host_event_num[3];
void CP_INTC_Init_EDMA(void)
{
	TDSP_Board_Type DSP_Board_Type;

	/* Disable Global host interrupts. */
	cpIntc0Regs->GLOBAL_ENABLE_HINT_REG= 0;

	DSP_Board_Type= KeyStone_Get_dsp_board_type();
	if(C6670_EVM==DSP_Board_Type
		||DUAL_NYQUIST_EVM==DSP_Board_Type
		||TCI6614_EVM==DSP_Board_Type)
	{
		uiEdma_host_event_num[0]= 74;
		uiEdma_host_event_num[1]= 84;
		uiEdma_host_event_num[2]= 94;

		/*map EDMA0, 1, 2 GINT interrupts events (36, 6, 22) to INTC0 out74, 84, 94*/
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(36)]= 74;
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(6)]= 84;
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(22)]= 94;

		/*enable INTC out74, 84, 94*/
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 74;
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 84;
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 94;
	}
	else if(C6678_EVM==DSP_Board_Type)
	{	
		uiEdma_host_event_num[0]= 44;
		uiEdma_host_event_num[1]= 55;
		uiEdma_host_event_num[2]= 66;

		/*map EDMA0, 1, 2 GINT interrupts events (36, 6, 22) to INTC0 out44, 55, 66*/
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(36)]= 44;
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(6)]= 55;
		cpIntc0Regs->CH_MAP[SWAP_ENDIAN(22)]= 66;

		/*enable INTC out44, 55, 66*/
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 44;
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 55;
		cpIntc0Regs->HINT_ENABLE_SET_INDEX_REG= 66;
	}
	else
	{
		puts("Unknown DSP board type!");
		return;
	}	
	/*clear EDMA0, 1, 2 GINT interrupts events (36, 6, 22)*/
	cpIntc0Regs->STATUS_CLR_INDEX_REG= 6; 
	cpIntc0Regs->STATUS_CLR_INDEX_REG= 22; 
	cpIntc0Regs->STATUS_CLR_INDEX_REG= 36; 

	/*enable EDMA0, 1, 2 GINT interrupts events (36, 6, 22)*/
	cpIntc0Regs->ENABLE_SET_INDEX_REG= 6;
	cpIntc0Regs->ENABLE_SET_INDEX_REG= 22;
	cpIntc0Regs->ENABLE_SET_INDEX_REG= 36;

	/* Enable Global host interrupts. */
	cpIntc0Regs->GLOBAL_ENABLE_HINT_REG= 1;

}
 
void EDMA_Timer_Interrupts_Init(void)
{
	/*on Nyquist, INTC0 out74, out84, out94 event number are 22 on core 1, 2, 3		
	on Shannon, INTC0 out44, out55, out66 event number are 22 on core 1, 2, 3		
	map this event 22 to INT8 */
	CGEM_regs->INTMUX2 = 22<<CSL_CGEM_INTMUX2_INTSEL8_SHIFT;

	//map timer interrupt to INT14
	CGEM_regs->INTMUX3 = CSL_GEM_TINTLN<<CSL_CGEM_INTMUX3_INTSEL14_SHIFT;

	 /*Clear all DSP core events*/
	CGEM_regs->EVTCLR[0]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[1]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[2]= 	0xFFFFFFFF;
	CGEM_regs->EVTCLR[3]= 	0xFFFFFFFF;

	//clear DSP core interrupt flag
	ICR= IFR;

	//enable INT8, 14
	IER = 3|(1<<8)|(1<<14);

	/*Interrupt Service Table Pointer to begining of LL2 memory*/
	ISTP= 0x800000;

	//enable GIE
	TSR = TSR|1;
}

