/******************************************************************************

  Copyright (C), 2001-2013, Texas Instrument.

 ******************************************************************************
  File Name     : Keystone_TCP3D.h
  Version       : Initial Draft
  Author        : Andy Yin
  Created       : 2013/8/29
  Last Modified :
  Description   : Keystone_TCP3D.c header file for TCP3D process

  Function List :
  History       :
  1.Date        : 2013/8/29
    Author      : Andy Yin
    Modification: Created file


******************************************************************************/

/*----------------------------------------------*
 * external variables                           *
 *----------------------------------------------*/

/*----------------------------------------------*
 * external routine prototypes                  *
 *----------------------------------------------*/

/*----------------------------------------------*
 * internal routine prototypes                  *
 *----------------------------------------------*/

/*----------------------------------------------*
 * project-wide global variables                *
 *----------------------------------------------*/

/*----------------------------------------------*
 * module-wide global variables                 *
 *----------------------------------------------*/

/*----------------------------------------------*
 * constants                                    *
 *----------------------------------------------*/

/*----------------------------------------------*
 * macros                                       *
 *----------------------------------------------*/

/*----------------------------------------------*
 * routines' implementations                    *
 *----------------------------------------------*/
#ifndef _KEYSTONE_TCP3D_H_
#define _KEYSTONE_TCP3D_H_

#include <c6x.h>
#include <tistdtypes.h>
#include <stdio.h>
#include <string.h>
#include <cslr_device.h>
#include <csl_edma3.h>
#include <csl_edma3Aux.h>
#include <cslr_tcp3d_cfg.h>
#include <cslr_tcp3d_dma_offsets.h>
#include <cslr_tcp3d_dma.h>
/*----------------------------------------------*
 * macros                                       *
 *----------------------------------------------*/
#ifdef DEVICE_TN
#define  NUM_TCP3D                       3
#endif

#ifdef DEVICE_APPLETON
#define  NUM_TCP3D                       2
#endif

#define  TCP3D_MIN_ITERATIONS            1
#define  TCP3D_MAX_ITERATIONS            8

#define  TCP3D_IC_CFG_REGS_SIZE          60       /* TCP3D input IC Regs 15words */
#define  TCP3D_DMA_HALF_SYS_SIZE         0x1000
#define  TCP3D_DMA_SYS_PAR_OFFSET        0x2000

typedef struct
{
    /* PSC info */
	Uint32    udGlbPscModuleNum;
    Uint32    udLocalPscModuleNum;

    /* global configuration regs */
    CSL_Tcp3d_cfgRegs * ptTCP3dCfgReg;

    Uint32    udTcp3dDataRegsAddress;

    /* OUT EDMA CC and REVT0/REVT1 CHANNEL */
    Uint8     ucEdmaCCInst;
    Uint8     ucRevtEdmaChannel[2];  /* TCP3D_REVT0/1 EDMA channel */
} T_TCP3D_InstInfo;

typedef struct
{
    Uint32    udInICCfg;
    Uint32    udInSys;
    Uint32    udInPar0;
    Uint32    udInPar1;
    Uint32    udOutHD;
    Uint32    udOutStatus;
} T_TCP3D_DmaOffset;

#ifdef _BIG_ENDIAN
typedef struct
{
    /* IC0 */
    Uint32    rsvd0                    :3;
    Uint32    blockLen                 :13;     /* block size -1, code Block Length (39 - 8191) */
    Uint32    rsvd1                    :10;
    Uint32    num_sw0                  :6;      /* number of SW0s (0 - 62), 0=off */
    /* IC1 */
    Uint32    rsvd2                    :17;
    Uint32    sw1Len                   :7;      /* SW1 Length (9 - 127) */
    Uint32    rsvd3                    :2;
    Uint32    sw2LenSel                :2;      /* SW2 Length Selection value (0,1,2) */
    Uint32    rsvd4                    :1;
    Uint32    sw0LenSel                :3;      /* SW0 Length Selection value (0 - 5) */
    /* IC2 */
    Uint32    rsvd5                    :5;
    Uint32    crcPolySel               :1;      /* LTE CRC polynomial selection (0,1), 0=LTE CB CRC, 1=LTE TB CRC */
    Uint32    crcIterSel               :2;      /* LTE CRC consecutive matches for stopping (0 - 3 ) */
    Uint32    stopSel                  :2;      /* Stopping criteria selection (0 - 3), 0=iteration only, 1=iteration or CRC, 2/3=iteration or SNR */
    Uint32    snrReport                :1;      /* Enable/disable SNR reporting (0,1), 0=disabled, 1=enabled */
    Uint32    snrVal                   :5;      /*0~20 SNR threshold value in dB used as stopping criteria (0 - 20) */
    Uint32    maxIter                  :4;      /* Maximum iterations (0 - 15) */
    Uint32    minIter                  :4;      /* Minumun iterations (0 - 15) */
    Uint32    softOutFrmtSel           :1;      /* Soft output bit format (0,1), 0=truncated, 1=saturated */
    Uint32    softOutOrderSel          :1;      /* Soft output byte order (0,1) used only in BIG ENDIAN mode, 0=32bit packed,1=8bit native */
    Uint32    softOutRead              :1;      /* Enable/disable Soft outputs read via EDMA3 (0,1), 0=not read, 1=read */
    Uint32    extScaleEn               :1;      /* Enable/disable Extrinsic scaling (0,1), 0=disabled, 1=enable scale */
    Uint32    outOrderSel              :1;      /* bit ordering of hard decisions, 0=no swapping, 1=Output bit order swapping within 32-bit word (0,1) */
    Uint32    outStsRead               :1;      /* Enable/disable Output Status registers read via EDMA3 (0,1), 0=not read, 1=read */
    Uint32    maxStar                  :1;      /* Enable/disable Max Star (0,1), 0=disable,1=enable */
    Uint32    intLoadSel               :1;      /* 0=neither load nor generate, 1=load or generate, Interleaver Table load or generate selection (0,1) */
    /* IC3 */
    Uint32    rsvd6                    :10;
    Uint32    maxStarValue             :6;      /* Max Star Value (0 - 63), suggested values is 0.5, with the same Qformat with input softbits */
    Uint32    rsvd7                    :10;
    Uint32    maxStarThres             :6;      /* Max Star Threshold value (0 - 63), suggested values is 1, with the same Qformat with input softbits */
    /* IC4-IC7, Beta state */
    Uint8     betaMap0[8];                      /* IC4=Beta3~0, IC5=Beta7~4, Beta state values for MAP0 decoder */
    Uint8     betaMap1[8];                      /* IC6=Beta3~0, IC7=Beta7~4, Beta state values for MAP1 decoder */
    /* IC8-IC11, extrinsic scale register, each scale value has a Q(6,5)fixed point precision, for example 1=0x20 */
    Uint32    rsvd8                    :8;
    Uint32    extrScale3               :6;      /* Extrinsic scale values */
    Uint32    extrScale2               :6;      /* Extrinsic scale values */
    Uint32    extrScale1               :6;      /* Extrinsic scale values */
    Uint32    extrScale0               :6;      /* Extrinsic scale values */

    Uint32    rsvd9                    :8;
    Uint32    extrScale7               :6;      /* Extrinsic scale values */
    Uint32    extrScale6               :6;      /* Extrinsic scale values */
    Uint32    extrScale5               :6;      /* Extrinsic scale values */
    Uint32    extrScale4               :6;      /* Extrinsic scale values */

    Uint32    rsvd10                   :8;
    Uint32    extrScale11              :6;      /* Extrinsic scale values */
    Uint32    extrScale10              :6;      /* Extrinsic scale values */
    Uint32    extrScale9               :6;      /* Extrinsic scale values */
    Uint32    extrScale8               :6;      /* Extrinsic scale values */

    Uint32    rsvd11                   :8;
    Uint32    extrScale15              :6;      /* Extrinsic scale values */
    Uint32    extrScale14              :6;      /* Extrinsic scale values */
    Uint32    extrScale13              :6;      /* Extrinsic scale values */
    Uint32    extrScale12              :6;      /* Extrinsic scale values */

    /* IC12-IC14,  Interleaver Table Generation init params */
    Uint32    rsvd12                   :3;
    Uint32    itg_param1               :13;     /* LTE ITG: g(0) */
    Uint32    rsvd13                   :3;
    Uint32    itg_param0               :13;     /* LTE ITG: 2*f2 mod k */

    Uint32    rsvd14                   :3;
    Uint32    itg_param3               :13;     /* LTE ITG: pi(k/2) */
    Uint32    rsvd15                   :3;
    Uint32    itg_param2               :13;     /* LTE ITG: pi(k/4) */

    Uint32    rsvd16                   :19;
    Uint32    itg_param4               :13;     /* LTE ITG: pi(3k/4)  */
} T_Tcp3dICCfgParams;
#else
typedef struct
{
    /* IC0 */
	Uint32    num_sw0                  :6;      /* number of SW0s (0 - 62), 0=off */
	Uint32    rsvd1                    :10;
	Uint32    blockLen                 :13;     /* block size -1, code Block Length (39 - 8191) */
    Uint32    rsvd0                    :3;

    /* IC1 */
    Uint32    sw0LenSel                :3;      /* SW0 Length Selection value (0 - 5) */
    Uint32    rsvd4                    :1;
    Uint32    sw2LenSel                :2;      /* SW2 Length Selection value (0,1,2) */
    Uint32    rsvd3                    :2;
    Uint32    sw1Len                   :7;      /* SW1 Length (9 - 127) */
    Uint32    rsvd2                    :17;

    /* IC2 */
    Uint32    intLoadSel               :1;      /* 0=neither load nor generate, 1=load or generate, Interleaver Table load or generate selection (0,1) */
    Uint32    maxStar                  :1;      /* Enable/disable Max Star (0,1), 0=disable,1=enable */
    Uint32    outStsRead               :1;      /* Enable/disable Output Status registers read via EDMA3 (0,1), 0=not read, 1=read */
    Uint32    outOrderSel              :1;      /* bit ordering of hard decisions, 0=no swapping, 1=Output bit order swapping within 32-bit word (0,1) */
    Uint32    extScaleEn               :1;      /* Enable/disable Extrinsic scaling (0,1), 0=disabled, 1=enable scale */
    Uint32    softOutRead              :1;      /* Enable/disable Soft outputs read via EDMA3 (0,1), 0=not read, 1=read */
    Uint32    softOutOrderSel          :1;      /* Soft output byte order (0,1) used only in BIG ENDIAN mode, 0=32bit packed,1=8bit native */
    Uint32    softOutFrmtSel           :1;      /* Soft output bit format (0,1), 0=truncated, 1=saturated */
    Uint32    minIter                  :4;      /* Minumun iterations (0 - 15) */
    Uint32    maxIter                  :4;      /* Maximum iterations (0 - 15) */
    Uint32    snrVal                   :5;      /*0~20 SNR threshold value in dB used as stopping criteria (0 - 20) */
    Uint32    snrReport                :1;      /* Enable/disable SNR reporting (0,1), 0=disabled, 1=enabled */
    Uint32    stopSel                  :2;      /* Stopping criteria selection (0 - 3), 0=iteration only, 1=iteration or CRC, 2/3=iteration or SNR */
    Uint32    crcIterSel               :2;      /* LTE CRC consecutive matches for stopping (0 - 3 ) */
    Uint32    crcPolySel               :1;      /* LTE CRC polynomial selection (0,1), 0=LTE CB CRC, 1=LTE TB CRC */
    Uint32    rsvd5                    :5;

    /* IC3 */
    Uint32    maxStarThres             :6;      /* Max Star Threshold value (0 - 63), suggested values is 1, with the same Qformat with input softbits */
    Uint32    rsvd7                    :10;
    Uint32    maxStarValue             :6;      /* Max Star Value (0 - 63), suggested values is 0.5, with the same Qformat with input softbits */
    Uint32    rsvd6                    :10;

    /* IC4-IC7, Beta state */
    Uint8     betaMap0[8];                      /* IC4=Beta3~0, IC5=Beta7~4, Beta state values for MAP0 decoder */
    Uint8     betaMap1[8];                      /* IC6=Beta3~0, IC7=Beta7~4, Beta state values for MAP1 decoder */
    /* IC8-IC11, extrinsic scale register, each scale value has a Q(6,5)fixed point precision, for example 1=0x20 */
    Uint32    extrScale0               :6;      /* Extrinsic scale values */
    Uint32    extrScale1               :6;      /* Extrinsic scale values */
    Uint32    extrScale2               :6;      /* Extrinsic scale values */
    Uint32    extrScale3               :6;      /* Extrinsic scale values */
    Uint32    rsvd8                    :8;

    Uint32    extrScale4               :6;      /* Extrinsic scale values */
    Uint32    extrScale5               :6;      /* Extrinsic scale values */
    Uint32    extrScale6               :6;      /* Extrinsic scale values */
    Uint32    extrScale7               :6;      /* Extrinsic scale values */
    Uint32    rsvd9                    :8;

    Uint32    extrScale8               :6;      /* Extrinsic scale values */
    Uint32    extrScale9               :6;      /* Extrinsic scale values */
    Uint32    extrScale10              :6;      /* Extrinsic scale values */
    Uint32    extrScale11              :6;      /* Extrinsic scale values */
    Uint32    rsvd10                   :8;

    Uint32    extrScale12              :6;      /* Extrinsic scale values */
    Uint32    extrScale13              :6;      /* Extrinsic scale values */
    Uint32    extrScale14              :6;      /* Extrinsic scale values */
    Uint32    extrScale15              :6;      /* Extrinsic scale values */
    Uint32    rsvd11                   :8;

    /* IC12-IC14,  Interleaver Table Generation init params */
    Uint32    itg_param0               :13;     /* LTE ITG: 2*f2 mod k */
    Uint32    rsvd13                   :3;
    Uint32    itg_param1               :13;     /* LTE ITG: g(0) */
    Uint32    rsvd12                   :3;

    Uint32    itg_param2               :13;     /* LTE ITG: pi(k/4) */
    Uint32    rsvd15                   :3;
    Uint32    itg_param3               :13;     /* LTE ITG: pi(k/2) */
    Uint32    rsvd14                   :3;

    Uint32    itg_param4               :13;     /* LTE ITG: pi(3k/4)  */
    Uint32    rsvd16                   :19;
} T_Tcp3dICCfgParams;
#endif
/*----------------------------------------------*
 * input resource structure for initialization
 *----------------------------------------------*/
/* hardware resource for TCP3D process */
typedef struct
{
	Uint8     ucTCPId;           /* TCP3D instance index */

    /* EDMA resource for TCP3D in/out;
     * Below [2] support double buffer and split mode (proc0, proc1), each proc has one configurable resource respectively
     * two input channels are used for double buffer mode and split mode(LTE&Wimax&3GPP) */
    Uint8     ucInEdmaTpcc;         /* select the same EDMA CC for in/out channel */
    Uint8     ucInEdmaTc[2];
    Uint8     ucInEdmaCh[2];        /* input EDMA channel */
    Uint8     ucOutEdmaTc[2];       /* output EDMA CC and channel is fixed, only the TC can be configured */
    /* start PaRAM set index for In/out respectively */
    Uint16    uwInPaRAMSetStartIdx;  /* num=4+2*(support total block number) */
    Uint16    uwOutPaRAMSetStartIdx; /* num=4+2*(support total block number) */
} T_TCP3D_ResInfo;

/* Resource for specific application
 * input data format: with ENDIAN_INDATA=1 for 8-bit native mode, only effect for big endian
 * Low address,     high address
 * LLR0, LLR1, ... , LLR15
 * hard bit output format
 * LSB,              MSB
 * BIT0, BIT1, ... , BIT127
 * OUT_ORDER_SEL = 1 for both big and little endian;
 * default only output the hardbit and status, while don't output the softbit */
typedef struct
{
	/* mode control, TCP3D_MODE, single buffer mode is not supported as double buffer mode is more efficiency.
	 * default with auto-trigger enabled, double buffer mode for Wimax and LTE, split mode for WCDMA  */
    Uint8     ucModeSel;    /* LTE/WCDMA/Wimax, 1-LTE double buffer mode, 2-Wimax double buffer mode, 3-WCDMA split mode, */

    Uint8     ucStopSel;    /* 0-Max iteration only, 1-CRC for LTE, 2/3-SNR */
    Uint8     ucMaxItr;     /* maximum number of iterations, 0~15, default with minimum iteration=1 */
    Uint8     ucSNRVal;     /* SNR threshold for SNR stop mode, default with 0db */
} T_TCP3D_ComAppInfo; /* common para for all the decode block */

/*----------------------------------------------*
 * input resource structure for TTI configure para per block
 *----------------------------------------------*/
typedef struct
{
    Uint8     ucCrcSel;     /* 0-CB CRC, 1-TB CRC, used for LTE mode */
    Uint16    uwBlockSize;  /* turbo decoder block size in bit, not include the tailing bits */
    Uint8     ucInitSw0Len; /* init value for sliding length cal, default with 64bit, range = {16, 32, 48,  64, 96, 128} */

    /* Note: All the below address is need to be globa, need to convert to global for LL2 address */
    /* Input IC configuration address */
    Uint32    *pudInICCfg;

    /* input systematic and parity LLR address */
    Int8     *pscInputSysLLR; /* need to add tail and dummy bit when K is not multiple of 4, refer to TCP3D UG3.3.5 */
    Int8     *pscInputP0LLR;  /* > pucInputSysLLR */
    Int8     *pscInputP1LLR;  /* > pucInputP0LLR */
    Int8     *pscTailBits;    /* 12tail bits for beta state calc, xt1[0]pt1[0]xt1[1]pt1[1]xt1[2]pt1[2]xt2[0]pt2[0]xt2[1]pt2[1]xt2[2]pt2[2] */

    /* output hardbit and status address */
    Uint8     *pucOutHardBit;
    Uint32    *pudOutStatus;
} T_TCP3D_BlockInfo;

/* record TCP3D handle for init/config and debug */
typedef struct
{
	Uint8     ucTCPId;
	Uint8     ucModeSel;

	Uint8     ucMaxSupportPingPongBlockNum[2];  /* compute the block number for ping pong respectively */

    /* in/out EDMA channel parameters update */
	CSL_Edma3ChannelObj atInEdmaObj[2];
	Uint16    uwInChMapPaRAMSetIdx[2];     /* ping-pong channel's direct map PaRAM set */
	Uint16    uwInUePaRAMSetStartIdx[2];   /* start PaRAM set index for UE IC/LLR config */
	CSL_TPCC_ParamsetRegs *ptInUeStartPaRAMRegs[2];  /* start PaRAM set address for ue IC/LLR config */

	CSL_Edma3ChannelObj atOutEdmaObj[2];
	Uint16    uwOutChMapPaRAMSetStartIdx[2];
	Uint16    uwOutUePaRAMSetStartIdx[2];
	CSL_TPCC_ParamsetRegs *ptOutUeStartPaRAMRegs[2];  /* start PaRAM set address */
} T_TCP3D_Hdl;

/* EDMA structure for BCP 1st stage de-interleaver */
typedef struct
{
	Uint8        ucSyncDim; /* 0-A-sync, 1-AB-sync */
    Uint8        ucTCC;
    Uint8        ucItcchEn;
    Uint8        ucTcchEn;
    Uint8        ucItcintEn;
    Uint8        ucTcintEn;
    Uint16       uwAcnt;
    Uint16       uwBcnt;
    Uint16       uwCcnt;
    Uint16       uwSrcBidx;
    Uint16       uwDstBidx;
    Uint16       uwSrcCidx;
    Uint16       uwDstCidx;
    Uint16       uwLinkPaRAMSetIdx;

    Uint32       udSrcAddr;
    Uint32       udDstAddr;
} T_Tcp3d_EdmaPara;

extern const T_TCP3D_InstInfo gtTcp3dInstInfo[NUM_TCP3D];
extern const T_TCP3D_DmaOffset gtTcp3dDmaOffset[2];
/*************************************************************************************************************************/
extern Int16 Keystone_TCP3D_Init(void                    * restrict pTcp3dHdl,
		                         T_TCP3D_ResInfo         * restrict ptTcp3dResInfo,
		                         T_TCP3D_ComAppInfo      * restrict ptTcp3dComAppInfo,
		                 		 T_Tcp3dICCfgParams      * restrict ptTcp3dICCfgBuf,
		                 		 Uint8                              ucMaxSupportBlockNum
		                         );

extern Int16 Keystone_TCP3D_TTICfg(void                    * restrict pTcp3dHdl,
		                           T_TCP3D_BlockInfo       * restrict ptTcp3dBlockInfoAddr,
		                   		   Uint8                   * restrict ucBlockNumPerUe,
		                   		   Uint8                              ucCurUeNum);

extern Int16 Keystone_TCP3D_PollFree(void                  * restrict pTcp3dHdl,
		                             Uint8                            ucLastProcBlockNum);

extern Int16 Keystone_TCP3D_Submit(void                    * restrict pTcp3dHdl,
		                           Uint8                              ucBlockNum);

extern Int16 Keystone_TCP3D_PostProc(Uint8 ucMode, Uint8 ucBlockNum, Uint32 *pudDecStatus, Uint8 *pucStatus);

#endif

/*************************************************************************************************************************/

