/*****************************************************************************
*            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
*
*   Property of Texas Instruments
*   For  Unrestricted  Internal  Use  Only
*   Unauthorized reproduction and/or distribution is strictly prohibited.
*   This product is protected under copyright law and trade secret law
*   as an unpublished work.
*   Created 2003, (C) Copyright 2003 Texas Instruments.  All rights reserved.
*
*   File content:        C file
*
*   Filename:            GIC_CTL.c
*
*   Description:         GIC library function configures the MPU interrupt 
*                        handler with basic functions like routing (to fiq 
*                        or irq) ,enabling ,prioritizing, masking each 
*                        interrupt.
*
*   Module name:         GIC
*
*   Module version:      1.0
*
*****************************************************************************/
/*****************************************************************************
* INCLUDE FILES
******************************************************************************
*/

#ifndef _GIC_CTL_H_
#define _GIC_CTL_H_

extern void regByteWrite(Uint32 regAddress, Uint8 regOffset, Uint8 regValue);

/*
****************************************************************************
* GIC Distributor FUNCTIONS
******************************************************************************
*/

/****************************************************************************** 
 * Global and Group Enable/Disable (GICD_CTLR) - Assumed Secure Mode
 ******************************************************************************/
ReturnCode_t GICD_Global_Enable_Disable(CSL_Cortexa15GICRegs *gicHandle,
                                        INTH_Group_t         intGroup,
                                        const INTH_Action_t  intAction);

/****************************************************************************** 
 * Enable/Disable Interrupts (GICD_ISENABLEn/GICD_ICENABLEn)
 ******************************************************************************/
#ifndef _SECURE_DEVICE
void GICD_Intr_Enable_Disable(CSL_Cortexa15GICRegs *gicHandle,
                                Uint32              intVector,
                                INTH_Action_t       intAction);
#else
Uint32 GICD_Intr_Enable_Disable(unsigned int (*fcn_p)(),
                                Uint32 gicHandle,
                                Uint32  intVector,
                                Uint32  intAction);
#endif

/****************************************************************************** 
 * Level/Edge triggered event config (GICD_ICFGRn)
 ******************************************************************************/
//TODO:

/****************************************************************************** 
 * Generate SGI (GICD_SGIR)
 ******************************************************************************/
ReturnCode_t GICD_TriggerSGI(CSL_Cortexa15GICRegs         *gicHandle,
                             const Uint8                sgiID, 
                             const INTH_SGI_Target_Mode_t trgtType, 
                             const Uint8                trgtList);

/*
 * Get pending int (GICD_ISPENDRn)
 */
ReturnCode_t GICD_Set_Pending(CSL_Cortexa15GICRegs *gicHandle, 
                              Uint32 intVector);

/*
 * Clear Pending state (GICD_ICPENDRn)
 */
ReturnCode_t GICD_Clear_Pending(CSL_Cortexa15GICRegs *gicHandle, 
                                Uint32 intVector);

/*
 *  Set int to ACTIVE state(GICD_ISACTIVERn)
 */
void GICD_Set_Active(CSL_Cortexa15GICRegs *gicHandle, Uint32 intVector);

/*
 * Clear ACTIVE state for int. (GICD_ICACTIVERn)
 */
void GICD_Clear_Active(CSL_Cortexa15GICRegs *gicHandle, Uint32 intVector);

/****************************************************************************** 
 * Map iterrupt to group.
 ******************************************************************************/
#ifndef _SECURE_DEVICE
void  GICD_Set_Intr_Group(CSL_Cortexa15GICRegs  *gicHandle,
                           Uint32 intVector,
                           INTH_Group_t intGroup);
#else
Uint32 GICD_Set_Intr_Group(unsigned int (*fcn_p)(),
                           Uint32 gicHandle,
                           Uint32   intVector,
                           Uint32   intGroup);
#endif
/****************************************************************************** 
 * Set Group1 Interrupt Priority.
 ******************************************************************************/
void GICD_Set_Group1_Intr_Priority(CSL_Cortexa15GICRegs  *gicHandle,
                                   const Uint32        intVector,
                                   const INTH_Priority_t intPriority);

/****************************************************************************** 
 * Set Targets for interrupt. (Assumed Secure access)
 ******************************************************************************/
#ifndef _SECURE_DEVICE
void GICD_Set_Intr_Targets(CSL_Cortexa15GICRegs *gicHandle,
                             Uint32               intVector,
                             Uint8                intTargetMask);
#else
Uint32 GICD_Set_Intr_Targets(unsigned int (*fcn_p)(),
                             Uint32 gicHandle,
                             Uint32 intVector,
                             Uint32 intTargetMask);
#endif

/****************************************************************************** 
 * Initialize GIC Distributor
 ******************************************************************************/
//Uint32 GICD_InitDistributor(CSL_Cortexa15GICRegs *gicHandle);

/*
****************************************************************************
* GIC CPU Interface FUNCTIONS
******************************************************************************
*/

/*******************************************************************
 * Initialize GIC CPU INterface - (Assumed Secure Mode)
 *
 *  GICC_CTLR
 *
 *  EnableGrp0    - 1 (Enable)
 *  EnableGrp1    - 1 (Enable)
 *  AckCtl        - 0
 *  FIQEn         - 1 (Group0 routed to FIQ)
 *  CBPR          - 0
 *  FIQBypDisGrp0 - 0 (Don't Care)
 *  IRQBypDisGrp0 - 0 (Don't Care)
 *  FIQBypDisGrp1 - 0 (Don't Care)
 *  IRQBypDisGrp1 - 0 (Don't Care)
 *  EOImodeS      - 1 (Priority drop and deactivation seperated)
 *  EOImodeNS     - 1 (Priority drop and deactivation seperated)
 ******************************************************************/
//Uint32 GICC_InitCPUInterface(CSL_Cortexa15GICRegs *gicHandle);

/*
 * Acknowledge interrupt (GICC_IAR/GICC_AIAR)
 */
Uint32 GICC_GetIntId(CSL_Cortexa15GICRegs *gicHandle);
//Uint32 GICC_GetIntId(unsigned int (*fcn_p)(),Uint32 xgicHandle, Uint32 xvecId);

/*
 * Signal End-of-Interrupt (GICC_EOIR/GICC_AEOIR)
 */
void GICC_EndOfInt(CSL_Cortexa15GICRegs *gicHandle, Uint32 eoiId);

/*
 * Deactivate Interrupt (GICC_DIR)
 */
void GICC_DeactInt(CSL_Cortexa15GICRegs *gicHandle, Uint32 eoiId);

/***************************************************************************
 * GIC Interface Functions 
 **************************************************************************/

void GIC_Init(CSL_Cortexa15GICRegs *gicHandle);

#endif // _GIC_CTL_H_
