/********************************************************************
* Copyright (C) 2003-2008 Texas Instruments Incorporated.
* All Rights Reserved
*********************************************************************
* file: cslr_cortexa15_r2p0_0.h
*
* Brief: This file contains the Register Description for cortexa15
*
*********************************************************************/
#ifndef _CSLR_CORTEXA15_GIC400_R2P0_0_H_
#define _CSLR_CORTEXA15_GIC400_R2P0_0_H_

//#include <cslr.h>

#include <ti/csl/tistdtypes.h>

/* Minimum unit = 1 byte */

typedef unsigned long Uint64;

/**************************************************************************\
* Register Overlay Structure for PMX
\**************************************************************************/
typedef struct  {
    volatile Uint32 PMXEVCNTR0;
    volatile Uint32 PMXEVCNTR1;
    volatile Uint32 PMXEVCNTR2;
    volatile Uint32 PMXEVCNTR3;
    volatile Uint32 PMXEVCNTR4;
    volatile Uint32 PMXEVCNTR5;
    volatile Uint8 RSVD0[100];
    volatile Uint32 PMCCNTR;
    volatile Uint8 RSVD1[896];
    volatile Uint32 PMXEVTYPER0;
    volatile Uint32 PMXEVTYPER1;
    volatile Uint32 PMXEVTYPER2;
    volatile Uint32 PMXEVTYPER3;
    volatile Uint32 PMXEVTYPER4;
    volatile Uint32 PMXEVTYPER5;
    volatile Uint8 RSVD2[100];
    volatile Uint32 PMCCFILTR;
    volatile Uint8 RSVD3[1920];
    volatile Uint32 PMCNTENSET;
    volatile Uint8 RSVD4[28];
    volatile Uint32 PMCNTENCLR;
    volatile Uint8 RSVD5[28];
    volatile Uint32 PMINTENSET;
    volatile Uint8 RSVD6[28];
    volatile Uint32 PMINTENCLR;
    volatile Uint8 RSVD7[28];
    volatile Uint32 PMOVSR;
    volatile Uint8 RSVD8[28];
    volatile Uint32 PMSWINC;
    volatile Uint8 RSVD9[348];
    volatile Uint32 PMCFGR;
    volatile Uint32 PMCR;
    volatile Uint32 PMUSERENR;
    volatile Uint8 RSVD10[20];
    volatile Uint32 PMCEID0;
    volatile Uint32 PMCEID1;
    volatile Uint8 RSVD11[392];
    volatile Uint32 PMLAR;
    volatile Uint32 PMLSR;
    volatile Uint32 PMAUTHSTATUS;
    volatile Uint8 RSVD12[16];
    volatile Uint32 PMDEVTYPE;
    volatile Uint32 PMPID4;
    volatile Uint32 PMPID5;
    volatile Uint32 PMPID6;
    volatile Uint32 PMPID7;
    volatile Uint32 PMPID0;
    volatile Uint32 PMPID1;
    volatile Uint32 PMPID2;
    volatile Uint32 PMPID3;
    volatile Uint32 PMCID0;
    volatile Uint32 PMCID1;
    volatile Uint32 PMCID2;
    volatile Uint32 PMCID3;
} CSL_Cortexa15PmxRegs;

/**************************************************************************\
* Register Overlay Structure for Distributer
\**************************************************************************/
#define MAX_GIC400_INTC_INTERFACES 8
#define MAX_GIC_SGI                16
#define NUM_GIC400_INTC_EVENTS     512   // 32 PPIs + 480 SPIs
typedef struct  {
    volatile Uint32 GICD_DCR;
    volatile Uint32 GICD_ICTR;
    volatile Uint32 GICD_IIDR;
    volatile Uint8 RSVD0[116];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_IGRP[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_IGRP0;
    volatile Uint32 GICD_IGRP1;
    volatile Uint32 GICD_IGRP2;
    volatile Uint32 GICD_IGRP3;
    volatile Uint32 GICD_IGRP4;
    volatile Uint32 GICD_IGRP5;
    volatile Uint32 GICD_IGRP6;
    volatile Uint32 GICD_IGRP7;
    volatile Uint32 GICD_IGRP8;
    volatile Uint32 GICD_IGRP9;
    volatile Uint32 GICD_IGRP10;
    volatile Uint32 GICD_IGRP11;
    volatile Uint32 GICD_IGRP12;
    volatile Uint32 GICD_IGRP13;
    volatile Uint32 GICD_IGRP14;
    volatile Uint32 GICD_IGRP15;
#endif
    volatile Uint8 RSVD1[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ISER[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ISER0;
    volatile Uint32 GICD_ISER1;
    volatile Uint32 GICD_ISER2;
    volatile Uint32 GICD_ISER3;
    volatile Uint32 GICD_ISER4;
    volatile Uint32 GICD_ISER5;
    volatile Uint32 GICD_ISER6;
    volatile Uint32 GICD_ISER7;
    volatile Uint32 GICD_ISER8;
    volatile Uint32 GICD_ISER9;
    volatile Uint32 GICD_ISER10;
    volatile Uint32 GICD_ISER11;
    volatile Uint32 GICD_ISER12;
    volatile Uint32 GICD_ISER13;
    volatile Uint32 GICD_ISER14;
    volatile Uint32 GICD_ISER15;
#endif
    volatile Uint8 RSVD2[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ICER[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ICER0;
    volatile Uint32 GICD_ICER1;
    volatile Uint32 GICD_ICER2;
    volatile Uint32 GICD_ICER3;
    volatile Uint32 GICD_ICER4;
    volatile Uint32 GICD_ICER5;
    volatile Uint32 GICD_ICER6;
    volatile Uint32 GICD_ICER7;
    volatile Uint32 GICD_ICER8;
    volatile Uint32 GICD_ICER9;
    volatile Uint32 GICD_ICER10;
    volatile Uint32 GICD_ICER11;
    volatile Uint32 GICD_ICER12;
    volatile Uint32 GICD_ICER13;
    volatile Uint32 GICD_ICER14;
    volatile Uint32 GICD_ICER15;
#endif
    volatile Uint8 RSVD3[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ISPR[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ISPR0;
    volatile Uint32 GICD_ISPR1;
    volatile Uint32 GICD_ISPR2;
    volatile Uint32 GICD_ISPR3;
    volatile Uint32 GICD_ISPR4;
    volatile Uint32 GICD_ISPR5;
    volatile Uint32 GICD_ISPR6;
    volatile Uint32 GICD_ISPR7;
    volatile Uint32 GICD_ISPR8;
    volatile Uint32 GICD_ISPR9;
    volatile Uint32 GICD_ISPR10;
    volatile Uint32 GICD_ISPR11;
    volatile Uint32 GICD_ISPR12;
    volatile Uint32 GICD_ISPR13;
    volatile Uint32 GICD_ISPR14;
    volatile Uint32 GICD_ISPR15;
#endif
    volatile Uint8 RSVD4[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ICPR[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ICPR0;
    volatile Uint32 GICD_ICPR1;
    volatile Uint32 GICD_ICPR2;
    volatile Uint32 GICD_ICPR3;
    volatile Uint32 GICD_ICPR4;
    volatile Uint32 GICD_ICPR5;
    volatile Uint32 GICD_ICPR6;
    volatile Uint32 GICD_ICPR7;
    volatile Uint32 GICD_ICPR8;
    volatile Uint32 GICD_ICPR9;
    volatile Uint32 GICD_ICPR10;
    volatile Uint32 GICD_ICPR11;
    volatile Uint32 GICD_ICPR12;
    volatile Uint32 GICD_ICPR13;
    volatile Uint32 GICD_ICPR14;
    volatile Uint32 GICD_ICPR15;
#endif
    volatile Uint8 RSVD5[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ISACTIVER[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ISACTIVER0;
    volatile Uint32 GICD_ISACTIVER1;
    volatile Uint32 GICD_ISACTIVER2;
    volatile Uint32 GICD_ISACTIVER3;
    volatile Uint32 GICD_ISACTIVER4;
    volatile Uint32 GICD_ISACTIVER5;
    volatile Uint32 GICD_ISACTIVER6;
    volatile Uint32 GICD_ISACTIVER7;
    volatile Uint32 GICD_ISACTIVER8;
    volatile Uint32 GICD_ISACTIVER9;
    volatile Uint32 GICD_ISACTIVER10;
    volatile Uint32 GICD_ISACTIVER11;
    volatile Uint32 GICD_ISACTIVER12;
    volatile Uint32 GICD_ISACTIVER13;
    volatile Uint32 GICD_ISACTIVER14;
    volatile Uint32 GICD_ISACTIVER15;
#endif
    volatile Uint8 RSVD6[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ICACTIVER[NUM_GIC400_INTC_EVENTS>>5];
#else
    volatile Uint32 GICD_ICACTIVER0;
    volatile Uint32 GICD_ICACTIVER1;
    volatile Uint32 GICD_ICACTIVER2;
    volatile Uint32 GICD_ICACTIVER3;
    volatile Uint32 GICD_ICACTIVER4;
    volatile Uint32 GICD_ICACTIVER5;
    volatile Uint32 GICD_ICACTIVER6;
    volatile Uint32 GICD_ICACTIVER7;
    volatile Uint32 GICD_ICACTIVER8;
    volatile Uint32 GICD_ICACTIVER9;
    volatile Uint32 GICD_ICACTIVER10;
    volatile Uint32 GICD_ICACTIVER11;
    volatile Uint32 GICD_ICACTIVER12;
    volatile Uint32 GICD_ICACTIVER13;
    volatile Uint32 GICD_ICACTIVER14;
    volatile Uint32 GICD_ICACTIVER15;
#endif
    volatile Uint8 RSVD7[64];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_IPRIORITYR[NUM_GIC400_INTC_EVENTS>>2];
#else
    volatile Uint32 GICD_IPRIORITYR0;
    volatile Uint32 GICD_IPRIORITYR1;
    volatile Uint32 GICD_IPRIORITYR2;
    volatile Uint32 GICD_IPRIORITYR3;
    volatile Uint32 GICD_IPRIORITYR4;
    volatile Uint32 GICD_IPRIORITYR5;
    volatile Uint32 GICD_IPRIORITYR6;
    volatile Uint32 GICD_IPRIORITYR7;
    volatile Uint32 GICD_IPRIORITYR8;
    volatile Uint32 GICD_IPRIORITYR9;
    volatile Uint32 GICD_IPRIORITYR10;
    volatile Uint32 GICD_IPRIORITYR11;
    volatile Uint32 GICD_IPRIORITYR12;
    volatile Uint32 GICD_IPRIORITYR13;
    volatile Uint32 GICD_IPRIORITYR14;
    volatile Uint32 GICD_IPRIORITYR15;
    volatile Uint32 GICD_IPRIORITYR16;
    volatile Uint32 GICD_IPRIORITYR17;
    volatile Uint32 GICD_IPRIORITYR18;
    volatile Uint32 GICD_IPRIORITYR19;
    volatile Uint32 GICD_IPRIORITYR20;
    volatile Uint32 GICD_IPRIORITYR21;
    volatile Uint32 GICD_IPRIORITYR22;
    volatile Uint32 GICD_IPRIORITYR23;
    volatile Uint32 GICD_IPRIORITYR24;
    volatile Uint32 GICD_IPRIORITYR25;
    volatile Uint32 GICD_IPRIORITYR26;
    volatile Uint32 GICD_IPRIORITYR27;
    volatile Uint32 GICD_IPRIORITYR28;
    volatile Uint32 GICD_IPRIORITYR29;
    volatile Uint32 GICD_IPRIORITYR30;
    volatile Uint32 GICD_IPRIORITYR31;
    volatile Uint32 GICD_IPRIORITYR32;
    volatile Uint32 GICD_IPRIORITYR33;
    volatile Uint32 GICD_IPRIORITYR34;
    volatile Uint32 GICD_IPRIORITYR35;
    volatile Uint32 GICD_IPRIORITYR36;
    volatile Uint32 GICD_IPRIORITYR37;
    volatile Uint32 GICD_IPRIORITYR38;
    volatile Uint32 GICD_IPRIORITYR39;
    volatile Uint32 GICD_IPRIORITYR40;
    volatile Uint32 GICD_IPRIORITYR41;
    volatile Uint32 GICD_IPRIORITYR42;
    volatile Uint32 GICD_IPRIORITYR43;
    volatile Uint32 GICD_IPRIORITYR44;
    volatile Uint32 GICD_IPRIORITYR45;
    volatile Uint32 GICD_IPRIORITYR46;
    volatile Uint32 GICD_IPRIORITYR47;
    volatile Uint32 GICD_IPRIORITYR48;
    volatile Uint32 GICD_IPRIORITYR49;
    volatile Uint32 GICD_IPRIORITYR50;
    volatile Uint32 GICD_IPRIORITYR51;
    volatile Uint32 GICD_IPRIORITYR52;
    volatile Uint32 GICD_IPRIORITYR53;
    volatile Uint32 GICD_IPRIORITYR54;
    volatile Uint32 GICD_IPRIORITYR55;
    volatile Uint32 GICD_IPRIORITYR56;
    volatile Uint32 GICD_IPRIORITYR57;
    volatile Uint32 GICD_IPRIORITYR58;
    volatile Uint32 GICD_IPRIORITYR59;
    volatile Uint32 GICD_IPRIORITYR60;
    volatile Uint32 GICD_IPRIORITYR61;
    volatile Uint32 GICD_IPRIORITYR62;
    volatile Uint32 GICD_IPRIORITYR63;
    volatile Uint32 GICD_IPRIORITYR64;
    volatile Uint32 GICD_IPRIORITYR65;
    volatile Uint32 GICD_IPRIORITYR66;
    volatile Uint32 GICD_IPRIORITYR67;
    volatile Uint32 GICD_IPRIORITYR68;
    volatile Uint32 GICD_IPRIORITYR69;
    volatile Uint32 GICD_IPRIORITYR70;
    volatile Uint32 GICD_IPRIORITYR71;
    volatile Uint32 GICD_IPRIORITYR72;
    volatile Uint32 GICD_IPRIORITYR73;
    volatile Uint32 GICD_IPRIORITYR74;
    volatile Uint32 GICD_IPRIORITYR75;
    volatile Uint32 GICD_IPRIORITYR76;
    volatile Uint32 GICD_IPRIORITYR77;
    volatile Uint32 GICD_IPRIORITYR78;
    volatile Uint32 GICD_IPRIORITYR79;
    volatile Uint32 GICD_IPRIORITYR80;
    volatile Uint32 GICD_IPRIORITYR81;
    volatile Uint32 GICD_IPRIORITYR82;
    volatile Uint32 GICD_IPRIORITYR83;
    volatile Uint32 GICD_IPRIORITYR84;
    volatile Uint32 GICD_IPRIORITYR85;
    volatile Uint32 GICD_IPRIORITYR86;
    volatile Uint32 GICD_IPRIORITYR87;
    volatile Uint32 GICD_IPRIORITYR88;
    volatile Uint32 GICD_IPRIORITYR89;
    volatile Uint32 GICD_IPRIORITYR90;
    volatile Uint32 GICD_IPRIORITYR91;
    volatile Uint32 GICD_IPRIORITYR92;
    volatile Uint32 GICD_IPRIORITYR93;
    volatile Uint32 GICD_IPRIORITYR94;
    volatile Uint32 GICD_IPRIORITYR95;
    volatile Uint32 GICD_IPRIORITYR96;
    volatile Uint32 GICD_IPRIORITYR97;
    volatile Uint32 GICD_IPRIORITYR98;
    volatile Uint32 GICD_IPRIORITYR99;
    volatile Uint32 GICD_IPRIORITYR100;
    volatile Uint32 GICD_IPRIORITYR101;
    volatile Uint32 GICD_IPRIORITYR102;
    volatile Uint32 GICD_IPRIORITYR103;
    volatile Uint32 GICD_IPRIORITYR104;
    volatile Uint32 GICD_IPRIORITYR105;
    volatile Uint32 GICD_IPRIORITYR106;
    volatile Uint32 GICD_IPRIORITYR107;
    volatile Uint32 GICD_IPRIORITYR108;
    volatile Uint32 GICD_IPRIORITYR109;
    volatile Uint32 GICD_IPRIORITYR110;
    volatile Uint32 GICD_IPRIORITYR111;
    volatile Uint32 GICD_IPRIORITYR112;
    volatile Uint32 GICD_IPRIORITYR113;
    volatile Uint32 GICD_IPRIORITYR114;
    volatile Uint32 GICD_IPRIORITYR115;
    volatile Uint32 GICD_IPRIORITYR116;
    volatile Uint32 GICD_IPRIORITYR117;
    volatile Uint32 GICD_IPRIORITYR118;
    volatile Uint32 GICD_IPRIORITYR119;
    volatile Uint32 GICD_IPRIORITYR120;
    volatile Uint32 GICD_IPRIORITYR121;
    volatile Uint32 GICD_IPRIORITYR122;
    volatile Uint32 GICD_IPRIORITYR123;
    volatile Uint32 GICD_IPRIORITYR124;
    volatile Uint32 GICD_IPRIORITYR125;
    volatile Uint32 GICD_IPRIORITYR126;
    volatile Uint32 GICD_IPRIORITYR127;
#endif
    volatile Uint8 RSVD8[512];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_IPTARGETR[NUM_GIC400_INTC_EVENTS>>2];
#else
    volatile Uint32 GICD_IPTARGETR0;
    volatile Uint32 GICD_IPTARGETR1;
    volatile Uint32 GICD_IPTARGETR2;
    volatile Uint32 GICD_IPTARGETR3;
    volatile Uint32 GICD_IPTARGETR4;
    volatile Uint32 GICD_IPTARGETR5;
    volatile Uint32 GICD_IPTARGETR6;
    volatile Uint32 GICD_IPTARGETR7;
    volatile Uint32 GICD_IPTARGETR8;
    volatile Uint32 GICD_IPTARGETR9;
    volatile Uint32 GICD_IPTARGETR10;
    volatile Uint32 GICD_IPTARGETR11;
    volatile Uint32 GICD_IPTARGETR12;
    volatile Uint32 GICD_IPTARGETR13;
    volatile Uint32 GICD_IPTARGETR14;
    volatile Uint32 GICD_IPTARGETR15;
    volatile Uint32 GICD_IPTARGETR16;
    volatile Uint32 GICD_IPTARGETR17;
    volatile Uint32 GICD_IPTARGETR18;
    volatile Uint32 GICD_IPTARGETR19;
    volatile Uint32 GICD_IPTARGETR20;
    volatile Uint32 GICD_IPTARGETR21;
    volatile Uint32 GICD_IPTARGETR22;
    volatile Uint32 GICD_IPTARGETR23;
    volatile Uint32 GICD_IPTARGETR24;
    volatile Uint32 GICD_IPTARGETR25;
    volatile Uint32 GICD_IPTARGETR26;
    volatile Uint32 GICD_IPTARGETR27;
    volatile Uint32 GICD_IPTARGETR28;
    volatile Uint32 GICD_IPTARGETR29;
    volatile Uint32 GICD_IPTARGETR30;
    volatile Uint32 GICD_IPTARGETR31;
    volatile Uint32 GICD_IPTARGETR32;
    volatile Uint32 GICD_IPTARGETR33;
    volatile Uint32 GICD_IPTARGETR34;
    volatile Uint32 GICD_IPTARGETR35;
    volatile Uint32 GICD_IPTARGETR36;
    volatile Uint32 GICD_IPTARGETR37;
    volatile Uint32 GICD_IPTARGETR38;
    volatile Uint32 GICD_IPTARGETR39;
    volatile Uint32 GICD_IPTARGETR40;
    volatile Uint32 GICD_IPTARGETR41;
    volatile Uint32 GICD_IPTARGETR42;
    volatile Uint32 GICD_IPTARGETR43;
    volatile Uint32 GICD_IPTARGETR44;
    volatile Uint32 GICD_IPTARGETR45;
    volatile Uint32 GICD_IPTARGETR46;
    volatile Uint32 GICD_IPTARGETR47;
    volatile Uint32 GICD_IPTARGETR48;
    volatile Uint32 GICD_IPTARGETR49;
    volatile Uint32 GICD_IPTARGETR50;
    volatile Uint32 GICD_IPTARGETR51;
    volatile Uint32 GICD_IPTARGETR52;
    volatile Uint32 GICD_IPTARGETR53;
    volatile Uint32 GICD_IPTARGETR54;
    volatile Uint32 GICD_IPTARGETR55;
    volatile Uint32 GICD_IPTARGETR56;
    volatile Uint32 GICD_IPTARGETR57;
    volatile Uint32 GICD_IPTARGETR58;
    volatile Uint32 GICD_IPTARGETR59;
    volatile Uint32 GICD_IPTARGETR60;
    volatile Uint32 GICD_IPTARGETR61;
    volatile Uint32 GICD_IPTARGETR62;
    volatile Uint32 GICD_IPTARGETR63;
    volatile Uint32 GICD_IPTARGETR64;
    volatile Uint32 GICD_IPTARGETR65;
    volatile Uint32 GICD_IPTARGETR66;
    volatile Uint32 GICD_IPTARGETR67;
    volatile Uint32 GICD_IPTARGETR68;
    volatile Uint32 GICD_IPTARGETR69;
    volatile Uint32 GICD_IPTARGETR70;
    volatile Uint32 GICD_IPTARGETR71;
    volatile Uint32 GICD_IPTARGETR72;
    volatile Uint32 GICD_IPTARGETR73;
    volatile Uint32 GICD_IPTARGETR74;
    volatile Uint32 GICD_IPTARGETR75;
    volatile Uint32 GICD_IPTARGETR76;
    volatile Uint32 GICD_IPTARGETR77;
    volatile Uint32 GICD_IPTARGETR78;
    volatile Uint32 GICD_IPTARGETR79;
    volatile Uint32 GICD_IPTARGETR80;
    volatile Uint32 GICD_IPTARGETR81;
    volatile Uint32 GICD_IPTARGETR82;
    volatile Uint32 GICD_IPTARGETR83;
    volatile Uint32 GICD_IPTARGETR84;
    volatile Uint32 GICD_IPTARGETR85;
    volatile Uint32 GICD_IPTARGETR86;
    volatile Uint32 GICD_IPTARGETR87;
    volatile Uint32 GICD_IPTARGETR88;
    volatile Uint32 GICD_IPTARGETR89;
    volatile Uint32 GICD_IPTARGETR90;
    volatile Uint32 GICD_IPTARGETR91;
    volatile Uint32 GICD_IPTARGETR92;
    volatile Uint32 GICD_IPTARGETR93;
    volatile Uint32 GICD_IPTARGETR94;
    volatile Uint32 GICD_IPTARGETR95;
    volatile Uint32 GICD_IPTARGETR96;
    volatile Uint32 GICD_IPTARGETR97;
    volatile Uint32 GICD_IPTARGETR98;
    volatile Uint32 GICD_IPTARGETR99;
    volatile Uint32 GICD_IPTARGETR100;
    volatile Uint32 GICD_IPTARGETR101;
    volatile Uint32 GICD_IPTARGETR102;
    volatile Uint32 GICD_IPTARGETR103;
    volatile Uint32 GICD_IPTARGETR104;
    volatile Uint32 GICD_IPTARGETR105;
    volatile Uint32 GICD_IPTARGETR106;
    volatile Uint32 GICD_IPTARGETR107;
    volatile Uint32 GICD_IPTARGETR108;
    volatile Uint32 GICD_IPTARGETR109;
    volatile Uint32 GICD_IPTARGETR110;
    volatile Uint32 GICD_IPTARGETR111;
    volatile Uint32 GICD_IPTARGETR112;
    volatile Uint32 GICD_IPTARGETR113;
    volatile Uint32 GICD_IPTARGETR114;
    volatile Uint32 GICD_IPTARGETR115;
    volatile Uint32 GICD_IPTARGETR116;
    volatile Uint32 GICD_IPTARGETR117;
    volatile Uint32 GICD_IPTARGETR118;
    volatile Uint32 GICD_IPTARGETR119;
    volatile Uint32 GICD_IPTARGETR120;
    volatile Uint32 GICD_IPTARGETR121;
    volatile Uint32 GICD_IPTARGETR122;
    volatile Uint32 GICD_IPTARGETR123;
    volatile Uint32 GICD_IPTARGETR124;
    volatile Uint32 GICD_IPTARGETR125;
    volatile Uint32 GICD_IPTARGETR126;
    volatile Uint32 GICD_IPTARGETR127;
#endif
    volatile Uint8 RSVD9[512];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_ICFGR[NUM_GIC400_INTC_EVENTS>>4];
#else
    volatile Uint32 GICD_ICFGR0;
    volatile Uint32 GICD_ICFGR1;
    volatile Uint32 GICD_ICFGR2;
    volatile Uint32 GICD_ICFGR3;
    volatile Uint32 GICD_ICFGR4;
    volatile Uint32 GICD_ICFGR5;
    volatile Uint32 GICD_ICFGR6;
    volatile Uint32 GICD_ICFGR7;
    volatile Uint32 GICD_ICFGR8;
    volatile Uint32 GICD_ICFGR9;
    volatile Uint32 GICD_ICFGR10;
    volatile Uint32 GICD_ICFGR11;
    volatile Uint32 GICD_ICFGR12;
    volatile Uint32 GICD_ICFGR13;
    volatile Uint32 GICD_ICFGR14;
    volatile Uint32 GICD_ICFGR15;
    volatile Uint32 GICD_ICFGR16;
    volatile Uint32 GICD_ICFGR17;
    volatile Uint32 GICD_ICFGR18;
    volatile Uint32 GICD_ICFGR19;
    volatile Uint32 GICD_ICFGR20;
    volatile Uint32 GICD_ICFGR21;
    volatile Uint32 GICD_ICFGR22;
    volatile Uint32 GICD_ICFGR23;
    volatile Uint32 GICD_ICFGR24;
    volatile Uint32 GICD_ICFGR25;
    volatile Uint32 GICD_ICFGR26;
    volatile Uint32 GICD_ICFGR27;
    volatile Uint32 GICD_ICFGR28;
    volatile Uint32 GICD_ICFGR29;
    volatile Uint32 GICD_ICFGR30;
    volatile Uint32 GICD_ICFGR31;
#endif
    volatile Uint8 RSVD10[128];
    volatile Uint32 GICD_PPISR;
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_SPISR[(NUM_GIC400_INTC_EVENTS>>5) - 1];
#else
    volatile Uint32 GICD_SPISR0;
    volatile Uint32 GICD_SPISR1;
    volatile Uint32 GICD_SPISR2;
    volatile Uint32 GICD_SPISR3;
    volatile Uint32 GICD_SPISR4;
    volatile Uint32 GICD_SPISR5;
    volatile Uint32 GICD_SPISR6;
    volatile Uint32 GICD_SPISR7;
    volatile Uint32 GICD_SPISR8;
    volatile Uint32 GICD_SPISR9;
    volatile Uint32 GICD_SPISR10;
    volatile Uint32 GICD_SPISR11;
    volatile Uint32 GICD_SPISR12;
    volatile Uint32 GICD_SPISR13;
    volatile Uint32 GICD_SPISR14;
#endif
    volatile Uint8 RSVD11[448];
    volatile Uint32 GICD_SGIR;
    volatile Uint8 RSVD12[12];
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_CPENDSGIR[MAX_GIC_SGI>>2];
#else
    volatile Uint32 GICD_CPENDSGIR0;
    volatile Uint32 GICD_CPENDSGIR1;
    volatile Uint32 GICD_CPENDSGIR2;
    volatile Uint32 GICD_CPENDSGIR3;
#endif
#ifndef ARM_INTC_REG_RAW
    volatile Uint32 GICD_SPENDSGIR[MAX_GIC_SGI>>2];
#else
    volatile Uint32 GICD_SPENDSGIR0;
    volatile Uint32 GICD_SPENDSGIR1;
    volatile Uint32 GICD_SPENDSGIR2;
    volatile Uint32 GICD_SPENDSGIR3;
#endif
    volatile Uint8 RSVD13[160];
    volatile Uint32 GICD_PIDR4;
    volatile Uint32 GICD_PIDR5;
    volatile Uint32 GICD_PIDR6;
    volatile Uint32 GICD_PIDR7;
    volatile Uint32 GICD_PIDR0;
    volatile Uint32 GICD_PIDR1;
    volatile Uint32 GICD_PIDR2;
    volatile Uint32 GICD_PIDR3;
    volatile Uint32 GICD_CIDR0;
    volatile Uint32 GICD_CIDR1;
    volatile Uint32 GICD_CIDR2;
    volatile Uint32 GICD_CIDR3;
} CSL_Cortexa15DistributerRegs;

/**************************************************************************\
* Register Overlay Structure for GICC
\**************************************************************************/
typedef struct  {
    volatile Uint32 GICC_ICR;
    volatile Uint32 GICC_PMR;
    volatile Uint32 GICC_BPR;
    volatile Uint32 GICC_IAR;
    volatile Uint32 GICC_EOIR;
    volatile Uint32 GICC_RPR;
    volatile Uint32 GICC_HPPIR;
    volatile Uint32 GICC_ABPR;
    volatile Uint32 GICC_AIAR;
    volatile Uint32 GICC_AEOIR;
    volatile Uint32 GICC_AHPPIR;
    volatile Uint8 RSVD0[164];
    volatile Uint32 GICC_APR0;
    volatile Uint8 RSVD1[12];
    volatile Uint32 GICC_NSAPR0;
    volatile Uint8 RSVD2[24];
    volatile Uint32 GICC_IIDR;
    volatile Uint8 RSVD3[3840];
    volatile Uint32 GICC_DIR;
} CSL_Cortexa15GiccRegs;

/**************************************************************************\
* Register Overlay Structure for GICH
\**************************************************************************/
typedef struct  {
    volatile Uint32 GICH_HCR;
    volatile Uint32 GICH_VTR;
    volatile Uint32 GICH_VMCR;
    volatile Uint8 RSVD0[4];
    volatile Uint32 GICH_MISR;
    volatile Uint8 RSVD1[12];
    volatile Uint32 GICH_EISR0;
    volatile Uint8 RSVD2[12];
    volatile Uint32 GICH_ELSR0;
    volatile Uint8 RSVD3[188];
    volatile Uint32 GICH_APR;
    volatile Uint8 RSVD4[12];
    volatile Uint32 GICH_LR0;
    volatile Uint32 GICH_LR1;
    volatile Uint32 GICH_LR2;
    volatile Uint32 GICH_LR3;
} CSL_Cortexa15GichRegs;

/**************************************************************************\
* Register Overlay Structure for GICV
\**************************************************************************/
typedef struct  {
    volatile Uint32 GICV_CTLR;
    volatile Uint32 GICV_PMR;
    volatile Uint32 GICV_BPR;
    volatile Uint32 GICV_IAR;
    volatile Uint32 GICV_EOIR;
    volatile Uint32 GICV_RPR;
    volatile Uint32 GICV_HPPIR;
    volatile Uint32 GICV_ABPR;
    volatile Uint32 GICV_AIAR;
    volatile Uint32 GICV_AEOIR;
    volatile Uint32 GICV_AHPPIR;
    volatile Uint8 RSVD0[164];
    volatile Uint32 GICV_APR0;
    volatile Uint8 RSVD1[40];
    volatile Uint32 GICV_IIDR;
    volatile Uint8 RSVD2[3840];
    volatile Uint32 GICV_DIR;
} CSL_Cortexa15GicvRegs;

/**************************************************************************\
* Register Overlay Structure for DBG
\**************************************************************************/
typedef struct  {
    volatile Uint32 DBGDIDR;
    volatile Uint32 DBGDSCR_INT;
    volatile Uint8 RSVD0[12];
    volatile Uint32 DBGDTRTX_INT;
    volatile Uint32 DBGWFAR;
    volatile Uint32 DBGVCR;
    volatile Uint8 RSVD1[4];
    volatile Uint32 DBGECR;
    volatile Uint8 RSVD2[88];
    volatile Uint32 DBGDTRRX_EXT;
    volatile Uint32 DBGITR;
    volatile Uint32 DBGDSCR_EXT;
    volatile Uint32 DBGDTRTX_EXT;
    volatile Uint32 DBGDRCR;
    volatile Uint32 DBGEACR;
    volatile Uint8 RSVD3[8];
    volatile Uint32 DBGPCSR_1;
    volatile Uint32 DBGCIDSR;
    volatile Uint32 DBGVIDSR;
    volatile Uint8 RSVD4[84];
    volatile Uint32 DBGBVR0;
    volatile Uint32 DBGBVR1;
    volatile Uint32 DBGBVR2;
    volatile Uint32 DBGBVR3;
    volatile Uint32 DBGBVR4;
    volatile Uint32 DBGBVR5;
    volatile Uint8 RSVD5[40];
    volatile Uint32 DBGBCR0;
    volatile Uint32 DBGBCR1;
    volatile Uint32 DBGBCR2;
    volatile Uint32 DBGBCR3;
    volatile Uint32 DBGBCR4;
    volatile Uint32 DBGBCR5;
    volatile Uint8 RSVD6[40];
    volatile Uint32 DBGWVR0;
    volatile Uint32 DBGWVR1;
    volatile Uint32 DBGWVR2;
    volatile Uint32 DBGWVR3;
    volatile Uint8 RSVD7[48];
    volatile Uint32 DBGWCR0;
    volatile Uint32 DBGWCR1;
    volatile Uint32 DBGWCR2;
    volatile Uint32 DBGWCR3;
    volatile Uint8 RSVD8[48];
    volatile Uint64 DBGDRAR;
    volatile Uint8 RSVD9[72];
    volatile Uint32 DBGBXVR0;
    volatile Uint32 DBGBXVR1;
    volatile Uint8 RSVD10[168];
    volatile Uint32 DBGOSLAR;
    volatile Uint32 DBGOSLSR;
    volatile Uint8 RSVD11[4];
    volatile Uint32 DBGOSDLR;
    volatile Uint32 DBGPRCR;
    volatile Uint32 DBGPRSR;
    volatile Uint8 RSVD12[232];
    volatile Uint64 DBGDSAR;
    volatile Uint8 RSVD13[2296];
    volatile Uint32 MIDR;
    volatile Uint32 CTR;
    volatile Uint8 RSVD14[4];
    volatile Uint32 TLBTR;
    volatile Uint8 RSVD15[4];
    volatile Uint32 MPIDR;
    volatile Uint8 RSVD16[8];
    volatile Uint32 ID_PFR0;
    volatile Uint32 ID_PFR1;
    volatile Uint32 ID_DFR0;
    volatile Uint8 RSVD17[4];
    volatile Uint32 ID_MMFR0;
    volatile Uint32 ID_MMFR1;
    volatile Uint32 ID_MMFR2;
    volatile Uint32 ID_MMFR3;
    volatile Uint32 ID_ISAR0;
    volatile Uint32 ID_ISAR1;
    volatile Uint32 ID_ISAR2;
    volatile Uint32 ID_ISAR3;
    volatile Uint32 ID_ISAR4;
    volatile Uint8 RSVD18[420];
    volatile Uint32 DBGITOCTRL;
    volatile Uint32 DBGITISR;
    volatile Uint32 DBGITCTRL;
    volatile Uint8 RSVD19[156];
    volatile Uint32 DBGCLAIMSET;
    volatile Uint32 DBGCLAIMCLR;
    volatile Uint8 RSVD20[8];
    volatile Uint32 DBGLAR;
    volatile Uint32 DBGLSR;
    volatile Uint32 DBGAUTHSTATUS;
    volatile Uint8 RSVD21[12];
    volatile Uint32 DBGDEVID0;
    volatile Uint32 DBGDEVTYPE;
    volatile Uint32 DBGPID4;
    volatile Uint32 DBGPID5;
    volatile Uint32 DBGPID6;
    volatile Uint32 DBGPID7;
    volatile Uint32 DBGPID0;
    volatile Uint32 DBGPID1;
    volatile Uint32 DBGPID2;
    volatile Uint32 DBGPID3;
    volatile Uint32 DBGCID0;
    volatile Uint32 DBGCID1;
    volatile Uint32 DBGCID2;
    volatile Uint32 DBGCID3;
} CSL_Cortexa15DbgRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    CSL_Cortexa15DistributerRegs GICD;
    CSL_Cortexa15GiccRegs GICC;
    volatile Uint8 RSVD0[4092];
    CSL_Cortexa15GichRegs GICH;
    volatile Uint8 RSVD1[7920];
    CSL_Cortexa15GicvRegs GICV;
} CSL_Cortexa15GICRegs;

typedef struct  {
    CSL_Cortexa15DbgRegs DBG;
    CSL_Cortexa15PmxRegs PMX;
} CSL_Cortexa15DebugRegs;


/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PMXEVCNTR0 */

#define CSL_CORTEXA15_PMXEVCNTR0_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR0_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR0_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR0_RESETVAL (0x00000000u)

/* PMXEVCNTR1 */

#define CSL_CORTEXA15_PMXEVCNTR1_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR1_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR1_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR1_RESETVAL (0x00000000u)

/* PMXEVCNTR2 */

#define CSL_CORTEXA15_PMXEVCNTR2_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR2_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR2_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR2_RESETVAL (0x00000000u)

/* PMXEVCNTR3 */

#define CSL_CORTEXA15_PMXEVCNTR3_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR3_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR3_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR3_RESETVAL (0x00000000u)

/* PMXEVCNTR4 */

#define CSL_CORTEXA15_PMXEVCNTR4_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR4_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR4_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR4_RESETVAL (0x00000000u)

/* PMXEVCNTR5 */

#define CSL_CORTEXA15_PMXEVCNTR5_PMNX_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMXEVCNTR5_PMNX_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVCNTR5_PMNX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVCNTR5_RESETVAL (0x00000000u)

/* PMCCNTR */

#define CSL_CORTEXA15_PMCCNTR_CCNT_MASK  (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMCCNTR_CCNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMCCNTR_CCNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCNTR_RESETVAL   (0x00000000u)

/* PMXEVTYPER0 */

#define CSL_CORTEXA15_PMXEVTYPER0_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER0_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER0_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER0_RESETVAL (0x00000000u)

/* PMXEVTYPER1 */

#define CSL_CORTEXA15_PMXEVTYPER1_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER1_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER1_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER1_RESETVAL (0x00000000u)

/* PMXEVTYPER2 */

#define CSL_CORTEXA15_PMXEVTYPER2_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER2_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER2_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER2_RESETVAL (0x00000000u)

/* PMXEVTYPER3 */

#define CSL_CORTEXA15_PMXEVTYPER3_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER3_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER3_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER3_RESETVAL (0x00000000u)

/* PMXEVTYPER4 */

#define CSL_CORTEXA15_PMXEVTYPER4_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER4_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER4_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER4_RESETVAL (0x00000000u)

/* PMXEVTYPER5 */

#define CSL_CORTEXA15_PMXEVTYPER5_EVTCOUNT_MASK (0x000000FFu)
#define CSL_CORTEXA15_PMXEVTYPER5_EVTCOUNT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMXEVTYPER5_EVTCOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMXEVTYPER5_RESETVAL (0x00000000u)

/* PMCCFILTR */

#define CSL_CORTEXA15_PMCCFILTR_PL1_MASK (0x80000000u)
#define CSL_CORTEXA15_PMCCFILTR_PL1_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_PMCCFILTR_PL1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCFILTR_U_MASK   (0x40000000u)
#define CSL_CORTEXA15_PMCCFILTR_U_SHIFT  (0x0000001Eu)
#define CSL_CORTEXA15_PMCCFILTR_U_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCFILTR_NSPL1_MASK (0x20000000u)
#define CSL_CORTEXA15_PMCCFILTR_NSPL1_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_PMCCFILTR_NSPL1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCFILTR_NSU_MASK (0x10000000u)
#define CSL_CORTEXA15_PMCCFILTR_NSU_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_PMCCFILTR_NSU_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCFILTR_NSH_MASK (0x08000000u)
#define CSL_CORTEXA15_PMCCFILTR_NSH_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_PMCCFILTR_NSH_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCCFILTR_RESETVAL (0x00000000u)

/* PMCNTENSET */

#define CSL_CORTEXA15_PMCNTENSET_C_MASK  (0x80000000u)
#define CSL_CORTEXA15_PMCNTENSET_C_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_PMCNTENSET_C_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P5_MASK (0x00000020u)
#define CSL_CORTEXA15_PMCNTENSET_P5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMCNTENSET_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P4_MASK (0x00000010u)
#define CSL_CORTEXA15_PMCNTENSET_P4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMCNTENSET_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P3_MASK (0x00000008u)
#define CSL_CORTEXA15_PMCNTENSET_P3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMCNTENSET_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P2_MASK (0x00000004u)
#define CSL_CORTEXA15_PMCNTENSET_P2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMCNTENSET_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P1_MASK (0x00000002u)
#define CSL_CORTEXA15_PMCNTENSET_P1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMCNTENSET_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_P0_MASK (0x00000001u)
#define CSL_CORTEXA15_PMCNTENSET_P0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMCNTENSET_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENSET_RESETVAL (0x00000000u)

/* PMCNTENCLR */

#define CSL_CORTEXA15_PMCNTENCLR_C_MASK  (0x80000000u)
#define CSL_CORTEXA15_PMCNTENCLR_C_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_PMCNTENCLR_C_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P5_MASK (0x00000020u)
#define CSL_CORTEXA15_PMCNTENCLR_P5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMCNTENCLR_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P4_MASK (0x00000010u)
#define CSL_CORTEXA15_PMCNTENCLR_P4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMCNTENCLR_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P3_MASK (0x00000008u)
#define CSL_CORTEXA15_PMCNTENCLR_P3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMCNTENCLR_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P2_MASK (0x00000004u)
#define CSL_CORTEXA15_PMCNTENCLR_P2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMCNTENCLR_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P1_MASK (0x00000002u)
#define CSL_CORTEXA15_PMCNTENCLR_P1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMCNTENCLR_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_P0_MASK (0x00000001u)
#define CSL_CORTEXA15_PMCNTENCLR_P0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMCNTENCLR_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCNTENCLR_RESETVAL (0x00000000u)

/* PMINTENSET */

#define CSL_CORTEXA15_PMINTENSET_C_MASK  (0x80000000u)
#define CSL_CORTEXA15_PMINTENSET_C_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_PMINTENSET_C_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P5_MASK (0x00000020u)
#define CSL_CORTEXA15_PMINTENSET_P5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMINTENSET_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P4_MASK (0x00000010u)
#define CSL_CORTEXA15_PMINTENSET_P4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMINTENSET_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P3_MASK (0x00000008u)
#define CSL_CORTEXA15_PMINTENSET_P3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMINTENSET_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P2_MASK (0x00000004u)
#define CSL_CORTEXA15_PMINTENSET_P2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMINTENSET_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P1_MASK (0x00000002u)
#define CSL_CORTEXA15_PMINTENSET_P1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMINTENSET_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_P0_MASK (0x00000001u)
#define CSL_CORTEXA15_PMINTENSET_P0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMINTENSET_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENSET_RESETVAL (0x00000000u)

/* PMINTENCLR */

#define CSL_CORTEXA15_PMINTENCLR_C_MASK  (0x80000000u)
#define CSL_CORTEXA15_PMINTENCLR_C_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_PMINTENCLR_C_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P5_MASK (0x00000020u)
#define CSL_CORTEXA15_PMINTENCLR_P5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMINTENCLR_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P4_MASK (0x00000010u)
#define CSL_CORTEXA15_PMINTENCLR_P4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMINTENCLR_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P3_MASK (0x00000008u)
#define CSL_CORTEXA15_PMINTENCLR_P3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMINTENCLR_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P2_MASK (0x00000004u)
#define CSL_CORTEXA15_PMINTENCLR_P2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMINTENCLR_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P1_MASK (0x00000002u)
#define CSL_CORTEXA15_PMINTENCLR_P1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMINTENCLR_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_P0_MASK (0x00000001u)
#define CSL_CORTEXA15_PMINTENCLR_P0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMINTENCLR_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMINTENCLR_RESETVAL (0x00000000u)

/* PMOVSR */

#define CSL_CORTEXA15_PMOVSR_C_MASK      (0x80000000u)
#define CSL_CORTEXA15_PMOVSR_C_SHIFT     (0x0000001Fu)
#define CSL_CORTEXA15_PMOVSR_C_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P5_MASK     (0x00000020u)
#define CSL_CORTEXA15_PMOVSR_P5_SHIFT    (0x00000005u)
#define CSL_CORTEXA15_PMOVSR_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P4_MASK     (0x00000010u)
#define CSL_CORTEXA15_PMOVSR_P4_SHIFT    (0x00000004u)
#define CSL_CORTEXA15_PMOVSR_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P3_MASK     (0x00000008u)
#define CSL_CORTEXA15_PMOVSR_P3_SHIFT    (0x00000003u)
#define CSL_CORTEXA15_PMOVSR_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P2_MASK     (0x00000004u)
#define CSL_CORTEXA15_PMOVSR_P2_SHIFT    (0x00000002u)
#define CSL_CORTEXA15_PMOVSR_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P1_MASK     (0x00000002u)
#define CSL_CORTEXA15_PMOVSR_P1_SHIFT    (0x00000001u)
#define CSL_CORTEXA15_PMOVSR_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_P0_MASK     (0x00000001u)
#define CSL_CORTEXA15_PMOVSR_P0_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_PMOVSR_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMOVSR_RESETVAL    (0x00000000u)

/* PMSWINC */

#define CSL_CORTEXA15_PMSWINC_P5_MASK    (0x00000020u)
#define CSL_CORTEXA15_PMSWINC_P5_SHIFT   (0x00000005u)
#define CSL_CORTEXA15_PMSWINC_P5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_P4_MASK    (0x00000010u)
#define CSL_CORTEXA15_PMSWINC_P4_SHIFT   (0x00000004u)
#define CSL_CORTEXA15_PMSWINC_P4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_P3_MASK    (0x00000008u)
#define CSL_CORTEXA15_PMSWINC_P3_SHIFT   (0x00000003u)
#define CSL_CORTEXA15_PMSWINC_P3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_P2_MASK    (0x00000004u)
#define CSL_CORTEXA15_PMSWINC_P2_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_PMSWINC_P2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_P1_MASK    (0x00000002u)
#define CSL_CORTEXA15_PMSWINC_P1_SHIFT   (0x00000001u)
#define CSL_CORTEXA15_PMSWINC_P1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_P0_MASK    (0x00000001u)
#define CSL_CORTEXA15_PMSWINC_P0_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMSWINC_P0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMSWINC_RESETVAL   (0x00000000u)

/* PMCFGR */

#define CSL_CORTEXA15_PMCFGR_UEN_MASK    (0x00080000u)
#define CSL_CORTEXA15_PMCFGR_UEN_SHIFT   (0x00000013u)
#define CSL_CORTEXA15_PMCFGR_UEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_WT_MASK     (0x00040000u)
#define CSL_CORTEXA15_PMCFGR_WT_SHIFT    (0x00000012u)
#define CSL_CORTEXA15_PMCFGR_WT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_NA_MASK     (0x00020000u)
#define CSL_CORTEXA15_PMCFGR_NA_SHIFT    (0x00000011u)
#define CSL_CORTEXA15_PMCFGR_NA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_EX_MASK     (0x00010000u)
#define CSL_CORTEXA15_PMCFGR_EX_SHIFT    (0x00000010u)
#define CSL_CORTEXA15_PMCFGR_EX_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_CCD_MASK    (0x00008000u)
#define CSL_CORTEXA15_PMCFGR_CCD_SHIFT   (0x0000000Fu)
#define CSL_CORTEXA15_PMCFGR_CCD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_CC_MASK     (0x00004000u)
#define CSL_CORTEXA15_PMCFGR_CC_SHIFT    (0x0000000Eu)
#define CSL_CORTEXA15_PMCFGR_CC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_SIZE_MASK   (0x00001800u)
#define CSL_CORTEXA15_PMCFGR_SIZE_SHIFT  (0x0000000Bu)
#define CSL_CORTEXA15_PMCFGR_SIZE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_N_MASK      (0x000000FFu)
#define CSL_CORTEXA15_PMCFGR_N_SHIFT     (0x00000000u)
#define CSL_CORTEXA15_PMCFGR_N_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_PMCFGR_RESETVAL    (0x00000000u)

/* PMCR */

#define CSL_CORTEXA15_PMCR_IMP_MASK      (0xFF000000u)
#define CSL_CORTEXA15_PMCR_IMP_SHIFT     (0x00000018u)
#define CSL_CORTEXA15_PMCR_IMP_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_PMCR_IDCODE_MASK   (0x00FF0000u)
#define CSL_CORTEXA15_PMCR_IDCODE_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_PMCR_IDCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCR_N_MASK        (0x0000F800u)
#define CSL_CORTEXA15_PMCR_N_SHIFT       (0x0000000Bu)
#define CSL_CORTEXA15_PMCR_N_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_DP_MASK       (0x00000020u)
#define CSL_CORTEXA15_PMCR_DP_SHIFT      (0x00000005u)
#define CSL_CORTEXA15_PMCR_DP_RESETVAL   (0x00000000u)

#define CSL_CORTEXA15_PMCR_X_MASK        (0x00000010u)
#define CSL_CORTEXA15_PMCR_X_SHIFT       (0x00000004u)
#define CSL_CORTEXA15_PMCR_X_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_D_MASK        (0x00000008u)
#define CSL_CORTEXA15_PMCR_D_SHIFT       (0x00000003u)
#define CSL_CORTEXA15_PMCR_D_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_C_MASK        (0x00000004u)
#define CSL_CORTEXA15_PMCR_C_SHIFT       (0x00000002u)
#define CSL_CORTEXA15_PMCR_C_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_P_MASK        (0x00000002u)
#define CSL_CORTEXA15_PMCR_P_SHIFT       (0x00000001u)
#define CSL_CORTEXA15_PMCR_P_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_E_MASK        (0x00000001u)
#define CSL_CORTEXA15_PMCR_E_SHIFT       (0x00000000u)
#define CSL_CORTEXA15_PMCR_E_RESETVAL    (0x00000000u)

#define CSL_CORTEXA15_PMCR_RESETVAL      (0x00000000u)

/* PMUSERENR */

#define CSL_CORTEXA15_PMUSERENR_EN_MASK  (0x00000001u)
#define CSL_CORTEXA15_PMUSERENR_EN_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMUSERENR_EN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMUSERENR_RESETVAL (0x00000000u)

/* PMCEID0 */

#define CSL_CORTEXA15_PMCEID0_BUSCYCLE_MASK (0x20000000u)
#define CSL_CORTEXA15_PMCEID0_BUSCYCLE_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_PMCEID0_BUSCYCLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSWRITETOTTB_MASK (0x10000000u)
#define CSL_CORTEXA15_PMCEID0_PASSWRITETOTTB_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_PMCEID0_PASSWRITETOTTB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_SPECEXC_MASK (0x08000000u)
#define CSL_CORTEXA15_PMCEID0_SPECEXC_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_PMCEID0_SPECEXC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_LOCALMEMERR_MASK (0x04000000u)
#define CSL_CORTEXA15_PMCEID0_LOCALMEMERR_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_PMCEID0_LOCALMEMERR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_BUSACCESS_MASK (0x02000000u)
#define CSL_CORTEXA15_PMCEID0_BUSACCESS_SHIFT (0x00000019u)
#define CSL_CORTEXA15_PMCEID0_BUSACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L2DCACHEWB_MASK (0x01000000u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEWB_SHIFT (0x00000018u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEWB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L2DCACHEREFILL_MASK (0x00800000u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEREFILL_SHIFT (0x00000017u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEREFILL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L2DCACHEACCESS_MASK (0x00400000u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEACCESS_SHIFT (0x00000016u)
#define CSL_CORTEXA15_PMCEID0_L2DCACHEACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1DCACHEWB_MASK (0x00200000u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEWB_SHIFT (0x00000015u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEWB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1ICACHEACCESS_MASK (0x00100000u)
#define CSL_CORTEXA15_PMCEID0_L1ICACHEACCESS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_PMCEID0_L1ICACHEACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_DATAMEMACCESS_MASK (0x00080000u)
#define CSL_CORTEXA15_PMCEID0_DATAMEMACCESS_SHIFT (0x00000013u)
#define CSL_CORTEXA15_PMCEID0_DATAMEMACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PREDBRNSPECEXC_MASK (0x00040000u)
#define CSL_CORTEXA15_PMCEID0_PREDBRNSPECEXC_SHIFT (0x00000012u)
#define CSL_CORTEXA15_PMCEID0_PREDBRNSPECEXC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_CYCLE_MASK (0x00020000u)
#define CSL_CORTEXA15_PMCEID0_CYCLE_SHIFT (0x00000011u)
#define CSL_CORTEXA15_PMCEID0_CYCLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_MISPREDBRNSPECEXC_MASK (0x00010000u)
#define CSL_CORTEXA15_PMCEID0_MISPREDBRNSPECEXC_SHIFT (0x00000010u)
#define CSL_CORTEXA15_PMCEID0_MISPREDBRNSPECEXC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSUNALGNLS_MASK (0x00008000u)
#define CSL_CORTEXA15_PMCEID0_PASSUNALGNLS_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_PMCEID0_PASSUNALGNLS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSPRCRETURN_MASK (0x00004000u)
#define CSL_CORTEXA15_PMCEID0_PASSPRCRETURN_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_PMCEID0_PASSPRCRETURN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_IMMBRN_MASK (0x00002000u)
#define CSL_CORTEXA15_PMCEID0_IMMBRN_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_PMCEID0_IMMBRN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSSWCHANGEPC_MASK (0x00001000u)
#define CSL_CORTEXA15_PMCEID0_PASSSWCHANGEPC_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_PMCEID0_PASSSWCHANGEPC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSWRITETOCONTEXTIDR_MASK (0x00000800u)
#define CSL_CORTEXA15_PMCEID0_PASSWRITETOCONTEXTIDR_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_PMCEID0_PASSWRITETOCONTEXTIDR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSEXCRETURN_MASK (0x00000400u)
#define CSL_CORTEXA15_PMCEID0_PASSEXCRETURN_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_PMCEID0_PASSEXCRETURN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_EXCTAKEN_MASK (0x00000200u)
#define CSL_CORTEXA15_PMCEID0_EXCTAKEN_SHIFT (0x00000009u)
#define CSL_CORTEXA15_PMCEID0_EXCTAKEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_INSTARCHEXC_MASK (0x00000100u)
#define CSL_CORTEXA15_PMCEID0_INSTARCHEXC_SHIFT (0x00000008u)
#define CSL_CORTEXA15_PMCEID0_INSTARCHEXC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSSTORE_MASK (0x00000080u)
#define CSL_CORTEXA15_PMCEID0_PASSSTORE_SHIFT (0x00000007u)
#define CSL_CORTEXA15_PMCEID0_PASSSTORE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSLOAD_MASK (0x00000040u)
#define CSL_CORTEXA15_PMCEID0_PASSLOAD_SHIFT (0x00000006u)
#define CSL_CORTEXA15_PMCEID0_PASSLOAD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1DATATLBREFILL_MASK (0x00000020u)
#define CSL_CORTEXA15_PMCEID0_L1DATATLBREFILL_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMCEID0_L1DATATLBREFILL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1DCACHEACCESS_MASK (0x00000010u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEACCESS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1DCACHEREFILL_MASK (0x00000008u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEREFILL_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMCEID0_L1DCACHEREFILL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1INSTTLBREFILL_MASK (0x00000004u)
#define CSL_CORTEXA15_PMCEID0_L1INSTTLBREFILL_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMCEID0_L1INSTTLBREFILL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_L1ICACHEREFILL_MASK (0x00000002u)
#define CSL_CORTEXA15_PMCEID0_L1ICACHEREFILL_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMCEID0_L1ICACHEREFILL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_PASSSWINC_MASK (0x00000001u)
#define CSL_CORTEXA15_PMCEID0_PASSSWINC_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMCEID0_PASSSWINC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCEID0_RESETVAL   (0x00000000u)

/* PMCEID1 */

#define CSL_CORTEXA15_PMCEID1_RESETVAL   (0x00000000u)

/* PMLAR */

#define CSL_CORTEXA15_PMLAR_LOCKACCESSCONTROL_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_PMLAR_LOCKACCESSCONTROL_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMLAR_LOCKACCESSCONTROL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMLAR_RESETVAL     (0x00000000u)

/* PMLSR */

#define CSL_CORTEXA15_PMLSR_NTT_MASK     (0x00000004u)
#define CSL_CORTEXA15_PMLSR_NTT_SHIFT    (0x00000002u)
#define CSL_CORTEXA15_PMLSR_NTT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMLSR_SLK_MASK     (0x00000002u)
#define CSL_CORTEXA15_PMLSR_SLK_SHIFT    (0x00000001u)
#define CSL_CORTEXA15_PMLSR_SLK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMLSR_SLI_MASK     (0x00000001u)
#define CSL_CORTEXA15_PMLSR_SLI_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_PMLSR_SLI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMLSR_RESETVAL     (0x00000000u)

/* PMAUTHSTATUS */

#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGFTIMP_MASK (0x00000080u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGFTIMP_SHIFT (0x00000007u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGFTIMP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGEN_MASK (0x00000040u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGEN_SHIFT (0x00000006u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECNINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGFTIMP_MASK (0x00000020u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGFTIMP_SHIFT (0x00000005u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGFTIMP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGEN_MASK (0x00000010u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGEN_SHIFT (0x00000004u)
#define CSL_CORTEXA15_PMAUTHSTATUS_SECINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGFTIMP_MASK (0x00000008u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGFTIMP_SHIFT (0x00000003u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGFTIMP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGEN_MASK (0x00000004u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGEN_SHIFT (0x00000002u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECNINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGFTIMP_MASK (0x00000002u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGFTIMP_SHIFT (0x00000001u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGFTIMP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGEN_MASK (0x00000001u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGEN_SHIFT (0x00000000u)
#define CSL_CORTEXA15_PMAUTHSTATUS_NSECINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMAUTHSTATUS_RESETVAL (0x00000000u)

/* PMDEVTYPE */

#define CSL_CORTEXA15_PMDEVTYPE_T_MASK   (0x000000F0u)
#define CSL_CORTEXA15_PMDEVTYPE_T_SHIFT  (0x00000004u)
#define CSL_CORTEXA15_PMDEVTYPE_T_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMDEVTYPE_C_MASK   (0x0000000Fu)
#define CSL_CORTEXA15_PMDEVTYPE_C_SHIFT  (0x00000000u)
#define CSL_CORTEXA15_PMDEVTYPE_C_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMDEVTYPE_RESETVAL (0x00000000u)

/* PMPID4 */

#define CSL_CORTEXA15_PMPID4_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID4_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID4_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID4_RESETVAL    (0x00000000u)

/* PMPID5 */

#define CSL_CORTEXA15_PMPID5_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID5_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID5_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID5_RESETVAL    (0x00000000u)

/* PMPID6 */

#define CSL_CORTEXA15_PMPID6_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID6_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID6_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID6_RESETVAL    (0x00000000u)

/* PMPID7 */

#define CSL_CORTEXA15_PMPID7_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID7_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID7_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID7_RESETVAL    (0x00000000u)

/* PMPID0 */

#define CSL_CORTEXA15_PMPID0_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID0_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID0_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID0_RESETVAL    (0x00000000u)

/* PMPID1 */

#define CSL_CORTEXA15_PMPID1_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID1_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID1_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID1_RESETVAL    (0x00000000u)

/* PMPID2 */

#define CSL_CORTEXA15_PMPID2_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID2_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID2_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID2_RESETVAL    (0x00000000u)

/* PMPID3 */

#define CSL_CORTEXA15_PMPID3_PID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMPID3_PID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMPID3_PID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMPID3_RESETVAL    (0x00000000u)

/* PMCID0 */

#define CSL_CORTEXA15_PMCID0_CID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMCID0_CID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMCID0_CID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCID0_RESETVAL    (0x00000000u)

/* PMCID1 */

#define CSL_CORTEXA15_PMCID1_CID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMCID1_CID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMCID1_CID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCID1_RESETVAL    (0x00000000u)

/* PMCID2 */

#define CSL_CORTEXA15_PMCID2_CID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMCID2_CID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMCID2_CID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCID2_RESETVAL    (0x00000000u)

/* PMCID3 */

#define CSL_CORTEXA15_PMCID3_CID_MASK    (0x000000FFu)
#define CSL_CORTEXA15_PMCID3_CID_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_PMCID3_CID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_PMCID3_RESETVAL    (0x00000000u)

/* GICD_DCR */

#define CSL_CORTEXA15_GICD_DCR_ENABLE_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_DCR_ENABLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_DCR_ENABLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_DCR_RESETVAL  (0x00000000u)

/* GICD_ICTR */

#define CSL_CORTEXA15_GICD_ICTR_ITLINESNUMBER_MASK (0x0000001Fu)
#define CSL_CORTEXA15_GICD_ICTR_ITLINESNUMBER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICTR_ITLINESNUMBER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICTR_CPUNUMBER_MASK (0x000000E0u)
#define CSL_CORTEXA15_GICD_ICTR_CPUNUMBER_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_ICTR_CPUNUMBER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICTR_SECURITYEXTN_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_ICTR_SECURITYEXTN_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICTR_SECURITYEXTN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICTR_LSPI_MASK (0x0000F800u)
#define CSL_CORTEXA15_GICD_ICTR_LSPI_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_ICTR_LSPI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICTR_RESETVAL (0x00000000u)

/* GICD_IIDR */

#define CSL_CORTEXA15_GICD_IIDR_IMPLEMENTER_MASK (0x00000FFFu)
#define CSL_CORTEXA15_GICD_IIDR_IMPLEMENTER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IIDR_IMPLEMENTER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IIDR_REVISION_MASK (0x0000F000u)
#define CSL_CORTEXA15_GICD_IIDR_REVISION_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_IIDR_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IIDR_VARIANT_MASK (0x000F0000u)
#define CSL_CORTEXA15_GICD_IIDR_VARIANT_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IIDR_VARIANT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IIDR_PRODUCDID_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IIDR_PRODUCDID_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IIDR_PRODUCDID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IIDR_RESETVAL (0x00000000u)

/* GICD_ISR0 */

#define CSL_CORTEXA15_GICD_ISR0_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR0_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR0_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR0_RESETVAL (0x00000000u)

/* GICD_ISR1 */

#define CSL_CORTEXA15_GICD_ISR1_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR1_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR1_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR1_RESETVAL (0x00000000u)

/* GICD_ISR2 */

#define CSL_CORTEXA15_GICD_ISR2_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR2_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR2_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR2_RESETVAL (0x00000000u)

/* GICD_ISR3 */

#define CSL_CORTEXA15_GICD_ISR3_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR3_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR3_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR3_RESETVAL (0x00000000u)

/* GICD_ISR4 */

#define CSL_CORTEXA15_GICD_ISR4_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR4_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR4_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR4_RESETVAL (0x00000000u)

/* GICD_ISR5 */

#define CSL_CORTEXA15_GICD_ISR5_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR5_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR5_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR5_RESETVAL (0x00000000u)

/* GICD_ISR6 */

#define CSL_CORTEXA15_GICD_ISR6_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR6_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR6_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR6_RESETVAL (0x00000000u)

/* GICD_ISR7 */

#define CSL_CORTEXA15_GICD_ISR7_SECURITYSTATUSBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISR7_SECURITYSTATUSBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISR7_SECURITYSTATUSBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISR7_RESETVAL (0x00000000u)

/* GICD_ISER0 */

#define CSL_CORTEXA15_GICD_ISER0_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER0_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER0_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER0_RESETVAL (0x00000000u)

/* GICD_ISER1 */

#define CSL_CORTEXA15_GICD_ISER1_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER1_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER1_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER1_RESETVAL (0x00000000u)

/* GICD_ISER2 */

#define CSL_CORTEXA15_GICD_ISER2_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER2_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER2_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER2_RESETVAL (0x00000000u)

/* GICD_ISER3 */

#define CSL_CORTEXA15_GICD_ISER3_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER3_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER3_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER3_RESETVAL (0x00000000u)

/* GICD_ISER4 */

#define CSL_CORTEXA15_GICD_ISER4_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER4_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER4_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER4_RESETVAL (0x00000000u)

/* GICD_ISER5 */

#define CSL_CORTEXA15_GICD_ISER5_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER5_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER5_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER5_RESETVAL (0x00000000u)

/* GICD_ISER6 */

#define CSL_CORTEXA15_GICD_ISER6_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER6_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER6_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER6_RESETVAL (0x00000000u)

/* GICD_ISER7 */

#define CSL_CORTEXA15_GICD_ISER7_SETENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISER7_SETENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISER7_SETENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISER7_RESETVAL (0x00000000u)

/* GICD_ICER0 */

#define CSL_CORTEXA15_GICD_ICER0_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER0_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER0_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER0_RESETVAL (0x00000000u)

/* GICD_ICER1 */

#define CSL_CORTEXA15_GICD_ICER1_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER1_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER1_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER1_RESETVAL (0x00000000u)

/* GICD_ICER2 */

#define CSL_CORTEXA15_GICD_ICER2_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER2_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER2_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER2_RESETVAL (0x00000000u)

/* GICD_ICER3 */

#define CSL_CORTEXA15_GICD_ICER3_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER3_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER3_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER3_RESETVAL (0x00000000u)

/* GICD_ICER4 */

#define CSL_CORTEXA15_GICD_ICER4_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER4_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER4_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER4_RESETVAL (0x00000000u)

/* GICD_ICER5 */

#define CSL_CORTEXA15_GICD_ICER5_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER5_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER5_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER5_RESETVAL (0x00000000u)

/* GICD_ICER6 */

#define CSL_CORTEXA15_GICD_ICER6_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER6_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER6_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER6_RESETVAL (0x00000000u)

/* GICD_ICER7 */

#define CSL_CORTEXA15_GICD_ICER7_CLEARENABLEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICER7_CLEARENABLEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICER7_CLEARENABLEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICER7_RESETVAL (0x00000000u)

/* GICD_ISPR0 */

#define CSL_CORTEXA15_GICD_ISPR0_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR0_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR0_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR0_RESETVAL (0x00000000u)

/* GICD_ISPR1 */

#define CSL_CORTEXA15_GICD_ISPR1_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR1_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR1_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR1_RESETVAL (0x00000000u)

/* GICD_ISPR2 */

#define CSL_CORTEXA15_GICD_ISPR2_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR2_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR2_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR2_RESETVAL (0x00000000u)

/* GICD_ISPR3 */

#define CSL_CORTEXA15_GICD_ISPR3_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR3_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR3_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR3_RESETVAL (0x00000000u)

/* GICD_ISPR4 */

#define CSL_CORTEXA15_GICD_ISPR4_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR4_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR4_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR4_RESETVAL (0x00000000u)

/* GICD_ISPR5 */

#define CSL_CORTEXA15_GICD_ISPR5_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR5_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR5_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR5_RESETVAL (0x00000000u)

/* GICD_ISPR6 */

#define CSL_CORTEXA15_GICD_ISPR6_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR6_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR6_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR6_RESETVAL (0x00000000u)

/* GICD_ISPR7 */

#define CSL_CORTEXA15_GICD_ISPR7_SETPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISPR7_SETPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISPR7_SETPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISPR7_RESETVAL (0x00000000u)

/* GICD_ICPR0 */

#define CSL_CORTEXA15_GICD_ICPR0_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR0_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR0_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR0_RESETVAL (0x00000000u)

/* GICD_ICPR1 */

#define CSL_CORTEXA15_GICD_ICPR1_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR1_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR1_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR1_RESETVAL (0x00000000u)

/* GICD_ICPR2 */

#define CSL_CORTEXA15_GICD_ICPR2_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR2_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR2_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR2_RESETVAL (0x00000000u)

/* GICD_ICPR3 */

#define CSL_CORTEXA15_GICD_ICPR3_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR3_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR3_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR3_RESETVAL (0x00000000u)

/* GICD_ICPR4 */

#define CSL_CORTEXA15_GICD_ICPR4_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR4_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR4_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR4_RESETVAL (0x00000000u)

/* GICD_ICPR5 */

#define CSL_CORTEXA15_GICD_ICPR5_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR5_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR5_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR5_RESETVAL (0x00000000u)

/* GICD_ICPR6 */

#define CSL_CORTEXA15_GICD_ICPR6_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR6_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR6_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR6_RESETVAL (0x00000000u)

/* GICD_ICPR7 */

#define CSL_CORTEXA15_GICD_ICPR7_CLEARPENDINGBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICPR7_CLEARPENDINGBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICPR7_CLEARPENDINGBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICPR7_RESETVAL (0x00000000u)

/* GICD_ISACTIVER0 */

#define CSL_CORTEXA15_GICD_ISACTIVER0_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER0_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER0_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER0_RESETVAL (0x00000000u)

/* GICD_ISACTIVER1 */

#define CSL_CORTEXA15_GICD_ISACTIVER1_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER1_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER1_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER1_RESETVAL (0x00000000u)

/* GICD_ISACTIVER2 */

#define CSL_CORTEXA15_GICD_ISACTIVER2_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER2_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER2_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER2_RESETVAL (0x00000000u)

/* GICD_ISACTIVER3 */

#define CSL_CORTEXA15_GICD_ISACTIVER3_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER3_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER3_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER3_RESETVAL (0x00000000u)

/* GICD_ISACTIVER4 */

#define CSL_CORTEXA15_GICD_ISACTIVER4_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER4_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER4_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER4_RESETVAL (0x00000000u)

/* GICD_ISACTIVER5 */

#define CSL_CORTEXA15_GICD_ISACTIVER5_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER5_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER5_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER5_RESETVAL (0x00000000u)

/* GICD_ISACTIVER6 */

#define CSL_CORTEXA15_GICD_ISACTIVER6_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER6_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER6_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER6_RESETVAL (0x00000000u)

/* GICD_ISACTIVER7 */

#define CSL_CORTEXA15_GICD_ISACTIVER7_SETACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ISACTIVER7_SETACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ISACTIVER7_SETACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ISACTIVER7_RESETVAL (0x00000000u)

/* GICD_ICACTIVER0 */

#define CSL_CORTEXA15_GICD_ICACTIVER0_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER0_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER0_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER0_RESETVAL (0x00000000u)

/* GICD_ICACTIVER1 */

#define CSL_CORTEXA15_GICD_ICACTIVER1_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER1_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER1_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER1_RESETVAL (0x00000000u)

/* GICD_ICACTIVER2 */

#define CSL_CORTEXA15_GICD_ICACTIVER2_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER2_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER2_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER2_RESETVAL (0x00000000u)

/* GICD_ICACTIVER3 */

#define CSL_CORTEXA15_GICD_ICACTIVER3_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER3_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER3_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER3_RESETVAL (0x00000000u)

/* GICD_ICACTIVER4 */

#define CSL_CORTEXA15_GICD_ICACTIVER4_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER4_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER4_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER4_RESETVAL (0x00000000u)

/* GICD_ICACTIVER5 */

#define CSL_CORTEXA15_GICD_ICACTIVER5_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER5_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER5_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER5_RESETVAL (0x00000000u)

/* GICD_ICACTIVER6 */

#define CSL_CORTEXA15_GICD_ICACTIVER6_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER6_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER6_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER6_RESETVAL (0x00000000u)

/* GICD_ICACTIVER7 */

#define CSL_CORTEXA15_GICD_ICACTIVER7_CLEARACTIVEBITS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_GICD_ICACTIVER7_CLEARACTIVEBITS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICACTIVER7_CLEARACTIVEBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICACTIVER7_RESETVAL (0x00000000u)

/* GICD_IPR0 */

#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR0_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR0_RESETVAL (0x00000000u)

/* GICD_IPR1 */

#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR1_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR1_RESETVAL (0x00000000u)

/* GICD_IPR2 */

#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR2_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR2_RESETVAL (0x00000000u)

/* GICD_IPR3 */

#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR3_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR3_RESETVAL (0x00000000u)

/* GICD_IPR4 */

#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR4_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR4_RESETVAL (0x00000000u)

/* GICD_IPR5 */

#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR5_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR5_RESETVAL (0x00000000u)

/* GICD_IPR6 */

#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR6_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR6_RESETVAL (0x00000000u)

/* GICD_IPR7 */

#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR7_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR7_RESETVAL (0x00000000u)

/* GICD_IPR8 */

#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR8_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR8_RESETVAL (0x00000000u)

/* GICD_IPR9 */

#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR9_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR9_RESETVAL (0x00000000u)

/* GICD_IPR10 */

#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR10_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR10_RESETVAL (0x00000000u)

/* GICD_IPR11 */

#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR11_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR11_RESETVAL (0x00000000u)

/* GICD_IPR12 */

#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR12_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR12_RESETVAL (0x00000000u)

/* GICD_IPR13 */

#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR13_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR13_RESETVAL (0x00000000u)

/* GICD_IPR14 */

#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR14_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR14_RESETVAL (0x00000000u)

/* GICD_IPR15 */

#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR15_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR15_RESETVAL (0x00000000u)

/* GICD_IPR16 */

#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR16_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR16_RESETVAL (0x00000000u)

/* GICD_IPR17 */

#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR17_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR17_RESETVAL (0x00000000u)

/* GICD_IPR18 */

#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR18_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR18_RESETVAL (0x00000000u)

/* GICD_IPR19 */

#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR19_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR19_RESETVAL (0x00000000u)

/* GICD_IPR20 */

#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR20_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR20_RESETVAL (0x00000000u)

/* GICD_IPR21 */

#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR21_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR21_RESETVAL (0x00000000u)

/* GICD_IPR22 */

#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR22_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR22_RESETVAL (0x00000000u)

/* GICD_IPR23 */

#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR23_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR23_RESETVAL (0x00000000u)

/* GICD_IPR24 */

#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR24_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR24_RESETVAL (0x00000000u)

/* GICD_IPR25 */

#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR25_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR25_RESETVAL (0x00000000u)

/* GICD_IPR26 */

#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR26_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR26_RESETVAL (0x00000000u)

/* GICD_IPR27 */

#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR27_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR27_RESETVAL (0x00000000u)

/* GICD_IPR28 */

#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR28_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR28_RESETVAL (0x00000000u)

/* GICD_IPR29 */

#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR29_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR29_RESETVAL (0x00000000u)

/* GICD_IPR30 */

#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR30_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR30_RESETVAL (0x00000000u)

/* GICD_IPR31 */

#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR31_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR31_RESETVAL (0x00000000u)

/* GICD_IPR32 */

#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR32_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR32_RESETVAL (0x00000000u)

/* GICD_IPR33 */

#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR33_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR33_RESETVAL (0x00000000u)

/* GICD_IPR34 */

#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR34_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR34_RESETVAL (0x00000000u)

/* GICD_IPR35 */

#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR35_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR35_RESETVAL (0x00000000u)

/* GICD_IPR36 */

#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR36_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR36_RESETVAL (0x00000000u)

/* GICD_IPR37 */

#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR37_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR37_RESETVAL (0x00000000u)

/* GICD_IPR38 */

#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR38_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR38_RESETVAL (0x00000000u)

/* GICD_IPR39 */

#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR39_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR39_RESETVAL (0x00000000u)

/* GICD_IPR40 */

#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR40_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR40_RESETVAL (0x00000000u)

/* GICD_IPR41 */

#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR41_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR41_RESETVAL (0x00000000u)

/* GICD_IPR42 */

#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR42_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR42_RESETVAL (0x00000000u)

/* GICD_IPR43 */

#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR43_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR43_RESETVAL (0x00000000u)

/* GICD_IPR44 */

#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR44_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR44_RESETVAL (0x00000000u)

/* GICD_IPR45 */

#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR45_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR45_RESETVAL (0x00000000u)

/* GICD_IPR46 */

#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR46_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR46_RESETVAL (0x00000000u)

/* GICD_IPR47 */

#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR47_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR47_RESETVAL (0x00000000u)

/* GICD_IPR48 */

#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR48_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR48_RESETVAL (0x00000000u)

/* GICD_IPR49 */

#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR49_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR49_RESETVAL (0x00000000u)

/* GICD_IPR50 */

#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR50_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR50_RESETVAL (0x00000000u)

/* GICD_IPR51 */

#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR51_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR51_RESETVAL (0x00000000u)

/* GICD_IPR52 */

#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR52_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR52_RESETVAL (0x00000000u)

/* GICD_IPR53 */

#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR53_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR53_RESETVAL (0x00000000u)

/* GICD_IPR54 */

#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR54_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR54_RESETVAL (0x00000000u)

/* GICD_IPR55 */

#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR55_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR55_RESETVAL (0x00000000u)

/* GICD_IPR56 */

#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR56_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR56_RESETVAL (0x00000000u)

/* GICD_IPR57 */

#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR57_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR57_RESETVAL (0x00000000u)

/* GICD_IPR58 */

#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR58_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR58_RESETVAL (0x00000000u)

/* GICD_IPR59 */

#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR59_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR59_RESETVAL (0x00000000u)

/* GICD_IPR60 */

#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR60_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR60_RESETVAL (0x00000000u)

/* GICD_IPR61 */

#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR61_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR61_RESETVAL (0x00000000u)

/* GICD_IPR62 */

#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR62_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR62_RESETVAL (0x00000000u)

/* GICD_IPR63 */

#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPR63_PRIORITYBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPR63_RESETVAL (0x00000000u)

/* GICD_IPTR0 */

#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR0_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR0_RESETVAL (0x00000000u)

/* GICD_IPTR1 */

#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR1_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR1_RESETVAL (0x00000000u)

/* GICD_IPTR2 */

#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR2_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR2_RESETVAL (0x00000000u)

/* GICD_IPTR3 */

#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR3_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR3_RESETVAL (0x00000000u)

/* GICD_IPTR4 */

#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR4_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR4_RESETVAL (0x00000000u)

/* GICD_IPTR5 */

#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR5_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR5_RESETVAL (0x00000000u)

/* GICD_IPTR6 */

#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR6_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR6_RESETVAL (0x00000000u)

/* GICD_IPTR7 */

#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR7_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR7_RESETVAL (0x00000000u)

/* GICD_IPTR8 */

#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR8_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR8_RESETVAL (0x00000000u)

/* GICD_IPTR9 */

#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR9_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR9_RESETVAL (0x00000000u)

/* GICD_IPTR10 */

#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR10_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR10_RESETVAL (0x00000000u)

/* GICD_IPTR11 */

#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR11_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR11_RESETVAL (0x00000000u)

/* GICD_IPTR12 */

#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR12_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR12_RESETVAL (0x00000000u)

/* GICD_IPTR13 */

#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR13_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR13_RESETVAL (0x00000000u)

/* GICD_IPTR14 */

#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR14_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR14_RESETVAL (0x00000000u)

/* GICD_IPTR15 */

#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR15_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR15_RESETVAL (0x00000000u)

/* GICD_IPTR16 */

#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR16_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR16_RESETVAL (0x00000000u)

/* GICD_IPTR17 */

#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR17_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR17_RESETVAL (0x00000000u)

/* GICD_IPTR18 */

#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR18_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR18_RESETVAL (0x00000000u)

/* GICD_IPTR19 */

#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR19_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR19_RESETVAL (0x00000000u)

/* GICD_IPTR20 */

#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR20_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR20_RESETVAL (0x00000000u)

/* GICD_IPTR21 */

#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR21_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR21_RESETVAL (0x00000000u)

/* GICD_IPTR22 */

#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR22_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR22_RESETVAL (0x00000000u)

/* GICD_IPTR23 */

#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR23_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR23_RESETVAL (0x00000000u)

/* GICD_IPTR24 */

#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR24_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR24_RESETVAL (0x00000000u)

/* GICD_IPTR25 */

#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR25_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR25_RESETVAL (0x00000000u)

/* GICD_IPTR26 */

#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR26_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR26_RESETVAL (0x00000000u)

/* GICD_IPTR27 */

#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR27_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR27_RESETVAL (0x00000000u)

/* GICD_IPTR28 */

#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR28_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR28_RESETVAL (0x00000000u)

/* GICD_IPTR29 */

#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR29_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR29_RESETVAL (0x00000000u)

/* GICD_IPTR30 */

#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR30_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR30_RESETVAL (0x00000000u)

/* GICD_IPTR31 */

#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR31_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR31_RESETVAL (0x00000000u)

/* GICD_IPTR32 */

#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR32_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR32_RESETVAL (0x00000000u)

/* GICD_IPTR33 */

#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR33_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR33_RESETVAL (0x00000000u)

/* GICD_IPTR34 */

#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR34_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR34_RESETVAL (0x00000000u)

/* GICD_IPTR35 */

#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR35_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR35_RESETVAL (0x00000000u)

/* GICD_IPTR36 */

#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR36_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR36_RESETVAL (0x00000000u)

/* GICD_IPTR37 */

#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR37_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR37_RESETVAL (0x00000000u)

/* GICD_IPTR38 */

#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR38_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR38_RESETVAL (0x00000000u)

/* GICD_IPTR39 */

#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR39_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR39_RESETVAL (0x00000000u)

/* GICD_IPTR40 */

#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR40_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR40_RESETVAL (0x00000000u)

/* GICD_IPTR41 */

#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR41_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR41_RESETVAL (0x00000000u)

/* GICD_IPTR42 */

#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR42_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR42_RESETVAL (0x00000000u)

/* GICD_IPTR43 */

#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR43_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR43_RESETVAL (0x00000000u)

/* GICD_IPTR44 */

#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR44_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR44_RESETVAL (0x00000000u)

/* GICD_IPTR45 */

#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR45_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR45_RESETVAL (0x00000000u)

/* GICD_IPTR46 */

#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR46_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR46_RESETVAL (0x00000000u)

/* GICD_IPTR47 */

#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR47_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR47_RESETVAL (0x00000000u)

/* GICD_IPTR48 */

#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR48_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR48_RESETVAL (0x00000000u)

/* GICD_IPTR49 */

#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR49_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR49_RESETVAL (0x00000000u)

/* GICD_IPTR50 */

#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR50_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR50_RESETVAL (0x00000000u)

/* GICD_IPTR51 */

#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR51_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR51_RESETVAL (0x00000000u)

/* GICD_IPTR52 */

#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR52_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR52_RESETVAL (0x00000000u)

/* GICD_IPTR53 */

#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR53_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR53_RESETVAL (0x00000000u)

/* GICD_IPTR54 */

#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR54_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR54_RESETVAL (0x00000000u)

/* GICD_IPTR55 */

#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR55_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR55_RESETVAL (0x00000000u)

/* GICD_IPTR56 */

#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR56_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR56_RESETVAL (0x00000000u)

/* GICD_IPTR57 */

#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR57_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR57_RESETVAL (0x00000000u)

/* GICD_IPTR58 */

#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR58_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR58_RESETVAL (0x00000000u)

/* GICD_IPTR59 */

#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR59_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR59_RESETVAL (0x00000000u)

/* GICD_IPTR60 */

#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR60_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR60_RESETVAL (0x00000000u)

/* GICD_IPTR61 */

#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR61_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR61_RESETVAL (0x00000000u)

/* GICD_IPTR62 */

#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR62_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR62_RESETVAL (0x00000000u)

/* GICD_IPTR63 */

#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET0_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET1_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET1_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET2_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET2_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET3_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET3_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_IPTR63_CPUTARGETSBYTEOFFSET3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_IPTR63_RESETVAL (0x00000000u)

/* GICD_ICFR0 */

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR0_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR0_RESETVAL (0x00000000u)

/* GICD_ICFR1 */

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR1_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR1_RESETVAL (0x00000000u)

/* GICD_ICFR2 */

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR2_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR2_RESETVAL (0x00000000u)

/* GICD_ICFR3 */

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR3_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR3_RESETVAL (0x00000000u)

/* GICD_ICFR4 */

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR4_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR4_RESETVAL (0x00000000u)

/* GICD_ICFR5 */

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR5_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR5_RESETVAL (0x00000000u)

/* GICD_ICFR6 */

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR6_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR6_RESETVAL (0x00000000u)

/* GICD_ICFR7 */

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR7_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR7_RESETVAL (0x00000000u)

/* GICD_ICFR8 */

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR8_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR8_RESETVAL (0x00000000u)

/* GICD_ICFR9 */

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR9_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR9_RESETVAL (0x00000000u)

/* GICD_ICFR10 */

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR10_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR10_RESETVAL (0x00000000u)

/* GICD_ICFR11 */

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR11_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR11_RESETVAL (0x00000000u)

/* GICD_ICFR12 */

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR12_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR12_RESETVAL (0x00000000u)

/* GICD_ICFR13 */

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR13_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR13_RESETVAL (0x00000000u)

/* GICD_ICFR14 */

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR14_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR14_RESETVAL (0x00000000u)

/* GICD_ICFR15 */

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER0_MASK (0x00000003u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER1_MASK (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER1_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER2_MASK (0x00000030u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER2_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER3_MASK (0x000000C0u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER3_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER4_MASK (0x00000300u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER4_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER5_MASK (0x00000C00u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER5_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER6_MASK (0x00003000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER6_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER7_MASK (0x0000C000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER7_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER8_MASK (0x00030000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER8_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER9_MASK (0x000C0000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER9_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER10_MASK (0x00300000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER10_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER11_MASK (0x00C00000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER11_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER12_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER12_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER13_MASK (0x0C000000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER13_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER14_MASK (0x30000000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER14_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER15_MASK (0xC0000000u)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER15_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_ICFR15_FIELDNUMBER15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_ICFR15_RESETVAL (0x00000000u)

/* GICD_PPISR */

#define CSL_CORTEXA15_GICD_PPISR_PPI0STATUS_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_PPISR_PPI0STATUS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_PPISR_PPI0STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI1STATUS_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_PPISR_PPI1STATUS_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_PPISR_PPI1STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI2STATUS_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_PPISR_PPI2STATUS_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_PPISR_PPI2STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI3STATUS_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_PPISR_PPI3STATUS_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_PPISR_PPI3STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI4STATUS_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_PPISR_PPI4STATUS_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_PPISR_PPI4STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI5STATUS_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_PPISR_PPI5STATUS_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_PPISR_PPI5STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_PPI6STATUS_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_PPISR_PPI6STATUS_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_PPISR_PPI6STATUS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PPISR_RESETVAL (0x00000000u)

/* GICD_SPISR0 */

#define CSL_CORTEXA15_GICD_SPISR0_IRQS0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS4_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS5_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS6_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS6_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS7_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS7_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS8_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS8_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS9_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS9_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS10_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS10_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS11_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS11_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS12_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS12_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS13_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS13_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS14_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS14_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS15_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS15_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS16_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS16_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS16_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS17_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS17_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS17_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS18_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS18_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS18_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS19_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS19_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS19_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS20_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS20_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS20_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS21_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS21_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS21_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS22_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS22_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS22_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS23_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS23_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS23_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS24_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS24_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS24_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS25_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS25_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS25_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS26_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS26_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS26_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS27_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS27_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS27_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS28_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS28_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS28_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS29_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS29_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS29_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS30_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS30_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS30_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_IRQS31_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS31_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR0_IRQS31_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR0_RESETVAL (0x00000000u)

/* GICD_SPISR1 */

#define CSL_CORTEXA15_GICD_SPISR1_IRQS32_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS32_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS32_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS33_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS33_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS33_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS34_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS34_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS34_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS35_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS35_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS35_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS36_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS36_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS36_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS37_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS37_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS37_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS38_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS38_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS38_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS39_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS39_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS39_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS40_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS40_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS40_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS41_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS41_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS41_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS42_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS42_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS42_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS43_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS43_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS43_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS44_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS44_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS44_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS45_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS45_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS45_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS46_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS46_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS46_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS47_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS47_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS47_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS48_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS48_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS48_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS49_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS49_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS49_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS50_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS50_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS50_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS51_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS51_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS51_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS52_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS52_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS52_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS53_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS53_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS53_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS54_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS54_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS54_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS55_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS55_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS55_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS56_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS56_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS56_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS57_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS57_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS57_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS58_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS58_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS58_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS59_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS59_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS59_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS60_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS60_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS60_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS61_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS61_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS61_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS62_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS62_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS62_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_IRQS63_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS63_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR1_IRQS63_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR1_RESETVAL (0x00000000u)

/* GICD_SPISR2 */

#define CSL_CORTEXA15_GICD_SPISR2_IRQS64_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS64_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS64_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS65_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS65_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS65_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS66_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS66_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS66_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS67_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS67_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS67_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS68_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS68_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS68_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS69_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS69_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS69_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS70_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS70_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS70_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS71_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS71_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS71_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS72_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS72_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS72_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS73_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS73_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS73_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS74_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS74_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS74_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS75_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS75_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS75_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS76_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS76_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS76_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS77_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS77_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS77_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS78_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS78_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS78_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS79_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS79_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS79_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS80_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS80_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS80_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS81_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS81_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS81_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS82_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS82_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS82_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS83_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS83_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS83_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS84_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS84_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS84_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS85_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS85_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS85_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS86_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS86_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS86_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS87_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS87_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS87_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS88_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS88_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS88_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS89_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS89_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS89_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS90_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS90_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS90_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS91_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS91_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS91_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS92_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS92_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS92_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS93_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS93_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS93_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS94_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS94_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS94_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_IRQS95_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS95_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR2_IRQS95_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR2_RESETVAL (0x00000000u)

/* GICD_SPISR3 */

#define CSL_CORTEXA15_GICD_SPISR3_IRQS96_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS96_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS96_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS97_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS97_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS97_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS98_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS98_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS98_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS99_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS99_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS99_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS100_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS100_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS100_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS101_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS101_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS101_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS102_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS102_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS102_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS103_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS103_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS103_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS104_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS104_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS104_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS105_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS105_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS105_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS106_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS106_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS106_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS107_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS107_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS107_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS108_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS108_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS108_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS109_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS109_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS109_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS110_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS110_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS110_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS111_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS111_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS111_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS112_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS112_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS112_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS113_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS113_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS113_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS114_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS114_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS114_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS115_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS115_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS115_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS116_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS116_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS116_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS117_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS117_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS117_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS118_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS118_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS118_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS119_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS119_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS119_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS120_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS120_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS120_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS121_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS121_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS121_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS122_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS122_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS122_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS123_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS123_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS123_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS124_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS124_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS124_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS125_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS125_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS125_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS126_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS126_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS126_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_IRQS127_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS127_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR3_IRQS127_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR3_RESETVAL (0x00000000u)

/* GICD_SPISR4 */

#define CSL_CORTEXA15_GICD_SPISR4_IRQS128_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS128_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS128_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS129_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS129_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS129_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS130_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS130_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS130_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS131_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS131_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS131_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS132_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS132_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS132_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS133_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS133_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS133_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS134_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS134_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS134_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS135_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS135_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS135_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS136_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS136_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS136_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS137_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS137_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS137_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS138_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS138_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS138_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS139_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS139_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS139_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS140_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS140_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS140_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS141_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS141_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS141_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS142_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS142_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS142_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS143_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS143_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS143_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS144_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS144_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS144_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS145_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS145_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS145_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS146_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS146_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS146_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS147_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS147_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS147_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS148_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS148_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS148_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS149_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS149_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS149_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS150_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS150_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS150_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS151_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS151_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS151_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS152_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS152_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS152_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS153_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS153_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS153_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS154_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS154_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS154_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS155_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS155_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS155_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS156_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS156_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS156_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS157_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS157_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS157_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS158_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS158_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS158_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_IRQS159_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS159_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR4_IRQS159_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR4_RESETVAL (0x00000000u)

/* GICD_SPISR5 */

#define CSL_CORTEXA15_GICD_SPISR5_IRQS160_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS160_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS160_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS161_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS161_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS161_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS162_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS162_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS162_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS163_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS163_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS163_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS164_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS164_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS164_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS165_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS165_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS165_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS166_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS166_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS166_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS167_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS167_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS167_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS168_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS168_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS168_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS169_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS169_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS169_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS170_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS170_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS170_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS171_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS171_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS171_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS172_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS172_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS172_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS173_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS173_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS173_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS174_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS174_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS174_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS175_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS175_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS175_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS176_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS176_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS176_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS177_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS177_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS177_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS178_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS178_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS178_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS179_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS179_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS179_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS180_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS180_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS180_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS181_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS181_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS181_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS182_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS182_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS182_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS183_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS183_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS183_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS184_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS184_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS184_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS185_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS185_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS185_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS186_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS186_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS186_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS187_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS187_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS187_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS188_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS188_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS188_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS189_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS189_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS189_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS190_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS190_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS190_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_IRQS191_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS191_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR5_IRQS191_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR5_RESETVAL (0x00000000u)

/* GICD_SPISR6 */

#define CSL_CORTEXA15_GICD_SPISR6_IRQS192_MASK (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS192_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS192_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS193_MASK (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS193_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS193_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS194_MASK (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS194_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS194_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS195_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS195_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS195_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS196_MASK (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS196_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS196_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS197_MASK (0x00000020u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS197_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS197_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS198_MASK (0x00000040u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS198_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS198_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS199_MASK (0x00000080u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS199_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS199_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS200_MASK (0x00000100u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS200_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS200_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS201_MASK (0x00000200u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS201_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS201_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS202_MASK (0x00000400u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS202_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS202_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS203_MASK (0x00000800u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS203_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS203_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS204_MASK (0x00001000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS204_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS204_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS205_MASK (0x00002000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS205_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS205_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS206_MASK (0x00004000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS206_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS206_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS207_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS207_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS207_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS208_MASK (0x00010000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS208_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS208_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS209_MASK (0x00020000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS209_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS209_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS210_MASK (0x00040000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS210_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS210_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS211_MASK (0x00080000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS211_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS211_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS212_MASK (0x00100000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS212_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS212_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS213_MASK (0x00200000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS213_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS213_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS214_MASK (0x00400000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS214_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS214_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS215_MASK (0x00800000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS215_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS215_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS216_MASK (0x01000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS216_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS216_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS217_MASK (0x02000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS217_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS217_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS218_MASK (0x04000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS218_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS218_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS219_MASK (0x08000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS219_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS219_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS220_MASK (0x10000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS220_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS220_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS221_MASK (0x20000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS221_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS221_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS222_MASK (0x40000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS222_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS222_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_IRQS223_MASK (0x80000000u)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS223_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICD_SPISR6_IRQS223_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPISR6_RESETVAL (0x00000000u)

/* GICD_SGIR */

#define CSL_CORTEXA15_GICD_SGIR_SGIINTID_MASK (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SGIR_SGIINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SGIR_SGIINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SGIR_SATT_MASK (0x00008000u)
#define CSL_CORTEXA15_GICD_SGIR_SATT_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICD_SGIR_SATT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SGIR_CPUTARGETLIST_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_SGIR_CPUTARGETLIST_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SGIR_CPUTARGETLIST_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SGIR_TARGETLISTFILTER_MASK (0x03000000u)
#define CSL_CORTEXA15_GICD_SGIR_TARGETLISTFILTER_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SGIR_TARGETLISTFILTER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SGIR_RESETVAL (0x00000000u)

/* GICD_CPENDSGIR0 */

#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI12_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI12_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI13_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI13_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI14_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI14_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI15_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI15_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_CPENDSGIR0_SGI15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR0_RESETVAL (0x00000000u)

/* GICD_CPENDSGIR1 */

#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI8_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI8_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI9_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI9_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI10_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI10_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI11_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI11_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_CPENDSGIR1_SGI11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR1_RESETVAL (0x00000000u)

/* GICD_CPENDSGIR2 */

#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI8_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI8_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI9_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI9_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI10_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI10_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI11_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI11_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_CPENDSGIR2_SGI11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR2_RESETVAL (0x00000000u)

/* GICD_CPENDSGIR3 */

#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI12_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI12_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI13_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI13_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI14_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI14_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI15_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI15_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_CPENDSGIR3_SGI15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CPENDSGIR3_RESETVAL (0x00000000u)

/* GICD_SPENDSGIR0 */

#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI12_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI12_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI13_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI13_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI14_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI14_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI15_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI15_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPENDSGIR0_SGI15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR0_RESETVAL (0x00000000u)

/* GICD_SPENDSGIR1 */

#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI8_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI8_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI9_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI9_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI10_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI10_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI11_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI11_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPENDSGIR1_SGI11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR1_RESETVAL (0x00000000u)

/* GICD_SPENDSGIR2 */

#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI8_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI8_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI9_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI9_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI10_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI10_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI11_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI11_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPENDSGIR2_SGI11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR2_RESETVAL (0x00000000u)

/* GICD_SPENDSGIR3 */

#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI12_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI12_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI13_MASK (0x0000FF00u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI13_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI14_MASK (0x00FF0000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI14_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI15_MASK (0xFF000000u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI15_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICD_SPENDSGIR3_SGI15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_SPENDSGIR3_RESETVAL (0x00000000u)

/* GICD_PIDR4 */

#define CSL_CORTEXA15_GICD_PIDR4_CONTINUATIONCODE_MASK (0x0000000Fu)
#define CSL_CORTEXA15_GICD_PIDR4_CONTINUATIONCODE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_PIDR4_CONTINUATIONCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR4_RESETVAL (0x00000000u)

/* GICD_PIDR5 */

#define CSL_CORTEXA15_GICD_PIDR5_RESETVAL (0x00000000u)

/* GICD_PIDR6 */

#define CSL_CORTEXA15_GICD_PIDR6_RESETVAL (0x00000000u)

/* GICD_PIDR7 */

#define CSL_CORTEXA15_GICD_PIDR7_RESETVAL (0x00000000u)

/* GICD_PIDR0 */

#define CSL_CORTEXA15_GICD_PIDR0_DEVID_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_PIDR0_DEVID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_PIDR0_DEVID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR0_RESETVAL (0x00000000u)

/* GICD_PIDR1 */

#define CSL_CORTEXA15_GICD_PIDR1_ARCHID_MASK (0x000000F0u)
#define CSL_CORTEXA15_GICD_PIDR1_ARCHID_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_PIDR1_ARCHID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR1_DEVID_MASK (0x0000000Fu)
#define CSL_CORTEXA15_GICD_PIDR1_DEVID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_PIDR1_DEVID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR1_RESETVAL (0x00000000u)

/* GICD_PIDR2 */

#define CSL_CORTEXA15_GICD_PIDR2_ARCHREV_MASK (0x000000F0u)
#define CSL_CORTEXA15_GICD_PIDR2_ARCHREV_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_PIDR2_ARCHREV_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR2_USESJEPCODE_MASK (0x00000008u)
#define CSL_CORTEXA15_GICD_PIDR2_USESJEPCODE_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICD_PIDR2_USESJEPCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR2_ARCHID_MASK (0x00000007u)
#define CSL_CORTEXA15_GICD_PIDR2_ARCHID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_PIDR2_ARCHID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR2_RESETVAL (0x00000000u)

/* GICD_PIDR3 */

#define CSL_CORTEXA15_GICD_PIDR3_REVISION_MASK (0x000000F0u)
#define CSL_CORTEXA15_GICD_PIDR3_REVISION_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICD_PIDR3_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_PIDR3_RESETVAL (0x00000000u)

/* GICD_CIDR0 */

#define CSL_CORTEXA15_GICD_CIDR0_REVISION_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CIDR0_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CIDR0_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CIDR0_RESETVAL (0x00000000u)

/* GICD_CIDR1 */

#define CSL_CORTEXA15_GICD_CIDR1_REVISION_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CIDR1_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CIDR1_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CIDR1_RESETVAL (0x00000000u)

/* GICD_CIDR2 */

#define CSL_CORTEXA15_GICD_CIDR2_REVISION_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CIDR2_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CIDR2_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CIDR2_RESETVAL (0x00000000u)

/* GICD_CIDR3 */

#define CSL_CORTEXA15_GICD_CIDR3_REVISION_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICD_CIDR3_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICD_CIDR3_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICD_CIDR3_RESETVAL (0x00000000u)

/* GICC_ICR */

#define CSL_CORTEXA15_GICC_ICR_EOIMODENS_MASK (0x00000400u)
#define CSL_CORTEXA15_GICC_ICR_EOIMODENS_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_ICR_EOIMODENS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_EOIMODES_MASK (0x00000200u)
#define CSL_CORTEXA15_GICC_ICR_EOIMODES_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICC_ICR_EOIMODES_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_CBPR_MASK (0x00000010u)
#define CSL_CORTEXA15_GICC_ICR_CBPR_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICC_ICR_CBPR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_FIQEN_MASK (0x00000008u)
#define CSL_CORTEXA15_GICC_ICR_FIQEN_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICC_ICR_FIQEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_ACKCTL_MASK (0x00000004u)
#define CSL_CORTEXA15_GICC_ICR_ACKCTL_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICC_ICR_ACKCTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_ENABLENS_MASK (0x00000002u)
#define CSL_CORTEXA15_GICC_ICR_ENABLENS_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICC_ICR_ENABLENS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_ENABLES_MASK (0x00000001u)
#define CSL_CORTEXA15_GICC_ICR_ENABLES_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_ICR_ENABLES_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ICR_RESETVAL  (0x00000000u)

/* GICC_PMR */

#define CSL_CORTEXA15_GICC_PMR_PRIORITY_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICC_PMR_PRIORITY_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_PMR_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_PMR_RESETVAL  (0x00000000u)

/* GICC_BPR */

#define CSL_CORTEXA15_GICC_BPR_BINARYPOINT_MASK (0x00000007u)
#define CSL_CORTEXA15_GICC_BPR_BINARYPOINT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_BPR_BINARYPOINT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_BPR_RESETVAL  (0x00000000u)

/* GICC_IAR */

#define CSL_CORTEXA15_GICC_IAR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_IAR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_IAR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IAR_ACKINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_IAR_ACKINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_IAR_ACKINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IAR_RESETVAL  (0x00000000u)

/* GICC_EOIR */

#define CSL_CORTEXA15_GICC_EOIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_EOIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_EOIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_EOIR_EOINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_EOIR_EOINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_EOIR_EOINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_EOIR_RESETVAL (0x00000000u)

/* GICC_RPR */

#define CSL_CORTEXA15_GICC_RPR_PRIORITY_MASK (0x000000FFu)
#define CSL_CORTEXA15_GICC_RPR_PRIORITY_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_RPR_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_RPR_RESETVAL  (0x00000000u)

/* GICC_HPPIR */

#define CSL_CORTEXA15_GICC_HPPIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_HPPIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_HPPIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_HPPIR_HPINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_HPPIR_HPINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_HPPIR_HPINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_HPPIR_RESETVAL (0x00000000u)

/* GICC_ABPR */

#define CSL_CORTEXA15_GICC_ABPR_BINARYPOINT_MASK (0x00000007u)
#define CSL_CORTEXA15_GICC_ABPR_BINARYPOINT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_ABPR_BINARYPOINT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_ABPR_RESETVAL (0x00000000u)

/* GICC_AIAR */

#define CSL_CORTEXA15_GICC_AIAR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_AIAR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_AIAR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AIAR_AACKINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_AIAR_AACKINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_AIAR_AACKINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AIAR_RESETVAL (0x00000000u)

/* GICC_AEOIR */

#define CSL_CORTEXA15_GICC_AEOIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_AEOIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_AEOIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AEOIR_AEOINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_AEOIR_AEOINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_AEOIR_AEOINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AEOIR_RESETVAL (0x00000000u)

/* GICC_AHPPIR */

#define CSL_CORTEXA15_GICC_AHPPIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_AHPPIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_AHPPIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AHPPIR_AHPINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_AHPPIR_AHPINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_AHPPIR_AHPINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_AHPPIR_RESETVAL (0x00000000u)

/* GICC_APR0 */

#define CSL_CORTEXA15_GICC_APR0_AP31_MASK (0x80000000u)
#define CSL_CORTEXA15_GICC_APR0_AP31_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICC_APR0_AP31_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP30_MASK (0x40000000u)
#define CSL_CORTEXA15_GICC_APR0_AP30_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICC_APR0_AP30_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP29_MASK (0x20000000u)
#define CSL_CORTEXA15_GICC_APR0_AP29_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICC_APR0_AP29_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP28_MASK (0x10000000u)
#define CSL_CORTEXA15_GICC_APR0_AP28_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICC_APR0_AP28_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP27_MASK (0x08000000u)
#define CSL_CORTEXA15_GICC_APR0_AP27_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICC_APR0_AP27_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP26_MASK (0x04000000u)
#define CSL_CORTEXA15_GICC_APR0_AP26_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICC_APR0_AP26_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP25_MASK (0x02000000u)
#define CSL_CORTEXA15_GICC_APR0_AP25_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICC_APR0_AP25_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP24_MASK (0x01000000u)
#define CSL_CORTEXA15_GICC_APR0_AP24_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICC_APR0_AP24_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP23_MASK (0x00800000u)
#define CSL_CORTEXA15_GICC_APR0_AP23_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICC_APR0_AP23_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP22_MASK (0x00400000u)
#define CSL_CORTEXA15_GICC_APR0_AP22_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICC_APR0_AP22_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP21_MASK (0x00200000u)
#define CSL_CORTEXA15_GICC_APR0_AP21_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICC_APR0_AP21_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP20_MASK (0x00100000u)
#define CSL_CORTEXA15_GICC_APR0_AP20_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICC_APR0_AP20_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP19_MASK (0x00080000u)
#define CSL_CORTEXA15_GICC_APR0_AP19_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICC_APR0_AP19_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP18_MASK (0x00040000u)
#define CSL_CORTEXA15_GICC_APR0_AP18_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICC_APR0_AP18_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP17_MASK (0x00020000u)
#define CSL_CORTEXA15_GICC_APR0_AP17_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICC_APR0_AP17_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP16_MASK (0x00010000u)
#define CSL_CORTEXA15_GICC_APR0_AP16_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICC_APR0_AP16_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP15_MASK (0x00008000u)
#define CSL_CORTEXA15_GICC_APR0_AP15_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICC_APR0_AP15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP14_MASK (0x00004000u)
#define CSL_CORTEXA15_GICC_APR0_AP14_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICC_APR0_AP14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP13_MASK (0x00002000u)
#define CSL_CORTEXA15_GICC_APR0_AP13_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICC_APR0_AP13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP12_MASK (0x00001000u)
#define CSL_CORTEXA15_GICC_APR0_AP12_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICC_APR0_AP12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP11_MASK (0x00000800u)
#define CSL_CORTEXA15_GICC_APR0_AP11_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICC_APR0_AP11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP10_MASK (0x00000400u)
#define CSL_CORTEXA15_GICC_APR0_AP10_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_APR0_AP10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP9_MASK (0x00000200u)
#define CSL_CORTEXA15_GICC_APR0_AP9_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICC_APR0_AP9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP8_MASK (0x00000100u)
#define CSL_CORTEXA15_GICC_APR0_AP8_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICC_APR0_AP8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP7_MASK (0x00000080u)
#define CSL_CORTEXA15_GICC_APR0_AP7_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICC_APR0_AP7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP6_MASK (0x00000040u)
#define CSL_CORTEXA15_GICC_APR0_AP6_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICC_APR0_AP6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP5_MASK (0x00000020u)
#define CSL_CORTEXA15_GICC_APR0_AP5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICC_APR0_AP5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP4_MASK (0x00000010u)
#define CSL_CORTEXA15_GICC_APR0_AP4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICC_APR0_AP4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICC_APR0_AP3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICC_APR0_AP3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICC_APR0_AP2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICC_APR0_AP2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICC_APR0_AP1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICC_APR0_AP1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_AP0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICC_APR0_AP0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_APR0_AP0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_APR0_RESETVAL (0x00000000u)

/* GICC_NSAPR0 */

#define CSL_CORTEXA15_GICC_NSAPR0_AP31_MASK (0x80000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP31_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP31_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP30_MASK (0x40000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP30_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP30_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP29_MASK (0x20000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP29_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICC_NSAPR0_AP29_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP28_MASK (0x10000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP28_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP28_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP27_MASK (0x08000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP27_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP27_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP26_MASK (0x04000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP26_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICC_NSAPR0_AP26_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP25_MASK (0x02000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP25_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP25_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP24_MASK (0x01000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP24_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP24_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP23_MASK (0x00800000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP23_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP23_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP22_MASK (0x00400000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP22_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP22_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP21_MASK (0x00200000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP21_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP21_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP20_MASK (0x00100000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP20_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP20_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP19_MASK (0x00080000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP19_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP19_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP18_MASK (0x00040000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP18_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP18_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP17_MASK (0x00020000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP17_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP17_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP16_MASK (0x00010000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP16_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP16_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP15_MASK (0x00008000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP15_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP14_MASK (0x00004000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP14_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP13_MASK (0x00002000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP13_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICC_NSAPR0_AP13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP12_MASK (0x00001000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP12_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP11_MASK (0x00000800u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP11_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICC_NSAPR0_AP11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP10_MASK (0x00000400u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP10_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_NSAPR0_AP10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP9_MASK (0x00000200u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP9_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP8_MASK (0x00000100u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP8_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP7_MASK (0x00000080u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP7_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP6_MASK (0x00000040u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP6_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP5_MASK (0x00000020u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP4_MASK (0x00000010u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_AP0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_NSAPR0_AP0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_NSAPR0_RESETVAL (0x00000000u)

/* GICC_IIDR */

#define CSL_CORTEXA15_GICC_IIDR_PRODUCTID_MASK (0xFFF00000u)
#define CSL_CORTEXA15_GICC_IIDR_PRODUCTID_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICC_IIDR_PRODUCTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IIDR_ARCHITECTUREVERSION_MASK (0x000F0000u)
#define CSL_CORTEXA15_GICC_IIDR_ARCHITECTUREVERSION_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICC_IIDR_ARCHITECTUREVERSION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IIDR_REVISION_MASK (0x0000F000u)
#define CSL_CORTEXA15_GICC_IIDR_REVISION_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICC_IIDR_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IIDR_IMPLEMENTER_MASK (0x00000FFFu)
#define CSL_CORTEXA15_GICC_IIDR_IMPLEMENTER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_IIDR_IMPLEMENTER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_IIDR_RESETVAL (0x00000000u)

/* GICC_DIR */

#define CSL_CORTEXA15_GICC_DIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICC_DIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICC_DIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_DIR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICC_DIR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICC_DIR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICC_DIR_RESETVAL  (0x00000000u)

/* GICH_HCR */

#define CSL_CORTEXA15_GICH_HCR_EOICOUNT_MASK (0xF8000000u)
#define CSL_CORTEXA15_GICH_HCR_EOICOUNT_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICH_HCR_EOICOUNT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_VDNSIE_MASK (0x00000080u)
#define CSL_CORTEXA15_GICH_HCR_VDNSIE_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICH_HCR_VDNSIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_VENSIE_MASK (0x00000040u)
#define CSL_CORTEXA15_GICH_HCR_VENSIE_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICH_HCR_VENSIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_VDSIE_MASK (0x00000020u)
#define CSL_CORTEXA15_GICH_HCR_VDSIE_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICH_HCR_VDSIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_VESIE_MASK (0x00000010u)
#define CSL_CORTEXA15_GICH_HCR_VESIE_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICH_HCR_VESIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_NPIE_MASK (0x00000008u)
#define CSL_CORTEXA15_GICH_HCR_NPIE_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_HCR_NPIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_SKIDIE_MASK (0x00000004u)
#define CSL_CORTEXA15_GICH_HCR_SKIDIE_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_HCR_SKIDIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_UIE_MASK  (0x00000002u)
#define CSL_CORTEXA15_GICH_HCR_UIE_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_HCR_UIE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_EN_MASK   (0x00000001u)
#define CSL_CORTEXA15_GICH_HCR_EN_SHIFT  (0x00000000u)
#define CSL_CORTEXA15_GICH_HCR_EN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_HCR_RESETVAL  (0x00000000u)

/* GICH_VTR */

#define CSL_CORTEXA15_GICH_VTR_PRIBITS_MASK (0xE0000000u)
#define CSL_CORTEXA15_GICH_VTR_PRIBITS_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICH_VTR_PRIBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VTR_PREBITS_MASK (0x1C000000u)
#define CSL_CORTEXA15_GICH_VTR_PREBITS_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICH_VTR_PREBITS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VTR_LISTREGS_MASK (0x0000003Fu)
#define CSL_CORTEXA15_GICH_VTR_LISTREGS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_VTR_LISTREGS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VTR_RESETVAL  (0x00000000u)

/* GICH_VMCR */

#define CSL_CORTEXA15_GICH_VMCR_VMPRIMASK_MASK (0xF8000000u)
#define CSL_CORTEXA15_GICH_VMCR_VMPRIMASK_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICH_VMCR_VMPRIMASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMBP_MASK (0x00E00000u)
#define CSL_CORTEXA15_GICH_VMCR_VMBP_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICH_VMCR_VMBP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMNSBP_MASK (0x001C0000u)
#define CSL_CORTEXA15_GICH_VMCR_VMNSBP_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICH_VMCR_VMNSBP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VEM_MASK (0x00000200u)
#define CSL_CORTEXA15_GICH_VMCR_VEM_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICH_VMCR_VEM_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMSBPR_MASK (0x00000010u)
#define CSL_CORTEXA15_GICH_VMCR_VMSBPR_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICH_VMCR_VMSBPR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMFIQEN_MASK (0x00000008u)
#define CSL_CORTEXA15_GICH_VMCR_VMFIQEN_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_VMCR_VMFIQEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMACKCTL_MASK (0x00000004u)
#define CSL_CORTEXA15_GICH_VMCR_VMACKCTL_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_VMCR_VMACKCTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMNSEN_MASK (0x00000002u)
#define CSL_CORTEXA15_GICH_VMCR_VMNSEN_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_VMCR_VMNSEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_VMSEN_MASK (0x00000001u)
#define CSL_CORTEXA15_GICH_VMCR_VMSEN_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_VMCR_VMSEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_VMCR_RESETVAL (0x00000000u)

/* GICH_MISR */

#define CSL_CORTEXA15_GICH_MISR_VDNSI_MASK (0x00000080u)
#define CSL_CORTEXA15_GICH_MISR_VDNSI_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICH_MISR_VDNSI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_VENSI_MASK (0x00000040u)
#define CSL_CORTEXA15_GICH_MISR_VENSI_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICH_MISR_VENSI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_VDSI_MASK (0x00000020u)
#define CSL_CORTEXA15_GICH_MISR_VDSI_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICH_MISR_VDSI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_VESI_MASK (0x00000010u)
#define CSL_CORTEXA15_GICH_MISR_VESI_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICH_MISR_VESI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_NPI_MASK (0x00000008u)
#define CSL_CORTEXA15_GICH_MISR_NPI_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_MISR_NPI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_SKIDI_MASK (0x00000004u)
#define CSL_CORTEXA15_GICH_MISR_SKIDI_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_MISR_SKIDI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_UI_MASK  (0x00000002u)
#define CSL_CORTEXA15_GICH_MISR_UI_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_MISR_UI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_EI_MASK  (0x00000001u)
#define CSL_CORTEXA15_GICH_MISR_EI_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_MISR_EI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_MISR_RESETVAL (0x00000000u)

/* GICH_EISR0 */

#define CSL_CORTEXA15_GICH_EISR0_LR3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICH_EISR0_LR3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_EISR0_LR3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_EISR0_LR2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICH_EISR0_LR2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_EISR0_LR2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_EISR0_LR1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICH_EISR0_LR1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_EISR0_LR1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_EISR0_LR0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICH_EISR0_LR0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_EISR0_LR0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_EISR0_RESETVAL (0x00000000u)

/* GICH_ELSR0 */

#define CSL_CORTEXA15_GICH_ELSR0_LR3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICH_ELSR0_LR3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_ELSR0_LR3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_ELSR0_LR2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICH_ELSR0_LR2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_ELSR0_LR2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_ELSR0_LR1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICH_ELSR0_LR1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_ELSR0_LR1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_ELSR0_LR0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICH_ELSR0_LR0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_ELSR0_LR0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_ELSR0_RESETVAL (0x00000000u)

/* GICH_APR */

#define CSL_CORTEXA15_GICH_APR_AP31_MASK (0x80000000u)
#define CSL_CORTEXA15_GICH_APR_AP31_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICH_APR_AP31_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP30_MASK (0x40000000u)
#define CSL_CORTEXA15_GICH_APR_AP30_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICH_APR_AP30_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP29_MASK (0x20000000u)
#define CSL_CORTEXA15_GICH_APR_AP29_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICH_APR_AP29_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP28_MASK (0x10000000u)
#define CSL_CORTEXA15_GICH_APR_AP28_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICH_APR_AP28_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP27_MASK (0x08000000u)
#define CSL_CORTEXA15_GICH_APR_AP27_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICH_APR_AP27_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP26_MASK (0x04000000u)
#define CSL_CORTEXA15_GICH_APR_AP26_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICH_APR_AP26_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP25_MASK (0x02000000u)
#define CSL_CORTEXA15_GICH_APR_AP25_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICH_APR_AP25_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP24_MASK (0x01000000u)
#define CSL_CORTEXA15_GICH_APR_AP24_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICH_APR_AP24_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP23_MASK (0x00800000u)
#define CSL_CORTEXA15_GICH_APR_AP23_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICH_APR_AP23_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP22_MASK (0x00400000u)
#define CSL_CORTEXA15_GICH_APR_AP22_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICH_APR_AP22_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP21_MASK (0x00200000u)
#define CSL_CORTEXA15_GICH_APR_AP21_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICH_APR_AP21_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP20_MASK (0x00100000u)
#define CSL_CORTEXA15_GICH_APR_AP20_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICH_APR_AP20_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP19_MASK (0x00080000u)
#define CSL_CORTEXA15_GICH_APR_AP19_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICH_APR_AP19_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP18_MASK (0x00040000u)
#define CSL_CORTEXA15_GICH_APR_AP18_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICH_APR_AP18_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP17_MASK (0x00020000u)
#define CSL_CORTEXA15_GICH_APR_AP17_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICH_APR_AP17_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP16_MASK (0x00010000u)
#define CSL_CORTEXA15_GICH_APR_AP16_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICH_APR_AP16_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP15_MASK (0x00008000u)
#define CSL_CORTEXA15_GICH_APR_AP15_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICH_APR_AP15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP14_MASK (0x00004000u)
#define CSL_CORTEXA15_GICH_APR_AP14_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICH_APR_AP14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP13_MASK (0x00002000u)
#define CSL_CORTEXA15_GICH_APR_AP13_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICH_APR_AP13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP12_MASK (0x00001000u)
#define CSL_CORTEXA15_GICH_APR_AP12_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICH_APR_AP12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP11_MASK (0x00000800u)
#define CSL_CORTEXA15_GICH_APR_AP11_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICH_APR_AP11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP10_MASK (0x00000400u)
#define CSL_CORTEXA15_GICH_APR_AP10_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICH_APR_AP10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP9_MASK  (0x00000200u)
#define CSL_CORTEXA15_GICH_APR_AP9_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICH_APR_AP9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP8_MASK  (0x00000100u)
#define CSL_CORTEXA15_GICH_APR_AP8_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICH_APR_AP8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP7_MASK  (0x00000080u)
#define CSL_CORTEXA15_GICH_APR_AP7_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICH_APR_AP7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP6_MASK  (0x00000040u)
#define CSL_CORTEXA15_GICH_APR_AP6_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICH_APR_AP6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP5_MASK  (0x00000020u)
#define CSL_CORTEXA15_GICH_APR_AP5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICH_APR_AP5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP4_MASK  (0x00000010u)
#define CSL_CORTEXA15_GICH_APR_AP4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICH_APR_AP4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP3_MASK  (0x00000008u)
#define CSL_CORTEXA15_GICH_APR_AP3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICH_APR_AP3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP2_MASK  (0x00000004u)
#define CSL_CORTEXA15_GICH_APR_AP2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICH_APR_AP2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP1_MASK  (0x00000002u)
#define CSL_CORTEXA15_GICH_APR_AP1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICH_APR_AP1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_AP0_MASK  (0x00000001u)
#define CSL_CORTEXA15_GICH_APR_AP0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_APR_AP0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_APR_RESETVAL  (0x00000000u)

/* GICH_LR0 */

#define CSL_CORTEXA15_GICH_LR0_HW_MASK   (0x80000000u)
#define CSL_CORTEXA15_GICH_LR0_HW_SHIFT  (0x0000001Fu)
#define CSL_CORTEXA15_GICH_LR0_HW_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_NS_MASK   (0x40000000u)
#define CSL_CORTEXA15_GICH_LR0_NS_SHIFT  (0x0000001Eu)
#define CSL_CORTEXA15_GICH_LR0_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_STATE_MASK (0x30000000u)
#define CSL_CORTEXA15_GICH_LR0_STATE_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICH_LR0_STATE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_PRIORITY_MASK (0x0F800000u)
#define CSL_CORTEXA15_GICH_LR0_PRIORITY_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICH_LR0_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_PHYSICALID_MASK (0x000FFC00u)
#define CSL_CORTEXA15_GICH_LR0_PHYSICALID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICH_LR0_PHYSICALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_VIRTUALID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICH_LR0_VIRTUALID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_LR0_VIRTUALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR0_RESETVAL  (0x00000000u)

/* GICH_LR1 */

#define CSL_CORTEXA15_GICH_LR1_HW_MASK   (0x80000000u)
#define CSL_CORTEXA15_GICH_LR1_HW_SHIFT  (0x0000001Fu)
#define CSL_CORTEXA15_GICH_LR1_HW_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_NS_MASK   (0x40000000u)
#define CSL_CORTEXA15_GICH_LR1_NS_SHIFT  (0x0000001Eu)
#define CSL_CORTEXA15_GICH_LR1_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_STATE_MASK (0x30000000u)
#define CSL_CORTEXA15_GICH_LR1_STATE_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICH_LR1_STATE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_PRIORITY_MASK (0x0F800000u)
#define CSL_CORTEXA15_GICH_LR1_PRIORITY_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICH_LR1_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_PHYSICALID_MASK (0x000FFC00u)
#define CSL_CORTEXA15_GICH_LR1_PHYSICALID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICH_LR1_PHYSICALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_VIRTUALID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICH_LR1_VIRTUALID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_LR1_VIRTUALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR1_RESETVAL  (0x00000000u)

/* GICH_LR2 */

#define CSL_CORTEXA15_GICH_LR2_HW_MASK   (0x80000000u)
#define CSL_CORTEXA15_GICH_LR2_HW_SHIFT  (0x0000001Fu)
#define CSL_CORTEXA15_GICH_LR2_HW_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_NS_MASK   (0x40000000u)
#define CSL_CORTEXA15_GICH_LR2_NS_SHIFT  (0x0000001Eu)
#define CSL_CORTEXA15_GICH_LR2_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_STATE_MASK (0x30000000u)
#define CSL_CORTEXA15_GICH_LR2_STATE_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICH_LR2_STATE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_PRIORITY_MASK (0x0F800000u)
#define CSL_CORTEXA15_GICH_LR2_PRIORITY_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICH_LR2_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_PHYSICALID_MASK (0x000FFC00u)
#define CSL_CORTEXA15_GICH_LR2_PHYSICALID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICH_LR2_PHYSICALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_VIRTUALID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICH_LR2_VIRTUALID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_LR2_VIRTUALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR2_RESETVAL  (0x00000000u)

/* GICH_LR3 */

#define CSL_CORTEXA15_GICH_LR3_HW_MASK   (0x80000000u)
#define CSL_CORTEXA15_GICH_LR3_HW_SHIFT  (0x0000001Fu)
#define CSL_CORTEXA15_GICH_LR3_HW_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_NS_MASK   (0x40000000u)
#define CSL_CORTEXA15_GICH_LR3_NS_SHIFT  (0x0000001Eu)
#define CSL_CORTEXA15_GICH_LR3_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_STATE_MASK (0x30000000u)
#define CSL_CORTEXA15_GICH_LR3_STATE_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICH_LR3_STATE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_PRIORITY_MASK (0x0F800000u)
#define CSL_CORTEXA15_GICH_LR3_PRIORITY_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICH_LR3_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_PHYSICALID_MASK (0x000FFC00u)
#define CSL_CORTEXA15_GICH_LR3_PHYSICALID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICH_LR3_PHYSICALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_VIRTUALID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICH_LR3_VIRTUALID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICH_LR3_VIRTUALID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICH_LR3_RESETVAL  (0x00000000u)

/* GICV_CTLR */

#define CSL_CORTEXA15_GICV_CTLR_EOIMODE_MASK (0x00000200u)
#define CSL_CORTEXA15_GICV_CTLR_EOIMODE_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICV_CTLR_EOIMODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_CBPR_MASK (0x00000010u)
#define CSL_CORTEXA15_GICV_CTLR_CBPR_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICV_CTLR_CBPR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_FIQEN_MASK (0x00000008u)
#define CSL_CORTEXA15_GICV_CTLR_FIQEN_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICV_CTLR_FIQEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_ACKCTL_MASK (0x00000004u)
#define CSL_CORTEXA15_GICV_CTLR_ACKCTL_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICV_CTLR_ACKCTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_CTLR_ENABLEGRP0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_CTLR_RESETVAL (0x00000000u)

/* GICV_PMR */

#define CSL_CORTEXA15_GICV_PMR_PRIORITY_MASK (0x000000F8u)
#define CSL_CORTEXA15_GICV_PMR_PRIORITY_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICV_PMR_PRIORITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_PMR_RESETVAL  (0x00000000u)

/* GICV_BPR */

#define CSL_CORTEXA15_GICV_BPR_BINARYPOINT_MASK (0x00000007u)
#define CSL_CORTEXA15_GICV_BPR_BINARYPOINT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_BPR_BINARYPOINT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_BPR_RESETVAL  (0x00000000u)

/* GICV_IAR */

#define CSL_CORTEXA15_GICV_IAR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_IAR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_IAR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IAR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_IAR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_IAR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IAR_RESETVAL  (0x00000000u)

/* GICV_EOIR */

#define CSL_CORTEXA15_GICV_EOIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_EOIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_EOIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_EOIR_EOIINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_EOIR_EOIINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_EOIR_EOIINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_EOIR_RESETVAL (0x00000000u)

/* GICV_RPR */

#define CSL_CORTEXA15_GICV_RPR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_RPR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_RPR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_RPR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_RPR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_RPR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_RPR_RESETVAL  (0x00000000u)

/* GICV_HPPIR */

#define CSL_CORTEXA15_GICV_HPPIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_HPPIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_HPPIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_HPPIR_PENDINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_HPPIR_PENDINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_HPPIR_PENDINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_HPPIR_RESETVAL (0x00000000u)

/* GICV_ABPR */

#define CSL_CORTEXA15_GICV_ABPR_BINARYPOINT_MASK (0x00000007u)
#define CSL_CORTEXA15_GICV_ABPR_BINARYPOINT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_ABPR_BINARYPOINT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_ABPR_RESETVAL (0x00000000u)

/* GICV_AIAR */

#define CSL_CORTEXA15_GICV_AIAR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_AIAR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_AIAR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AIAR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_AIAR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_AIAR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AIAR_RESETVAL (0x00000000u)

/* GICV_AEOIR */

#define CSL_CORTEXA15_GICV_AEOIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_AEOIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_AEOIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AEOIR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_AEOIR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_AEOIR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AEOIR_RESETVAL (0x00000000u)

/* GICV_AHPPIR */

#define CSL_CORTEXA15_GICV_AHPPIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_AHPPIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_AHPPIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AHPPIR_PENDINTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_AHPPIR_PENDINTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_AHPPIR_PENDINTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_AHPPIR_RESETVAL (0x00000000u)

/* GICV_APR0 */

#define CSL_CORTEXA15_GICV_APR0_AP31_MASK (0x80000000u)
#define CSL_CORTEXA15_GICV_APR0_AP31_SHIFT (0x0000001Fu)
#define CSL_CORTEXA15_GICV_APR0_AP31_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP30_MASK (0x40000000u)
#define CSL_CORTEXA15_GICV_APR0_AP30_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_GICV_APR0_AP30_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP29_MASK (0x20000000u)
#define CSL_CORTEXA15_GICV_APR0_AP29_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_GICV_APR0_AP29_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP28_MASK (0x10000000u)
#define CSL_CORTEXA15_GICV_APR0_AP28_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_GICV_APR0_AP28_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP27_MASK (0x08000000u)
#define CSL_CORTEXA15_GICV_APR0_AP27_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_GICV_APR0_AP27_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP26_MASK (0x04000000u)
#define CSL_CORTEXA15_GICV_APR0_AP26_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_GICV_APR0_AP26_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP25_MASK (0x02000000u)
#define CSL_CORTEXA15_GICV_APR0_AP25_SHIFT (0x00000019u)
#define CSL_CORTEXA15_GICV_APR0_AP25_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP24_MASK (0x01000000u)
#define CSL_CORTEXA15_GICV_APR0_AP24_SHIFT (0x00000018u)
#define CSL_CORTEXA15_GICV_APR0_AP24_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP23_MASK (0x00800000u)
#define CSL_CORTEXA15_GICV_APR0_AP23_SHIFT (0x00000017u)
#define CSL_CORTEXA15_GICV_APR0_AP23_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP22_MASK (0x00400000u)
#define CSL_CORTEXA15_GICV_APR0_AP22_SHIFT (0x00000016u)
#define CSL_CORTEXA15_GICV_APR0_AP22_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP21_MASK (0x00200000u)
#define CSL_CORTEXA15_GICV_APR0_AP21_SHIFT (0x00000015u)
#define CSL_CORTEXA15_GICV_APR0_AP21_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP20_MASK (0x00100000u)
#define CSL_CORTEXA15_GICV_APR0_AP20_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICV_APR0_AP20_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP19_MASK (0x00080000u)
#define CSL_CORTEXA15_GICV_APR0_AP19_SHIFT (0x00000013u)
#define CSL_CORTEXA15_GICV_APR0_AP19_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP18_MASK (0x00040000u)
#define CSL_CORTEXA15_GICV_APR0_AP18_SHIFT (0x00000012u)
#define CSL_CORTEXA15_GICV_APR0_AP18_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP17_MASK (0x00020000u)
#define CSL_CORTEXA15_GICV_APR0_AP17_SHIFT (0x00000011u)
#define CSL_CORTEXA15_GICV_APR0_AP17_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP16_MASK (0x00010000u)
#define CSL_CORTEXA15_GICV_APR0_AP16_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICV_APR0_AP16_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP15_MASK (0x00008000u)
#define CSL_CORTEXA15_GICV_APR0_AP15_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_GICV_APR0_AP15_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP14_MASK (0x00004000u)
#define CSL_CORTEXA15_GICV_APR0_AP14_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_GICV_APR0_AP14_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP13_MASK (0x00002000u)
#define CSL_CORTEXA15_GICV_APR0_AP13_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_GICV_APR0_AP13_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP12_MASK (0x00001000u)
#define CSL_CORTEXA15_GICV_APR0_AP12_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICV_APR0_AP12_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP11_MASK (0x00000800u)
#define CSL_CORTEXA15_GICV_APR0_AP11_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_GICV_APR0_AP11_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP10_MASK (0x00000400u)
#define CSL_CORTEXA15_GICV_APR0_AP10_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_APR0_AP10_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP9_MASK (0x00000200u)
#define CSL_CORTEXA15_GICV_APR0_AP9_SHIFT (0x00000009u)
#define CSL_CORTEXA15_GICV_APR0_AP9_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP8_MASK (0x00000100u)
#define CSL_CORTEXA15_GICV_APR0_AP8_SHIFT (0x00000008u)
#define CSL_CORTEXA15_GICV_APR0_AP8_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP7_MASK (0x00000080u)
#define CSL_CORTEXA15_GICV_APR0_AP7_SHIFT (0x00000007u)
#define CSL_CORTEXA15_GICV_APR0_AP7_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP6_MASK (0x00000040u)
#define CSL_CORTEXA15_GICV_APR0_AP6_SHIFT (0x00000006u)
#define CSL_CORTEXA15_GICV_APR0_AP6_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP5_MASK (0x00000020u)
#define CSL_CORTEXA15_GICV_APR0_AP5_SHIFT (0x00000005u)
#define CSL_CORTEXA15_GICV_APR0_AP5_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP4_MASK (0x00000010u)
#define CSL_CORTEXA15_GICV_APR0_AP4_SHIFT (0x00000004u)
#define CSL_CORTEXA15_GICV_APR0_AP4_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP3_MASK (0x00000008u)
#define CSL_CORTEXA15_GICV_APR0_AP3_SHIFT (0x00000003u)
#define CSL_CORTEXA15_GICV_APR0_AP3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP2_MASK (0x00000004u)
#define CSL_CORTEXA15_GICV_APR0_AP2_SHIFT (0x00000002u)
#define CSL_CORTEXA15_GICV_APR0_AP2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP1_MASK (0x00000002u)
#define CSL_CORTEXA15_GICV_APR0_AP1_SHIFT (0x00000001u)
#define CSL_CORTEXA15_GICV_APR0_AP1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_AP0_MASK (0x00000001u)
#define CSL_CORTEXA15_GICV_APR0_AP0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_APR0_AP0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_APR0_RESETVAL (0x00000000u)

/* GICV_IIDR */

#define CSL_CORTEXA15_GICV_IIDR_PRODUCTID_MASK (0xFFF00000u)
#define CSL_CORTEXA15_GICV_IIDR_PRODUCTID_SHIFT (0x00000014u)
#define CSL_CORTEXA15_GICV_IIDR_PRODUCTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IIDR_ARCHITECTUREVERSION_MASK (0x000F0000u)
#define CSL_CORTEXA15_GICV_IIDR_ARCHITECTUREVERSION_SHIFT (0x00000010u)
#define CSL_CORTEXA15_GICV_IIDR_ARCHITECTUREVERSION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IIDR_REVISION_MASK (0x0000F000u)
#define CSL_CORTEXA15_GICV_IIDR_REVISION_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_GICV_IIDR_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IIDR_IMPLEMENTER_MASK (0x00000FFFu)
#define CSL_CORTEXA15_GICV_IIDR_IMPLEMENTER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_IIDR_IMPLEMENTER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_IIDR_RESETVAL (0x00000000u)

/* GICV_DIR */

#define CSL_CORTEXA15_GICV_DIR_CPUID_MASK (0x00001C00u)
#define CSL_CORTEXA15_GICV_DIR_CPUID_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_GICV_DIR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_DIR_INTERRUPTID_MASK (0x000003FFu)
#define CSL_CORTEXA15_GICV_DIR_INTERRUPTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_GICV_DIR_INTERRUPTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_GICV_DIR_RESETVAL  (0x00000000u)

/* DBGDIDR */

#define CSL_CORTEXA15_DBGDIDR_WRPS_MASK  (0xF0000000u)
#define CSL_CORTEXA15_DBGDIDR_WRPS_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_DBGDIDR_WRPS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_BRPS_MASK  (0x0F000000u)
#define CSL_CORTEXA15_DBGDIDR_BRPS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGDIDR_BRPS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_CTX_CMPS_MASK (0x00F00000u)
#define CSL_CORTEXA15_DBGDIDR_CTX_CMPS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_DBGDIDR_CTX_CMPS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_VERSION_MASK (0x000F0000u)
#define CSL_CORTEXA15_DBGDIDR_VERSION_SHIFT (0x00000010u)
#define CSL_CORTEXA15_DBGDIDR_VERSION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_DEVID_MASK (0x00008000u)
#define CSL_CORTEXA15_DBGDIDR_DEVID_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_DBGDIDR_DEVID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_NSUHD_MASK (0x00004000u)
#define CSL_CORTEXA15_DBGDIDR_NSUHD_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_DBGDIDR_NSUHD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_PCSR_MASK  (0x00002000u)
#define CSL_CORTEXA15_DBGDIDR_PCSR_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_DBGDIDR_PCSR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_SE_MASK    (0x00001000u)
#define CSL_CORTEXA15_DBGDIDR_SE_SHIFT   (0x0000000Cu)
#define CSL_CORTEXA15_DBGDIDR_SE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_VARIANT_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGDIDR_VARIANT_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGDIDR_VARIANT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_REVISION_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGDIDR_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDIDR_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDIDR_RESETVAL   (0x00000000u)

/* DBGDSCR_INT */

#define CSL_CORTEXA15_DBGDSCR_INT_RXFULL_MASK (0x40000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_RXFULL_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_DBGDSCR_INT_RXFULL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_TXFULL_MASK (0x20000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_TXFULL_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_DBGDSCR_INT_TXFULL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_RXFULLL_MASK (0x08000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_RXFULLL_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_DBGDSCR_INT_RXFULLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_TXFULLL_MASK (0x04000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_TXFULLL_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_DBGDSCR_INT_TXFULLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_PIPEADV_MASK (0x02000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_PIPEADV_SHIFT (0x00000019u)
#define CSL_CORTEXA15_DBGDSCR_INT_PIPEADV_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_INSTRCOMPLL_MASK (0x01000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_INSTRCOMPLL_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGDSCR_INT_INSTRCOMPLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_EXTDCCMODE_MASK (0x00300000u)
#define CSL_CORTEXA15_DBGDSCR_INT_EXTDCCMODE_SHIFT (0x00000014u)
#define CSL_CORTEXA15_DBGDSCR_INT_EXTDCCMODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_ADADISCARD_MASK (0x00080000u)
#define CSL_CORTEXA15_DBGDSCR_INT_ADADISCARD_SHIFT (0x00000013u)
#define CSL_CORTEXA15_DBGDSCR_INT_ADADISCARD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_NS_MASK (0x00040000u)
#define CSL_CORTEXA15_DBGDSCR_INT_NS_SHIFT (0x00000012u)
#define CSL_CORTEXA15_DBGDSCR_INT_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_SPNIDDIS_MASK (0x00020000u)
#define CSL_CORTEXA15_DBGDSCR_INT_SPNIDDIS_SHIFT (0x00000011u)
#define CSL_CORTEXA15_DBGDSCR_INT_SPNIDDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_SPIDDIS_MASK (0x00010000u)
#define CSL_CORTEXA15_DBGDSCR_INT_SPIDDIS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_DBGDSCR_INT_SPIDDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_MDBGEN_MASK (0x00008000u)
#define CSL_CORTEXA15_DBGDSCR_INT_MDBGEN_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_DBGDSCR_INT_MDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_HDBGEN_MASK (0x00004000u)
#define CSL_CORTEXA15_DBGDSCR_INT_HDBGEN_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_DBGDSCR_INT_HDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_ITREN_MASK (0x00002000u)
#define CSL_CORTEXA15_DBGDSCR_INT_ITREN_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_DBGDSCR_INT_ITREN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_UDCCDIS_MASK (0x00001000u)
#define CSL_CORTEXA15_DBGDSCR_INT_UDCCDIS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_DBGDSCR_INT_UDCCDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_INTDIS_MASK (0x00000800u)
#define CSL_CORTEXA15_DBGDSCR_INT_INTDIS_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_DBGDSCR_INT_INTDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_DBGACK_MASK (0x00000400u)
#define CSL_CORTEXA15_DBGDSCR_INT_DBGACK_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_DBGDSCR_INT_DBGACK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_FS_MASK (0x00000200u)
#define CSL_CORTEXA15_DBGDSCR_INT_FS_SHIFT (0x00000009u)
#define CSL_CORTEXA15_DBGDSCR_INT_FS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_UNDL_MASK (0x00000100u)
#define CSL_CORTEXA15_DBGDSCR_INT_UNDL_SHIFT (0x00000008u)
#define CSL_CORTEXA15_DBGDSCR_INT_UNDL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_ADABORTL_MASK (0x00000080u)
#define CSL_CORTEXA15_DBGDSCR_INT_ADABORTL_SHIFT (0x00000007u)
#define CSL_CORTEXA15_DBGDSCR_INT_ADABORTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_SDABORTL_MASK (0x00000040u)
#define CSL_CORTEXA15_DBGDSCR_INT_SDABORTL_SHIFT (0x00000006u)
#define CSL_CORTEXA15_DBGDSCR_INT_SDABORTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_MOE_MASK (0x0000003Cu)
#define CSL_CORTEXA15_DBGDSCR_INT_MOE_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGDSCR_INT_MOE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_RESTARTED_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGDSCR_INT_RESTARTED_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGDSCR_INT_RESTARTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_HALTED_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGDSCR_INT_HALTED_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDSCR_INT_HALTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_INT_RESETVAL (0x00000000u)

/* DBGDTRTX_INT */

#define CSL_CORTEXA15_DBGDTRTX_INT_TARGETTOHOSTDATA_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGDTRTX_INT_TARGETTOHOSTDATA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDTRTX_INT_TARGETTOHOSTDATA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDTRTX_INT_RESETVAL (0x00000000u)

/* DBGDTRRX_INT */

#define CSL_CORTEXA15_DBGDTRRX_INT_HOSTTOTARGETDATA_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGDTRRX_INT_HOSTTOTARGETDATA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDTRRX_INT_HOSTTOTARGETDATA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDTRRX_INT_RESETVAL (0x00000000u)

/* DBGWFAR */

#define CSL_CORTEXA15_DBGWFAR_IAPLUSOFFSET_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGWFAR_IAPLUSOFFSET_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGWFAR_IAPLUSOFFSET_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWFAR_RESETVAL   (0x00000000u)

/* DBGVCR */

#define CSL_CORTEXA15_DBGVCR_NSF_MASK    (0x80000000u)
#define CSL_CORTEXA15_DBGVCR_NSF_SHIFT   (0x0000001Fu)
#define CSL_CORTEXA15_DBGVCR_NSF_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSI_MASK    (0x40000000u)
#define CSL_CORTEXA15_DBGVCR_NSI_SHIFT   (0x0000001Eu)
#define CSL_CORTEXA15_DBGVCR_NSI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSD_MASK    (0x10000000u)
#define CSL_CORTEXA15_DBGVCR_NSD_SHIFT   (0x0000001Cu)
#define CSL_CORTEXA15_DBGVCR_NSD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSP_MASK    (0x08000000u)
#define CSL_CORTEXA15_DBGVCR_NSP_SHIFT   (0x0000001Bu)
#define CSL_CORTEXA15_DBGVCR_NSP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSS_MASK    (0x04000000u)
#define CSL_CORTEXA15_DBGVCR_NSS_SHIFT   (0x0000001Au)
#define CSL_CORTEXA15_DBGVCR_NSS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSU_MASK    (0x02000000u)
#define CSL_CORTEXA15_DBGVCR_NSU_SHIFT   (0x00000019u)
#define CSL_CORTEXA15_DBGVCR_NSU_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHF_MASK   (0x00800000u)
#define CSL_CORTEXA15_DBGVCR_NSHF_SHIFT  (0x00000017u)
#define CSL_CORTEXA15_DBGVCR_NSHF_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHI_MASK   (0x00400000u)
#define CSL_CORTEXA15_DBGVCR_NSHI_SHIFT  (0x00000016u)
#define CSL_CORTEXA15_DBGVCR_NSHI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHE_MASK   (0x00200000u)
#define CSL_CORTEXA15_DBGVCR_NSHE_SHIFT  (0x00000015u)
#define CSL_CORTEXA15_DBGVCR_NSHE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHD_MASK   (0x00100000u)
#define CSL_CORTEXA15_DBGVCR_NSHD_SHIFT  (0x00000014u)
#define CSL_CORTEXA15_DBGVCR_NSHD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHP_MASK   (0x00080000u)
#define CSL_CORTEXA15_DBGVCR_NSHP_SHIFT  (0x00000013u)
#define CSL_CORTEXA15_DBGVCR_NSHP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHC_MASK   (0x00040000u)
#define CSL_CORTEXA15_DBGVCR_NSHC_SHIFT  (0x00000012u)
#define CSL_CORTEXA15_DBGVCR_NSHC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_NSHU_MASK   (0x00020000u)
#define CSL_CORTEXA15_DBGVCR_NSHU_SHIFT  (0x00000011u)
#define CSL_CORTEXA15_DBGVCR_NSHU_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_MF_MASK     (0x00008000u)
#define CSL_CORTEXA15_DBGVCR_MF_SHIFT    (0x0000000Fu)
#define CSL_CORTEXA15_DBGVCR_MF_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_MI_MASK     (0x00004000u)
#define CSL_CORTEXA15_DBGVCR_MI_SHIFT    (0x0000000Eu)
#define CSL_CORTEXA15_DBGVCR_MI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_MD_MASK     (0x00001000u)
#define CSL_CORTEXA15_DBGVCR_MD_SHIFT    (0x0000000Cu)
#define CSL_CORTEXA15_DBGVCR_MD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_MP_MASK     (0x00000800u)
#define CSL_CORTEXA15_DBGVCR_MP_SHIFT    (0x0000000Bu)
#define CSL_CORTEXA15_DBGVCR_MP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_MS_MASK     (0x00000400u)
#define CSL_CORTEXA15_DBGVCR_MS_SHIFT    (0x0000000Au)
#define CSL_CORTEXA15_DBGVCR_MS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SF_MASK     (0x00000080u)
#define CSL_CORTEXA15_DBGVCR_SF_SHIFT    (0x00000007u)
#define CSL_CORTEXA15_DBGVCR_SF_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SI_MASK     (0x00000040u)
#define CSL_CORTEXA15_DBGVCR_SI_SHIFT    (0x00000006u)
#define CSL_CORTEXA15_DBGVCR_SI_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SD_MASK     (0x00000010u)
#define CSL_CORTEXA15_DBGVCR_SD_SHIFT    (0x00000004u)
#define CSL_CORTEXA15_DBGVCR_SD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SP_MASK     (0x00000008u)
#define CSL_CORTEXA15_DBGVCR_SP_SHIFT    (0x00000003u)
#define CSL_CORTEXA15_DBGVCR_SP_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SS_MASK     (0x00000004u)
#define CSL_CORTEXA15_DBGVCR_SS_SHIFT    (0x00000002u)
#define CSL_CORTEXA15_DBGVCR_SS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_SU_MASK     (0x00000002u)
#define CSL_CORTEXA15_DBGVCR_SU_SHIFT    (0x00000001u)
#define CSL_CORTEXA15_DBGVCR_SU_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_R_MASK      (0x00000001u)
#define CSL_CORTEXA15_DBGVCR_R_SHIFT     (0x00000000u)
#define CSL_CORTEXA15_DBGVCR_R_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_DBGVCR_RESETVAL    (0x00000000u)

/* DBGECR */

#define CSL_CORTEXA15_DBGECR_OSUCE_MASK  (0x00000001u)
#define CSL_CORTEXA15_DBGECR_OSUCE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGECR_OSUCE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGECR_RESETVAL    (0x00000000u)

/* DBGDTRRX_EXT */

#define CSL_CORTEXA15_DBGDTRRX_EXT_HOSTTOTARGETDATA_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGDTRRX_EXT_HOSTTOTARGETDATA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDTRRX_EXT_HOSTTOTARGETDATA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDTRRX_EXT_RESETVAL (0x00000000u)

/* DBGITR */

#define CSL_CORTEXA15_DBGITR_ARMINSTR_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGITR_ARMINSTR_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGITR_ARMINSTR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITR_RESETVAL    (0x00000000u)

/* DBGPCSR_0 */

#define CSL_CORTEXA15_DBGPCSR_0_PCS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGPCSR_0_PCS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGPCSR_0_PCS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPCSR_0_IS_MASK  (0x00000003u)
#define CSL_CORTEXA15_DBGPCSR_0_IS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPCSR_0_IS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPCSR_0_RESETVAL (0x00000000u)

/* DBGDSCR_EXT */

#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULL_MASK (0x40000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULL_SHIFT (0x0000001Eu)
#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULL_MASK (0x20000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULL_SHIFT (0x0000001Du)
#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULLL_MASK (0x08000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULLL_SHIFT (0x0000001Bu)
#define CSL_CORTEXA15_DBGDSCR_EXT_RXFULLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULLL_MASK (0x04000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULLL_SHIFT (0x0000001Au)
#define CSL_CORTEXA15_DBGDSCR_EXT_TXFULLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_PIPEADV_MASK (0x02000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_PIPEADV_SHIFT (0x00000019u)
#define CSL_CORTEXA15_DBGDSCR_EXT_PIPEADV_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_INSTRCOMPLL_MASK (0x01000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_INSTRCOMPLL_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGDSCR_EXT_INSTRCOMPLL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_EXTDCCMODE_MASK (0x00300000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_EXTDCCMODE_SHIFT (0x00000014u)
#define CSL_CORTEXA15_DBGDSCR_EXT_EXTDCCMODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_ADADISCARD_MASK (0x00080000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_ADADISCARD_SHIFT (0x00000013u)
#define CSL_CORTEXA15_DBGDSCR_EXT_ADADISCARD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_NS_MASK (0x00040000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_NS_SHIFT (0x00000012u)
#define CSL_CORTEXA15_DBGDSCR_EXT_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_SPNIDDIS_MASK (0x00020000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SPNIDDIS_SHIFT (0x00000011u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SPNIDDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_SPIDDIS_MASK (0x00010000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SPIDDIS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SPIDDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_MDBGEN_MASK (0x00008000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_MDBGEN_SHIFT (0x0000000Fu)
#define CSL_CORTEXA15_DBGDSCR_EXT_MDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_HDBGEN_MASK (0x00004000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_HDBGEN_SHIFT (0x0000000Eu)
#define CSL_CORTEXA15_DBGDSCR_EXT_HDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_ITREN_MASK (0x00002000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_ITREN_SHIFT (0x0000000Du)
#define CSL_CORTEXA15_DBGDSCR_EXT_ITREN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_UDCCDIS_MASK (0x00001000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_UDCCDIS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_DBGDSCR_EXT_UDCCDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_INTDIS_MASK (0x00000800u)
#define CSL_CORTEXA15_DBGDSCR_EXT_INTDIS_SHIFT (0x0000000Bu)
#define CSL_CORTEXA15_DBGDSCR_EXT_INTDIS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_DBGACK_MASK (0x00000400u)
#define CSL_CORTEXA15_DBGDSCR_EXT_DBGACK_SHIFT (0x0000000Au)
#define CSL_CORTEXA15_DBGDSCR_EXT_DBGACK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_FS_MASK (0x00000200u)
#define CSL_CORTEXA15_DBGDSCR_EXT_FS_SHIFT (0x00000009u)
#define CSL_CORTEXA15_DBGDSCR_EXT_FS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_UNDL_MASK (0x00000100u)
#define CSL_CORTEXA15_DBGDSCR_EXT_UNDL_SHIFT (0x00000008u)
#define CSL_CORTEXA15_DBGDSCR_EXT_UNDL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_ADABORTL_MASK (0x00000080u)
#define CSL_CORTEXA15_DBGDSCR_EXT_ADABORTL_SHIFT (0x00000007u)
#define CSL_CORTEXA15_DBGDSCR_EXT_ADABORTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_SDABORTL_MASK (0x00000040u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SDABORTL_SHIFT (0x00000006u)
#define CSL_CORTEXA15_DBGDSCR_EXT_SDABORTL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_MOE_MASK (0x0000003Cu)
#define CSL_CORTEXA15_DBGDSCR_EXT_MOE_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGDSCR_EXT_MOE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_RESTARTED_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGDSCR_EXT_RESTARTED_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGDSCR_EXT_RESTARTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_HALTED_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGDSCR_EXT_HALTED_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDSCR_EXT_HALTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDSCR_EXT_RESETVAL (0x00000000u)

/* DBGDTRTX_EXT */

#define CSL_CORTEXA15_DBGDTRTX_EXT_TARGETTOHOSTDATA_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGDTRTX_EXT_TARGETTOHOSTDATA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDTRTX_EXT_TARGETTOHOSTDATA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDTRTX_EXT_RESETVAL (0x00000000u)

/* DBGDRCR */

#define CSL_CORTEXA15_DBGDRCR_CBRRQ_MASK (0x00000010u)
#define CSL_CORTEXA15_DBGDRCR_CBRRQ_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGDRCR_CBRRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDRCR_CSPA_MASK  (0x00000008u)
#define CSL_CORTEXA15_DBGDRCR_CSPA_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGDRCR_CSPA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDRCR_CSE_MASK   (0x00000004u)
#define CSL_CORTEXA15_DBGDRCR_CSE_SHIFT  (0x00000002u)
#define CSL_CORTEXA15_DBGDRCR_CSE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDRCR_RRQ_MASK   (0x00000002u)
#define CSL_CORTEXA15_DBGDRCR_RRQ_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGDRCR_RRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDRCR_HRQ_MASK   (0x00000001u)
#define CSL_CORTEXA15_DBGDRCR_HRQ_SHIFT  (0x00000000u)
#define CSL_CORTEXA15_DBGDRCR_HRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDRCR_RESETVAL   (0x00000000u)

/* DBGEACR */

#define CSL_CORTEXA15_DBGEACR_CDRS_MASK  (0x00000008u)
#define CSL_CORTEXA15_DBGEACR_CDRS_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGEACR_CDRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGEACR_DECRRQ_MASK (0x00000004u)
#define CSL_CORTEXA15_DBGEACR_DECRRQ_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGEACR_DECRRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGEACR_DPDO_MASK  (0x00000002u)
#define CSL_CORTEXA15_DBGEACR_DPDO_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGEACR_DPDO_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGEACR_DCSC_MASK  (0x00000001u)
#define CSL_CORTEXA15_DBGEACR_DCSC_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGEACR_DCSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGEACR_RESETVAL   (0x00000000u)

/* DBGPCSR_1 */

#define CSL_CORTEXA15_DBGPCSR_1_PCS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGPCSR_1_PCS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGPCSR_1_PCS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPCSR_1_IS_MASK  (0x00000003u)
#define CSL_CORTEXA15_DBGPCSR_1_IS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPCSR_1_IS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPCSR_1_RESETVAL (0x00000000u)

/* DBGCIDSR */

#define CSL_CORTEXA15_DBGCIDSR_CONTEXTIDRSAMPVAL_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGCIDSR_CONTEXTIDRSAMPVAL_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCIDSR_CONTEXTIDRSAMPVAL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCIDSR_RESETVAL  (0x00000000u)

/* DBGVIDSR */

#define CSL_CORTEXA15_DBGVIDSR_NS_MASK   (0x80000000u)
#define CSL_CORTEXA15_DBGVIDSR_NS_SHIFT  (0x0000001Fu)
#define CSL_CORTEXA15_DBGVIDSR_NS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVIDSR_H_MASK    (0x40000000u)
#define CSL_CORTEXA15_DBGVIDSR_H_SHIFT   (0x0000001Eu)
#define CSL_CORTEXA15_DBGVIDSR_H_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVIDSR_VMID_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGVIDSR_VMID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGVIDSR_VMID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGVIDSR_RESETVAL  (0x00000000u)

/* DBGBVR0 */

#define CSL_CORTEXA15_DBGBVR0_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR0_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR0_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR0_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR0_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR0_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR0_RESETVAL   (0x00000000u)

/* DBGBVR1 */

#define CSL_CORTEXA15_DBGBVR1_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR1_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR1_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR1_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR1_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR1_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR1_RESETVAL   (0x00000000u)

/* DBGBVR2 */

#define CSL_CORTEXA15_DBGBVR2_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR2_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR2_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR2_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR2_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR2_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR2_RESETVAL   (0x00000000u)

/* DBGBVR3 */

#define CSL_CORTEXA15_DBGBVR3_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR3_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR3_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR3_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR3_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR3_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR3_RESETVAL   (0x00000000u)

/* DBGBVR4 */

#define CSL_CORTEXA15_DBGBVR4_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR4_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR4_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR4_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR4_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR4_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR4_RESETVAL   (0x00000000u)

/* DBGBVR5 */

#define CSL_CORTEXA15_DBGBVR5_IA_MASK    (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGBVR5_IA_SHIFT   (0x00000002u)
#define CSL_CORTEXA15_DBGBVR5_IA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR5_CONTEXTID_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGBVR5_CONTEXTID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBVR5_CONTEXTID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBVR5_RESETVAL   (0x00000000u)

/* DBGBCR0 */

#define CSL_CORTEXA15_DBGBCR0_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR0_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR0_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR0_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR0_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR0_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR0_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR0_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR0_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR0_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR0_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR0_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR0_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR0_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR0_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR0_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR0_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR0_RESETVAL   (0x00000000u)

/* DBGBCR1 */

#define CSL_CORTEXA15_DBGBCR1_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR1_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR1_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR1_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR1_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR1_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR1_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR1_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR1_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR1_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR1_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR1_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR1_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR1_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR1_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR1_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR1_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR1_RESETVAL   (0x00000000u)

/* DBGBCR2 */

#define CSL_CORTEXA15_DBGBCR2_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR2_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR2_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR2_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR2_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR2_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR2_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR2_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR2_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR2_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR2_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR2_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR2_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR2_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR2_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR2_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR2_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR2_RESETVAL   (0x00000000u)

/* DBGBCR3 */

#define CSL_CORTEXA15_DBGBCR3_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR3_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR3_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR3_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR3_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR3_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR3_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR3_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR3_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR3_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR3_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR3_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR3_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR3_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR3_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR3_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR3_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR3_RESETVAL   (0x00000000u)

/* DBGBCR4 */

#define CSL_CORTEXA15_DBGBCR4_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR4_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR4_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR4_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR4_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR4_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR4_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR4_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR4_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR4_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR4_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR4_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR4_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR4_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR4_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR4_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR4_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR4_RESETVAL   (0x00000000u)

/* DBGBCR5 */

#define CSL_CORTEXA15_DBGBCR5_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGBCR5_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGBCR5_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_BT_MASK    (0x00F00000u)
#define CSL_CORTEXA15_DBGBCR5_BT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGBCR5_BT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGBCR5_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGBCR5_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGBCR5_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGBCR5_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGBCR5_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGBCR5_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_BAS_MASK   (0x000001E0u)
#define CSL_CORTEXA15_DBGBCR5_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGBCR5_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_PMC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGBCR5_PMC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGBCR5_PMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGBCR5_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGBCR5_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBCR5_RESETVAL   (0x00000000u)

/* DBGWVR0 */

#define CSL_CORTEXA15_DBGWVR0_DATAADDRESS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGWVR0_DATAADDRESS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGWVR0_DATAADDRESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWVR0_RESETVAL   (0x00000000u)

/* DBGWVR1 */

#define CSL_CORTEXA15_DBGWVR1_DATAADDRESS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGWVR1_DATAADDRESS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGWVR1_DATAADDRESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWVR1_RESETVAL   (0x00000000u)

/* DBGWVR2 */

#define CSL_CORTEXA15_DBGWVR2_DATAADDRESS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGWVR2_DATAADDRESS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGWVR2_DATAADDRESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWVR2_RESETVAL   (0x00000000u)

/* DBGWVR3 */

#define CSL_CORTEXA15_DBGWVR3_DATAADDRESS_MASK (0xFFFFFFFCu)
#define CSL_CORTEXA15_DBGWVR3_DATAADDRESS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGWVR3_DATAADDRESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWVR3_RESETVAL   (0x00000000u)

/* DBGWCR0 */

#define CSL_CORTEXA15_DBGWCR0_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGWCR0_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGWCR0_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_WT_MASK    (0x00100000u)
#define CSL_CORTEXA15_DBGWCR0_WT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGWCR0_WT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGWCR0_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGWCR0_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGWCR0_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGWCR0_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGWCR0_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGWCR0_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_BAS_MASK   (0x00001FE0u)
#define CSL_CORTEXA15_DBGWCR0_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGWCR0_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_LSC_MASK   (0x00000018u)
#define CSL_CORTEXA15_DBGWCR0_LSC_SHIFT  (0x00000003u)
#define CSL_CORTEXA15_DBGWCR0_LSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_PAC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGWCR0_PAC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGWCR0_PAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGWCR0_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGWCR0_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR0_RESETVAL   (0x00000000u)

/* DBGWCR1 */

#define CSL_CORTEXA15_DBGWCR1_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGWCR1_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGWCR1_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_WT_MASK    (0x00100000u)
#define CSL_CORTEXA15_DBGWCR1_WT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGWCR1_WT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGWCR1_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGWCR1_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGWCR1_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGWCR1_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGWCR1_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGWCR1_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_BAS_MASK   (0x00001FE0u)
#define CSL_CORTEXA15_DBGWCR1_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGWCR1_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_LSC_MASK   (0x00000018u)
#define CSL_CORTEXA15_DBGWCR1_LSC_SHIFT  (0x00000003u)
#define CSL_CORTEXA15_DBGWCR1_LSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_PAC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGWCR1_PAC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGWCR1_PAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGWCR1_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGWCR1_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR1_RESETVAL   (0x00000000u)

/* DBGWCR2 */

#define CSL_CORTEXA15_DBGWCR2_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGWCR2_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGWCR2_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_WT_MASK    (0x00100000u)
#define CSL_CORTEXA15_DBGWCR2_WT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGWCR2_WT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGWCR2_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGWCR2_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGWCR2_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGWCR2_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGWCR2_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGWCR2_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_BAS_MASK   (0x00001FE0u)
#define CSL_CORTEXA15_DBGWCR2_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGWCR2_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_LSC_MASK   (0x00000018u)
#define CSL_CORTEXA15_DBGWCR2_LSC_SHIFT  (0x00000003u)
#define CSL_CORTEXA15_DBGWCR2_LSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_PAC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGWCR2_PAC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGWCR2_PAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGWCR2_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGWCR2_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR2_RESETVAL   (0x00000000u)

/* DBGWCR3 */

#define CSL_CORTEXA15_DBGWCR3_MASK_MASK  (0x1F000000u)
#define CSL_CORTEXA15_DBGWCR3_MASK_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGWCR3_MASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_WT_MASK    (0x00100000u)
#define CSL_CORTEXA15_DBGWCR3_WT_SHIFT   (0x00000014u)
#define CSL_CORTEXA15_DBGWCR3_WT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_LBN_MASK   (0x000F0000u)
#define CSL_CORTEXA15_DBGWCR3_LBN_SHIFT  (0x00000010u)
#define CSL_CORTEXA15_DBGWCR3_LBN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_SSC_MASK   (0x0000C000u)
#define CSL_CORTEXA15_DBGWCR3_SSC_SHIFT  (0x0000000Eu)
#define CSL_CORTEXA15_DBGWCR3_SSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_HMC_MASK   (0x00002000u)
#define CSL_CORTEXA15_DBGWCR3_HMC_SHIFT  (0x0000000Du)
#define CSL_CORTEXA15_DBGWCR3_HMC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_BAS_MASK   (0x00001FE0u)
#define CSL_CORTEXA15_DBGWCR3_BAS_SHIFT  (0x00000005u)
#define CSL_CORTEXA15_DBGWCR3_BAS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_LSC_MASK   (0x00000018u)
#define CSL_CORTEXA15_DBGWCR3_LSC_SHIFT  (0x00000003u)
#define CSL_CORTEXA15_DBGWCR3_LSC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_PAC_MASK   (0x00000006u)
#define CSL_CORTEXA15_DBGWCR3_PAC_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGWCR3_PAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_E_MASK     (0x00000001u)
#define CSL_CORTEXA15_DBGWCR3_E_SHIFT    (0x00000000u)
#define CSL_CORTEXA15_DBGWCR3_E_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGWCR3_RESETVAL   (0x00000000u)

/* DBGDRAR */

#define CSL_CORTEXA15_DBGDRAR_ROMADDR_MASK (0x000000FFFFFFF000u)
#define CSL_CORTEXA15_DBGDRAR_ROMADDR_SHIFT (0x000000000000000Cu)
#define CSL_CORTEXA15_DBGDRAR_ROMADDR_RESETVAL (0x0000000000000000u)

#define CSL_CORTEXA15_DBGDRAR_VALID_MASK (0x0000000000000003u)
#define CSL_CORTEXA15_DBGDRAR_VALID_SHIFT (0x0000000000000000u)
#define CSL_CORTEXA15_DBGDRAR_VALID_RESETVAL (0x0000000000000000u)

#define CSL_CORTEXA15_DBGDRAR_RESETVAL   (0x0000000000000000u)

/* DBGBXVR0 */

#define CSL_CORTEXA15_DBGBXVR0_VMID_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGBXVR0_VMID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBXVR0_VMID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBXVR0_RESETVAL  (0x00000000u)

/* DBGBXVR1 */

#define CSL_CORTEXA15_DBGBXVR1_VMID_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGBXVR1_VMID_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGBXVR1_VMID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGBXVR1_RESETVAL  (0x00000000u)

/* DBGOSLAR */

#define CSL_CORTEXA15_DBGOSLAR_OSLOCKACCESS_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGOSLAR_OSLOCKACCESS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGOSLAR_OSLOCKACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSLAR_RESETVAL  (0x00000000u)

/* DBGOSLSR */

#define CSL_CORTEXA15_DBGOSLSR_LM1_MASK  (0x00000008u)
#define CSL_CORTEXA15_DBGOSLSR_LM1_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGOSLSR_LM1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSLSR_NTT_MASK  (0x00000004u)
#define CSL_CORTEXA15_DBGOSLSR_NTT_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGOSLSR_NTT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSLSR_LK_MASK   (0x00000002u)
#define CSL_CORTEXA15_DBGOSLSR_LK_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGOSLSR_LK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSLSR_LM0_MASK  (0x00000001u)
#define CSL_CORTEXA15_DBGOSLSR_LM0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGOSLSR_LM0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSLSR_RESETVAL  (0x00000000u)

/* DBGOSDLR */

#define CSL_CORTEXA15_DBGOSDLR_DLK_MASK  (0x00000001u)
#define CSL_CORTEXA15_DBGOSDLR_DLK_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGOSDLR_DLK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGOSDLR_RESETVAL  (0x00000000u)

/* DBGPRCR */

#define CSL_CORTEXA15_DBGPRCR_COREPURQ_MASK (0x00000008u)
#define CSL_CORTEXA15_DBGPRCR_COREPURQ_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGPRCR_COREPURQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRCR_HCWR_MASK  (0x00000004u)
#define CSL_CORTEXA15_DBGPRCR_HCWR_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGPRCR_HCWR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRCR_CWRR_MASK  (0x00000002u)
#define CSL_CORTEXA15_DBGPRCR_CWRR_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGPRCR_CWRR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRCR_CORENPDRQ_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGPRCR_CORENPDRQ_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPRCR_CORENPDRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRCR_RESETVAL   (0x00000000u)

/* DBGPRSR */

#define CSL_CORTEXA15_DBGPRSR_DLK_MASK   (0x00000040u)
#define CSL_CORTEXA15_DBGPRSR_DLK_SHIFT  (0x00000006u)
#define CSL_CORTEXA15_DBGPRSR_DLK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_OSLK_MASK  (0x00000020u)
#define CSL_CORTEXA15_DBGPRSR_OSLK_SHIFT (0x00000005u)
#define CSL_CORTEXA15_DBGPRSR_OSLK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_HALTED_MASK (0x00000010u)
#define CSL_CORTEXA15_DBGPRSR_HALTED_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGPRSR_HALTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_SR_MASK    (0x00000008u)
#define CSL_CORTEXA15_DBGPRSR_SR_SHIFT   (0x00000003u)
#define CSL_CORTEXA15_DBGPRSR_SR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_R_MASK     (0x00000004u)
#define CSL_CORTEXA15_DBGPRSR_R_SHIFT    (0x00000002u)
#define CSL_CORTEXA15_DBGPRSR_R_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_SPD_MASK   (0x00000002u)
#define CSL_CORTEXA15_DBGPRSR_SPD_SHIFT  (0x00000001u)
#define CSL_CORTEXA15_DBGPRSR_SPD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_PU_MASK    (0x00000001u)
#define CSL_CORTEXA15_DBGPRSR_PU_SHIFT   (0x00000000u)
#define CSL_CORTEXA15_DBGPRSR_PU_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPRSR_RESETVAL   (0x00000000u)

/* DBGDSAR */

#define CSL_CORTEXA15_DBGDSAR_SGN_MASK   (0xFFFFFF0000000000u)
#define CSL_CORTEXA15_DBGDSAR_SGN_SHIFT  (0x0000000000000028u)
#define CSL_CORTEXA15_DBGDSAR_SGN_RESETVAL (0x0000000000000000u)

#define CSL_CORTEXA15_DBGDSAR_SELFOFFSET_MASK (0x000000FFFFFFF000u)
#define CSL_CORTEXA15_DBGDSAR_SELFOFFSET_SHIFT (0x000000000000000Cu)
#define CSL_CORTEXA15_DBGDSAR_SELFOFFSET_RESETVAL (0x0000000000000000u)

#define CSL_CORTEXA15_DBGDSAR_VALID_MASK (0x0000000000000003u)
#define CSL_CORTEXA15_DBGDSAR_VALID_SHIFT (0x0000000000000000u)
#define CSL_CORTEXA15_DBGDSAR_VALID_RESETVAL (0x0000000000000000u)

#define CSL_CORTEXA15_DBGDSAR_RESETVAL   (0x0000000000000000u)

/* MIDR */

#define CSL_CORTEXA15_MIDR_IMPLEMENTER_MASK (0xFF000000u)
#define CSL_CORTEXA15_MIDR_IMPLEMENTER_SHIFT (0x00000018u)
#define CSL_CORTEXA15_MIDR_IMPLEMENTER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MIDR_VARIANT_MASK  (0x00F00000u)
#define CSL_CORTEXA15_MIDR_VARIANT_SHIFT (0x00000014u)
#define CSL_CORTEXA15_MIDR_VARIANT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MIDR_ARCHITECTURE_MASK (0x000F0000u)
#define CSL_CORTEXA15_MIDR_ARCHITECTURE_SHIFT (0x00000010u)
#define CSL_CORTEXA15_MIDR_ARCHITECTURE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MIDR_PRIMARYPARTNUMBER_MASK (0x0000FFF0u)
#define CSL_CORTEXA15_MIDR_PRIMARYPARTNUMBER_SHIFT (0x00000004u)
#define CSL_CORTEXA15_MIDR_PRIMARYPARTNUMBER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MIDR_REVISION_MASK (0x0000000Fu)
#define CSL_CORTEXA15_MIDR_REVISION_SHIFT (0x00000000u)
#define CSL_CORTEXA15_MIDR_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MIDR_RESETVAL      (0x00000000u)

/* CTR */

#define CSL_CORTEXA15_CTR_FORMAT_MASK    (0xE0000000u)
#define CSL_CORTEXA15_CTR_FORMAT_SHIFT   (0x0000001Du)
#define CSL_CORTEXA15_CTR_FORMAT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_CTR_CWG_MASK       (0x0F000000u)
#define CSL_CORTEXA15_CTR_CWG_SHIFT      (0x00000018u)
#define CSL_CORTEXA15_CTR_CWG_RESETVAL   (0x00000000u)

#define CSL_CORTEXA15_CTR_ERG_MASK       (0x00F00000u)
#define CSL_CORTEXA15_CTR_ERG_SHIFT      (0x00000014u)
#define CSL_CORTEXA15_CTR_ERG_RESETVAL   (0x00000000u)

#define CSL_CORTEXA15_CTR_DMINLINE_MASK  (0x000F0000u)
#define CSL_CORTEXA15_CTR_DMINLINE_SHIFT (0x00000010u)
#define CSL_CORTEXA15_CTR_DMINLINE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_CTR_L1IP_MASK      (0x0000C000u)
#define CSL_CORTEXA15_CTR_L1IP_SHIFT     (0x0000000Eu)
#define CSL_CORTEXA15_CTR_L1IP_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_CTR_IMINLINE_MASK  (0x0000000Fu)
#define CSL_CORTEXA15_CTR_IMINLINE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_CTR_IMINLINE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_CTR_RESETVAL       (0x00000000u)

/* TLBTR */

#define CSL_CORTEXA15_TLBTR_NU_MASK      (0x00000001u)
#define CSL_CORTEXA15_TLBTR_NU_SHIFT     (0x00000000u)
#define CSL_CORTEXA15_TLBTR_NU_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_TLBTR_RESETVAL     (0x00000000u)

/* MPIDR */

#define CSL_CORTEXA15_MPIDR_U_MASK       (0x40000000u)
#define CSL_CORTEXA15_MPIDR_U_SHIFT      (0x0000001Eu)
#define CSL_CORTEXA15_MPIDR_U_RESETVAL   (0x00000000u)

#define CSL_CORTEXA15_MPIDR_MT_MASK      (0x01000000u)
#define CSL_CORTEXA15_MPIDR_MT_SHIFT     (0x00000018u)
#define CSL_CORTEXA15_MPIDR_MT_RESETVAL  (0x00000000u)

#define CSL_CORTEXA15_MPIDR_CLUSTERID_MASK (0x00000F00u)
#define CSL_CORTEXA15_MPIDR_CLUSTERID_SHIFT (0x00000008u)
#define CSL_CORTEXA15_MPIDR_CLUSTERID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MPIDR_CPUID_MASK   (0x00000003u)
#define CSL_CORTEXA15_MPIDR_CPUID_SHIFT  (0x00000000u)
#define CSL_CORTEXA15_MPIDR_CPUID_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_MPIDR_RESETVAL     (0x00000000u)

/* ID_PFR0 */

#define CSL_CORTEXA15_ID_PFR0_STATE3_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_PFR0_STATE3_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_PFR0_STATE3_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR0_STATE2_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_PFR0_STATE2_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_PFR0_STATE2_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR0_STATE1_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_PFR0_STATE1_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_PFR0_STATE1_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR0_STATE0_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_PFR0_STATE0_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_PFR0_STATE0_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR0_RESETVAL   (0x00000000u)

/* ID_PFR1 */

#define CSL_CORTEXA15_ID_PFR1_GENERICTIMER_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_PFR1_GENERICTIMER_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_PFR1_GENERICTIMER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR1_VIRTEXT_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_PFR1_VIRTEXT_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_PFR1_VIRTEXT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR1_MPROFPROGMODEL_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_PFR1_MPROFPROGMODEL_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_PFR1_MPROFPROGMODEL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR1_SECURITYEXT_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_PFR1_SECURITYEXT_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_PFR1_SECURITYEXT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR1_PROGMODEL_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_PFR1_PROGMODEL_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_PFR1_PROGMODEL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_PFR1_RESETVAL   (0x00000000u)

/* ID_DFR0 */

#define CSL_CORTEXA15_ID_DFR0_PERFMONMOD_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_DFR0_PERFMONMOD_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_DFR0_PERFMONMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_MDEBUGMOD_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_DFR0_MDEBUGMOD_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_DFR0_MDEBUGMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDTRACEMOD_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDTRACEMOD_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDTRACEMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_COPROCTRACEMOD_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_DFR0_COPROCTRACEMOD_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_DFR0_COPROCTRACEMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDDEBUGMOD_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDDEBUGMOD_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_DFR0_MEMMAPPEDDEBUGMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_COPROCSECDEBUGMOD_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_DFR0_COPROCSECDEBUGMOD_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_DFR0_COPROCSECDEBUGMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_COPROCDEBUGMOD_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_DFR0_COPROCDEBUGMOD_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_DFR0_COPROCDEBUGMOD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_DFR0_RESETVAL   (0x00000000u)

/* ID_MMFR0 */

#define CSL_CORTEXA15_ID_MMFR0_INNERSHAREABILITY_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_MMFR0_INNERSHAREABILITY_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_MMFR0_INNERSHAREABILITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_FCSESUPPORT_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_MMFR0_FCSESUPPORT_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_MMFR0_FCSESUPPORT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_AUXILIARYREGS_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_MMFR0_AUXILIARYREGS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_MMFR0_AUXILIARYREGS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_TCMSUPPORT_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_MMFR0_TCMSUPPORT_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_MMFR0_TCMSUPPORT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_SHAREABILITYLEVELS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_MMFR0_SHAREABILITYLEVELS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_MMFR0_SHAREABILITYLEVELS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_OUTERSHAREABILITY_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_MMFR0_OUTERSHAREABILITY_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_MMFR0_OUTERSHAREABILITY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_PMSASUPPORT_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_MMFR0_PMSASUPPORT_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_MMFR0_PMSASUPPORT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_VMSASUPPORT_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_MMFR0_VMSASUPPORT_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_MMFR0_VMSASUPPORT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR0_RESETVAL  (0x00000000u)

/* ID_MMFR1 */

#define CSL_CORTEXA15_ID_MMFR1_BRANCHPREDICTOR_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_MMFR1_BRANCHPREDICTOR_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_MMFR1_BRANCHPREDICTOR_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1TESTANDCLEAN_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_MMFR1_L1TESTANDCLEAN_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_MMFR1_L1TESTANDCLEAN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIED_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIED_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1HARVARD_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARD_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARD_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDSETWAY_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDSETWAY_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDSETWAY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDSETWAY_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDSETWAY_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDSETWAY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDVA_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDVA_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_MMFR1_L1UNIFIEDVA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDVA_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDVA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_MMFR1_L1HARVARDVA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR1_RESETVAL  (0x00000000u)

/* ID_MMFR2 */

#define CSL_CORTEXA15_ID_MMFR2_HWACCESSFLAG_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_MMFR2_HWACCESSFLAG_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_MMFR2_HWACCESSFLAG_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_WFISTALL_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_MMFR2_WFISTALL_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_MMFR2_WFISTALL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_MEMORYBARRIER_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_MMFR2_MEMORYBARRIER_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_MMFR2_MEMORYBARRIER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_UNIFIEDTLB_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_MMFR2_UNIFIEDTLB_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_MMFR2_UNIFIEDTLB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_HARVARDTLB_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_MMFR2_HARVARDTLB_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_MMFR2_HARVARDTLB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDRANGE_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDRANGE_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDRANGE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDBGPREFETCH_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDBGPREFETCH_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDBGPREFETCH_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDFGPREFETCH_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDFGPREFETCH_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_MMFR2_L1HARVARDFGPREFETCH_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR2_RESETVAL  (0x00000000u)

/* ID_MMFR3 */

#define CSL_CORTEXA15_ID_MMFR3_SUPERSECTIONSUPPORT_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_MMFR3_SUPERSECTIONSUPPORT_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_MMFR3_SUPERSECTIONSUPPORT_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_PHYSICALMEMSIZE_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_MMFR3_PHYSICALMEMSIZE_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_MMFR3_PHYSICALMEMSIZE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_COHERENTWALK_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_MMFR3_COHERENTWALK_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_MMFR3_COHERENTWALK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_MAINTENANCEBROADCAST_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_MMFR3_MAINTENANCEBROADCAST_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_MMFR3_MAINTENANCEBROADCAST_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_BRANCHPREDMAINTENANCE_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_MMFR3_BRANCHPREDMAINTENANCE_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_MMFR3_BRANCHPREDMAINTENANCE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYSETWAY_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYSETWAY_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYSETWAY_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYMVA_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYMVA_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_MMFR3_CACHEMAINTBYMVA_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_MMFR3_RESETVAL  (0x00000000u)

/* ID_ISAR0 */

#define CSL_CORTEXA15_ID_ISAR0_DIVIDEINSTRS_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_ISAR0_DIVIDEINSTRS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_ISAR0_DIVIDEINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_DEBUGINSTRS_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_ISAR0_DEBUGINSTRS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_ISAR0_DEBUGINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_COPROCINSTRS_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_ISAR0_COPROCINSTRS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_ISAR0_COPROCINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_CMPBRANCHINSTRS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_ISAR0_CMPBRANCHINSTRS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_ISAR0_CMPBRANCHINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_BITFIELDINSTRS_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_ISAR0_BITFIELDINSTRS_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_ISAR0_BITFIELDINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_BITCOUNTINSTRS_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_ISAR0_BITCOUNTINSTRS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_ISAR0_BITCOUNTINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_SWAPINSTRS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_ISAR0_SWAPINSTRS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_ISAR0_SWAPINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR0_RESETVAL  (0x00000000u)

/* ID_ISAR1 */

#define CSL_CORTEXA15_ID_ISAR1_JAZELLEINSTRS_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_ISAR1_JAZELLEINSTRS_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_ISAR1_JAZELLEINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_INTERWORKINSTRS_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_ISAR1_INTERWORKINSTRS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_ISAR1_INTERWORKINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_IMMEDIATEINSTRS_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_ISAR1_IMMEDIATEINSTRS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_ISAR1_IMMEDIATEINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_IFTHENINSTRS_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_ISAR1_IFTHENINSTRS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_ISAR1_IFTHENINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_EXTENDINSTRS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_ISAR1_EXTENDINSTRS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_ISAR1_EXTENDINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_EXCEPTARINSTRS_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_ISAR1_EXCEPTARINSTRS_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_ISAR1_EXCEPTARINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_EXCEPTINSTRS_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_ISAR1_EXCEPTINSTRS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_ISAR1_EXCEPTINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_ENDIANINSTRS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_ISAR1_ENDIANINSTRS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_ISAR1_ENDIANINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR1_RESETVAL  (0x00000000u)

/* ID_ISAR2 */

#define CSL_CORTEXA15_ID_ISAR2_REVERSALINSTRS_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_ISAR2_REVERSALINSTRS_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_ISAR2_REVERSALINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_PSRINSTRS_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_ISAR2_PSRINSTRS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_ISAR2_PSRINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_MULTUINSTRS_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_ISAR2_MULTUINSTRS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_ISAR2_MULTUINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_MULTSINSTRS_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_ISAR2_MULTSINSTRS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_ISAR2_MULTSINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_MULTINSTRS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_ISAR2_MULTINSTRS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_ISAR2_MULTINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_MULTIACCESSINTINSTRS_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_ISAR2_MULTIACCESSINTINSTRS_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_ISAR2_MULTIACCESSINTINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_MEMHINTINSTRS_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_ISAR2_MEMHINTINSTRS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_ISAR2_MEMHINTINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_LOADSTOREINSTRS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_ISAR2_LOADSTOREINSTRS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_ISAR2_LOADSTOREINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR2_RESETVAL  (0x00000000u)

/* ID_ISAR3 */

#define CSL_CORTEXA15_ID_ISAR3_THUMBEEEXTNINSTRS_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_ISAR3_THUMBEEEXTNINSTRS_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_ISAR3_THUMBEEEXTNINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_TRUENOPINSTRS_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_ISAR3_TRUENOPINSTRS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_ISAR3_TRUENOPINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_THUMBCOPYINSTRS_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_ISAR3_THUMBCOPYINSTRS_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_ISAR3_THUMBCOPYINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_TABBRANCHINSTRS_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_ISAR3_TABBRANCHINSTRS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_ISAR3_TABBRANCHINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_SYNCHPRIMINSTRS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_ISAR3_SYNCHPRIMINSTRS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_ISAR3_SYNCHPRIMINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_SVCINSTRS_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_ISAR3_SVCINSTRS_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_ISAR3_SVCINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_SIMDINSTRS_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_ISAR3_SIMDINSTRS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_ISAR3_SIMDINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_SATURATEINSTRS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_ISAR3_SATURATEINSTRS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_ISAR3_SATURATEINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR3_RESETVAL  (0x00000000u)

/* ID_ISAR4 */

#define CSL_CORTEXA15_ID_ISAR4_SWPFRAC_MASK (0xF0000000u)
#define CSL_CORTEXA15_ID_ISAR4_SWPFRAC_SHIFT (0x0000001Cu)
#define CSL_CORTEXA15_ID_ISAR4_SWPFRAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_PSRMINSTRS_MASK (0x0F000000u)
#define CSL_CORTEXA15_ID_ISAR4_PSRMINSTRS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_ID_ISAR4_PSRMINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_SYNCHPRIMINSTRSFRAC_MASK (0x00F00000u)
#define CSL_CORTEXA15_ID_ISAR4_SYNCHPRIMINSTRSFRAC_SHIFT (0x00000014u)
#define CSL_CORTEXA15_ID_ISAR4_SYNCHPRIMINSTRSFRAC_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_BARRIERINSTRS_MASK (0x000F0000u)
#define CSL_CORTEXA15_ID_ISAR4_BARRIERINSTRS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_ID_ISAR4_BARRIERINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_SMCINSTRS_MASK (0x0000F000u)
#define CSL_CORTEXA15_ID_ISAR4_SMCINSTRS_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_ID_ISAR4_SMCINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_WRITEBACKINSTRS_MASK (0x00000F00u)
#define CSL_CORTEXA15_ID_ISAR4_WRITEBACKINSTRS_SHIFT (0x00000008u)
#define CSL_CORTEXA15_ID_ISAR4_WRITEBACKINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_WITHSHIFTSINSTRS_MASK (0x000000F0u)
#define CSL_CORTEXA15_ID_ISAR4_WITHSHIFTSINSTRS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_ID_ISAR4_WITHSHIFTSINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_UNPRIVINSTRS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_ID_ISAR4_UNPRIVINSTRS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_ID_ISAR4_UNPRIVINSTRS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_ID_ISAR4_RESETVAL  (0x00000000u)

/* DBGITOCTRL */

#define CSL_CORTEXA15_DBGITOCTRL_NPMUIRQ_MASK (0x00000008u)
#define CSL_CORTEXA15_DBGITOCTRL_NPMUIRQ_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGITOCTRL_NPMUIRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITOCTRL_CTIPMUIRQ_MASK (0x00000004u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIPMUIRQ_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIPMUIRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGRESTARTED_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGRESTARTED_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGRESTARTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGTRIGGER_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGTRIGGER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGITOCTRL_CTIDBGTRIGGER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITOCTRL_RESETVAL (0x00000000u)

/* DBGITISR */

#define CSL_CORTEXA15_DBGITISR_DBGSWENABLE_MASK (0x00000008u)
#define CSL_CORTEXA15_DBGITISR_DBGSWENABLE_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGITISR_DBGSWENABLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITISR_CTIDBGRESTART_MASK (0x00000004u)
#define CSL_CORTEXA15_DBGITISR_CTIDBGRESTART_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGITISR_CTIDBGRESTART_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITISR_CTIEDBGRQ_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGITISR_CTIEDBGRQ_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGITISR_CTIEDBGRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITISR_EDBGRQ_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGITISR_EDBGRQ_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGITISR_EDBGRQ_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITISR_RESETVAL  (0x00000000u)

/* DBGITCTRL */

#define CSL_CORTEXA15_DBGITCTRL_IME_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGITCTRL_IME_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGITCTRL_IME_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGITCTRL_RESETVAL (0x00000000u)

/* DBGCLAIMSET */

#define CSL_CORTEXA15_DBGCLAIMSET_CLAIM_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGCLAIMSET_CLAIM_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCLAIMSET_CLAIM_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCLAIMSET_RESETVAL (0x00000000u)

/* DBGCLAIMCLR */

#define CSL_CORTEXA15_DBGCLAIMCLR_CLAIM_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGCLAIMCLR_CLAIM_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCLAIMCLR_CLAIM_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCLAIMCLR_RESETVAL (0x00000000u)

/* DBGLAR */

#define CSL_CORTEXA15_DBGLAR_LOCKACCESSCONTROL_MASK (0xFFFFFFFFu)
#define CSL_CORTEXA15_DBGLAR_LOCKACCESSCONTROL_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGLAR_LOCKACCESSCONTROL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGLAR_RESETVAL    (0x00000000u)

/* DBGLSR */

#define CSL_CORTEXA15_DBGLSR_X32BITACCESS_MASK (0x00000004u)
#define CSL_CORTEXA15_DBGLSR_X32BITACCESS_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGLSR_X32BITACCESS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGLSR_LOCKED_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGLSR_LOCKED_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGLSR_LOCKED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGLSR_LOCKIMPLEMENTED_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGLSR_LOCKIMPLEMENTED_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGLSR_LOCKIMPLEMENTED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGLSR_RESETVAL    (0x00000000u)

/* DBGAUTHSTATUS */

#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGFEATURESIMPL_MASK (0x00000080u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGFEATURESIMPL_SHIFT (0x00000007u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGFEATURESIMPL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGEN_MASK (0x00000040u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGEN_SHIFT (0x00000006u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECNONINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGFEATURESIMPL_MASK (0x00000020u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGFEATURESIMPL_SHIFT (0x00000005u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGFEATURESIMPL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGEN_MASK (0x00000010u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGEN_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_SECINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGFEATURSIMPL_MASK (0x00000008u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGFEATURSIMPL_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGFEATURSIMPL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGEN_MASK (0x00000004u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGEN_SHIFT (0x00000002u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECNONINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGFEATURESIMPL_MASK (0x00000002u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGFEATURESIMPL_SHIFT (0x00000001u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGFEATURESIMPL_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGEN_MASK (0x00000001u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGEN_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGAUTHSTATUS_NONSECINVDBGEN_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGAUTHSTATUS_RESETVAL (0x00000000u)

/* DBGDEVID0 */

#define CSL_CORTEXA15_DBGDEVID0_AUXREGS_MASK (0x0F000000u)
#define CSL_CORTEXA15_DBGDEVID0_AUXREGS_SHIFT (0x00000018u)
#define CSL_CORTEXA15_DBGDEVID0_AUXREGS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_DOUBLELOCK_MASK (0x00F00000u)
#define CSL_CORTEXA15_DBGDEVID0_DOUBLELOCK_SHIFT (0x00000014u)
#define CSL_CORTEXA15_DBGDEVID0_DOUBLELOCK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_VIRTEXTNS_MASK (0x000F0000u)
#define CSL_CORTEXA15_DBGDEVID0_VIRTEXTNS_SHIFT (0x00000010u)
#define CSL_CORTEXA15_DBGDEVID0_VIRTEXTNS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_VECTORCATCH_MASK (0x0000F000u)
#define CSL_CORTEXA15_DBGDEVID0_VECTORCATCH_SHIFT (0x0000000Cu)
#define CSL_CORTEXA15_DBGDEVID0_VECTORCATCH_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_BPADDRMASK_MASK (0x00000F00u)
#define CSL_CORTEXA15_DBGDEVID0_BPADDRMASK_SHIFT (0x00000008u)
#define CSL_CORTEXA15_DBGDEVID0_BPADDRMASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_WPADDRMASK_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGDEVID0_WPADDRMASK_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGDEVID0_WPADDRMASK_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_PCSAMPLE_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGDEVID0_PCSAMPLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDEVID0_PCSAMPLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVID0_RESETVAL (0x00000000u)

/* DBGDEVTYPE */

#define CSL_CORTEXA15_DBGDEVTYPE_SUBTYPE_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGDEVTYPE_SUBTYPE_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGDEVTYPE_SUBTYPE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVTYPE_MAINCLASS_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGDEVTYPE_MAINCLASS_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGDEVTYPE_MAINCLASS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGDEVTYPE_RESETVAL (0x00000000u)

/* DBGPID4 */

#define CSL_CORTEXA15_DBGPID4_COUNT4KB_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGPID4_COUNT4KB_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGPID4_COUNT4KB_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID4_JEP106CONTCODE_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGPID4_JEP106CONTCODE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPID4_JEP106CONTCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID4_RESETVAL   (0x00000000u)

/* DBGPID5 */

#define CSL_CORTEXA15_DBGPID5_RESETVAL   (0x00000000u)

/* DBGPID6 */

#define CSL_CORTEXA15_DBGPID6_RESETVAL   (0x00000000u)

/* DBGPID7 */

#define CSL_CORTEXA15_DBGPID7_RESETVAL   (0x00000000u)

/* DBGPID0 */

#define CSL_CORTEXA15_DBGPID0_PARTNUMBER_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGPID0_PARTNUMBER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPID0_PARTNUMBER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID0_RESETVAL   (0x00000000u)

/* DBGPID1 */

#define CSL_CORTEXA15_DBGPID1_JEP106IDCODE_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGPID1_JEP106IDCODE_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGPID1_JEP106IDCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID1_PARTNUMBER_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGPID1_PARTNUMBER_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPID1_PARTNUMBER_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID1_RESETVAL   (0x00000000u)

/* DBGPID2 */

#define CSL_CORTEXA15_DBGPID2_REVISION_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGPID2_REVISION_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGPID2_REVISION_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID2_USESJEP106IDCODE_MASK (0x00000008u)
#define CSL_CORTEXA15_DBGPID2_USESJEP106IDCODE_SHIFT (0x00000003u)
#define CSL_CORTEXA15_DBGPID2_USESJEP106IDCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID2_JEP106IDCODE_MASK (0x00000007u)
#define CSL_CORTEXA15_DBGPID2_JEP106IDCODE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPID2_JEP106IDCODE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID2_RESETVAL   (0x00000000u)

/* DBGPID3 */

#define CSL_CORTEXA15_DBGPID3_REVAND_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGPID3_REVAND_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGPID3_REVAND_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID3_CUSTOMERMODIFIED_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGPID3_CUSTOMERMODIFIED_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGPID3_CUSTOMERMODIFIED_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGPID3_RESETVAL   (0x00000000u)

/* DBGCID0 */

#define CSL_CORTEXA15_DBGCID0_PREAMBLE_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGCID0_PREAMBLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCID0_PREAMBLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCID0_RESETVAL   (0x00000000u)

/* DBGCID1 */

#define CSL_CORTEXA15_DBGCID1_COMPONENTCLASS_MASK (0x000000F0u)
#define CSL_CORTEXA15_DBGCID1_COMPONENTCLASS_SHIFT (0x00000004u)
#define CSL_CORTEXA15_DBGCID1_COMPONENTCLASS_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCID1_PREAMBLE_MASK (0x0000000Fu)
#define CSL_CORTEXA15_DBGCID1_PREAMBLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCID1_PREAMBLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCID1_RESETVAL   (0x00000000u)

/* DBGCID2 */

#define CSL_CORTEXA15_DBGCID2_PREAMBLE_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGCID2_PREAMBLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCID2_PREAMBLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCID2_RESETVAL   (0x00000000u)

/* DBGCID3 */

#define CSL_CORTEXA15_DBGCID3_PREAMBLE_MASK (0x000000FFu)
#define CSL_CORTEXA15_DBGCID3_PREAMBLE_SHIFT (0x00000000u)
#define CSL_CORTEXA15_DBGCID3_PREAMBLE_RESETVAL (0x00000000u)

#define CSL_CORTEXA15_DBGCID3_RESETVAL   (0x00000000u)

#endif
