C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: 
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6657L GEL file Ver is 1.003 
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache... 
C66xx_0: GEL Output: L1P = 32K   
C66xx_0: GEL Output: L1D = 32K   
C66xx_0: GEL Output: L2 = ALL SRAM   
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL in Bypass ... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR3 Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL: Error while executing OnTargetConnect(): Evaluation canceled.
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.