#include "../include/io_addr.h"
#include "../include/type.h"
#include "../include/DataType.h"
#include "../include/C6747_reg.h"
#include "../include/edma3.h"

extern s16 AD0_Data_Buf[100][750];
//extern u16 AD1_Data_Buf[100][750];
//extern u16 AD2_Data_Buf[100][750];
//extern u16 AD3_Data_Buf[100][750];

extern u16 period_cnt;
extern ChannelDataInfo Channel_1_Up;
extern s8 SaveDataFlag;

u8 Flag0 = 1;
u8 Flag1 = 0;

extern s16 REV_Data[750];
//жϺ
void interrupt FPGA_1_isr()
{
/*	u16 temp = 0;
	u16	rx_num = 0;
	u16	rx_num_1 = 0;
	u16 info = 0;
	u16 cnt = 0;
	u16 cnt_1 = 0;

 	rx_num = 750;
	while(rx_num)
	{
		temp = *(vs16 *)(ADC_START_ADDR + AD2_FIFO);//ȡֽ
		info =  temp & 0x3fff;

		AD0_Data_Buf[period_cnt][cnt] = info;
		cnt++;
		rx_num--;

		if (rx_num == 0)
		{
			cnt = 0;
			period_cnt++;
			break;
		}
	}

	rx_num_1 = 750;
	while(rx_num_1)
	{
		temp = *(vs16 *)(ADC_START_ADDR + AD3_FIFO);//ȡֽ
		info =  temp & 0x3fff;

		AD0_Data_Buf[period_cnt+49][cnt_1] = info;
		cnt_1++;
		rx_num_1--;

		if (rx_num_1 == 0)
		{
			cnt_1 = 0;
			break;
		}
	}

	if (period_cnt == 50)
	{
		period_cnt = 0;
		SaveDataFlag = 1;
	//	CSR = 0;
	}*/
}

