/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2011
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
Interrupts configuration for QMSS
 * =============================================================================
 *  Revision History
 *  ===============
 *  8-May-2011 Brighton Feng  file created
 * =============================================================================
 */

#include <stdio.h>
#include <c6x.h> 
#include <csl_cpintc.h>
#include "KeyStone_common.h"

int uiQ662_pend_system_event_num;
int uiQ662_pend_host_event_num;

void CIC_Init_QM(void)
{
	TDSP_Board_Type DSP_Board_Type;

	/* Disable Global host interrupts. */
	gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 0;

	DSP_Board_Type= KeyStone_Get_dsp_board_type();
	if(C6670_EVM==DSP_Board_Type
		||DUAL_NYQUIST_EVM==DSP_Board_Type
		||TCI6614_EVM==DSP_Board_Type)
	{	
		uiQ662_pend_system_event_num= 134;
		uiQ662_pend_host_event_num= 64;
		
		/*map Queue 662 pend interrupts events (134) to CIC0 out64*/
		KeyStone_CIC_event_map(gpCIC0_regs, 134, 64);
	}
	else if(C6678_EVM==DSP_Board_Type)
	{	
		/*map Queue 662 pend interrupts events (156) to CIC0 out33*/
		uiQ662_pend_system_event_num= 156;
		uiQ662_pend_host_event_num= 33;

		KeyStone_CIC_event_map(gpCIC0_regs, 156, 33);
	}
	else if(C6657_EVM==DSP_Board_Type)
	{
		uiQ662_pend_system_event_num= 134;
		uiQ662_pend_host_event_num= 0;

		/*map Queue 662 pend interrupts events (134) to CIC0 out0*/
		KeyStone_CIC_event_map(gpCIC0_regs, 134, 0);
	}
	else
	{
		puts("Unknown DSP board type!");
		return;
	}	

	/* Enable Global host interrupts. */
	gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 1;

}

void QM_Interrupts_Init(void)
{
	CIC_Init_QM();
	
	//map high priority queue channel 0 interrupt to INT4
	//map low priority queues channel 0 interrupt to INT5
	/*on Nyquist, CIC0 out64 event number are 22 on core 0		
	on Shannon, CIC0 out33 event number are 22 on core0		
	on Gauss, CIC0 out0 event number are 22 on core0
	map this event 22 to INT6 */
	gpCGEM_regs->INTMUX1 = (CSL_GEM_QM_INT_HIGH_N<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)|
		(CSL_GEM_QM_INT_LOW_0<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)|
		(22<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT);

	 /*Clear all DSP core events*/
	gpCGEM_regs->EVTCLR[0]= 	0xFFFFFFFF;
	gpCGEM_regs->EVTCLR[1]= 	0xFFFFFFFF;
	gpCGEM_regs->EVTCLR[2]= 	0xFFFFFFFF;
	gpCGEM_regs->EVTCLR[3]= 	0xFFFFFFFF;

	//clear DSP core interrupt flag
	ICR= IFR;

	//enable INT4, 5, 6
	IER = 3|(1<<4)|(1<<5)|(1<<6);

	/*Interrupt Service Table Pointer to begining of LL2 memory*/
	ISTP= 0x800000;

	//enable GIE
	TSR = TSR|1;
}


