/******************************************************************************

  Copyright (C), 2001-2012, Texas Instrument.

 ******************************************************************************
  File Name     : Robust_DDR_XMC_MP.c
  Version       : Initial Draft
  Author        : Zhan
  Created       : 2012/3/12
  Last Modified :
  Description   : DDR3 XMC memory protection example
  Function List :
              DDR3MemoryBufInit
              XMC_DDR_MP_test
  History       :
  1.Date        : 2012/3/12
    Author      : Zhan
    Modification: Created file

******************************************************************************/

#include <stdio.h>
#include "KeyStone_common.h"
/*----------------------------------------------*
 * external variables                           *
 *----------------------------------------------*/

/*----------------------------------------------*
 * external routine prototypes                  *
 *----------------------------------------------*/

/*----------------------------------------------*
 * internal routine prototypes                  *
 *----------------------------------------------*/

/*----------------------------------------------*
 * project-wide global variables                *
 *----------------------------------------------*/

/*----------------------------------------------*
 * module-wide global variables                 *
 *----------------------------------------------*/

/*total 64K data for DDR3*/
#pragma DATA_SECTION(ddr3MPDataDst, "ddr3MPData_w")
#pragma DATA_ALIGN(ddr3MPDataDst,64*1024) //align to MPAX segment bouandary
volatile char ddr3MPDataDst[2][32768];

/* 4K per segments */
#pragma DATA_SECTION(ddr3MPDataSrc, "ddr3MPData_r")
#pragma DATA_ALIGN(ddr3MPDataSrc,16*1024) //align to MPAX segment bouandary
volatile char ddr3MPDataSrc[4][4096];

/*memory protection and address extension configuration table*/
#pragma DATA_SECTION(DDR_MPAX_cfg_table,".far:Core_MPAX")
MPAX_Config DDR_MPAX_cfg_table[]=
{
    /*BADDR                  RADDR           SegementSize            AccessPermisionMask
    32-bit virtual           36-bit physical in byte, must           Access types allowed
    base address             address right   be power of 2           in this address range
                             shift by 4                                                    */
    {(Uint32)ddr3MPDataDst,  0,              sizeof(ddr3MPDataDst), MP_SW|MP_UW},/*write only data*/
    {(Uint32)ddr3MPDataSrc,  0,              sizeof(ddr3MPDataSrc), MP_SR|MP_UR}/*read only data*/
};

/*----------------------------------------------*
 * constants                                    *
 *----------------------------------------------*/

/*----------------------------------------------*
 * macros                                       *
 *----------------------------------------------*/

/*----------------------------------------------*
 * routines' implementations                    *
 *----------------------------------------------*/
/*****************************************************************************
 Prototype    : DDR3MemoryBufInit
 Description  : DDR3 XMC test buffer initialization
 Input        : None
 Output       : None
 Return Value : 
 
  History        :
  1.Date         : 2012/3/12
    Author       : Zhan
    Modification : Created function

*****************************************************************************/
void DDR3MemoryBufInit()
{
	int i;
	for(i=0; i<4096; i++)
	{
		ddr3MPDataSrc[0][i] = i;
		ddr3MPDataSrc[1][i] = i;
		ddr3MPDataSrc[2][i] = i;
		ddr3MPDataSrc[3][i] = i;

	}

	for(i=0; i<32768; i++)
	{
		ddr3MPDataDst[0][i] = 0xFF;
		ddr3MPDataDst[1][i] = 0xFF;
	}
	return;
}

/*****************************************************************************
 Prototype    : XMC_DDR_MP_test
 Description  : DDR3 memory protection test, the 64K data was used for test
 Input        : None
 Output       : None
 Return Value : 
 
  History        :
  1.Date         : 2012/10/28
    Author       : Zhan
    Modification : Created function

*****************************************************************************/
void XMC_DDR_MP_test()
{
	volatile char readVal;

	puts("===================-XMC DDR memory protection test-==============");

	DDR3MemoryBufInit();

	DDR_MPAX_cfg_table[0].RADDR= DDR_PHY_ADDR(DDR_MPAX_cfg_table[0].BADDR);
	DDR_MPAX_cfg_table[1].RADDR= DDR_PHY_ADDR(DDR_MPAX_cfg_table[1].BADDR);
	KeyStone_XMC_MPAX_setup(DDR_MPAX_cfg_table, 14,
		sizeof(DDR_MPAX_cfg_table)/sizeof(MPAX_Config));

	/* The first write is allowed */
	printf("DSP core write to 0x%x which is write-only...\n",
		&ddr3MPDataDst[0][1024]);
	ddr3MPDataDst[0][1024] = 0xAA;

	/* The first read is allowed */
	printf("DSP core read from 0x%x which is read-only...\n",
		&ddr3MPDataSrc[0][2056]);
	readVal = ddr3MPDataSrc[0][2056];

	/* Read the DDR trigger memory protection */
	printf("\n!!!DSP core read from 0x%x which is write-only...\n",
		&ddr3MPDataDst[1][2111]);
	readVal = ddr3MPDataDst[1][2111];

	/*normally, exception is captured about 10~100 cycles after the 
	access violation. Dummy operations added here to wait for it.*/
	asm(" nop 5");
	asm(" nop 5");
	asm(" nop 5"); 	
	asm(" nop 5"); /*NRP should be around the address of this instruction*/	
	asm(" nop 5"); 	

	/* Write the DDR trigger memory protection */
	printf("\n!!!DSP core write to 0x%x which is read-only...\n",
		&ddr3MPDataSrc[1][1100]);
	ddr3MPDataSrc[1][1100] = 0x11;

	/*normally, exception is captured about 10~100 cycles after the 
	access violation. Dummy operations added here to wait for it.*/
	asm(" nop 5");
	asm(" nop 5");
	asm(" nop 5");
	asm(" nop 5");
	asm(" nop 5");
	asm(" nop 5"); 	/*NRP should be around the address of this instruction*/
	asm(" nop 5"); 	
}




