#include <stdio.h>
#include <c6x.h>
#include "types.h"
#include "interrupt.h"
#define MAILBOX5_BASE_ADDR		0x48840000
#define MAILBOX13_BASE_ADDR		0x48802000
#define RD_MEM_32(addr) 	  	 *(volatile unsigned int*)(addr)
#define WR_MEM_32(addr, data)    do {*(volatile unsigned int*)(addr) =(unsigned int)(data);}while(0)

/*
MAILBOX13_IRQ_U IRQ_CROSSBAR_379 – MAILBOX13 user 0 interrupt request.	mpu		m=0
SER0
MAILBOX13_IRQ_U IRQ_CROSSBAR_380 – MAILBOX13 user 1 interrupt request.	dsp1	m=1
SER1
MAILBOX13_IRQ_U IRQ_CROSSBAR_381 – MAILBOX13 user 2 interrupt request.	dsp2	m=2
SER2
MAILBOX13_IRQ_U IRQ_CROSSBAR_382 – MAILBOX13 user 3 interrupt request.	none
 * */


#define MAILBOX_MESSAGE_DSP1   (MAILBOX13_BASE_ADDR+0x40+0x4*1)
#define MAILBOX_FIFOSTATUS_DSP1    (MAILBOX13_BASE_ADDR+0x80+0x4*1)
#define MAILBOX_MSGSTATUS_DSP1   (MAILBOX13_BASE_ADDR+0xc0+0x4*1)
#define MAILBOX_IRQSTATUS_RAW_U_DSP1   (MAILBOX13_BASE_ADDR+0x100+0x10*1)
#define MAILBOX_IRQSTATUS_CLR_U_DSP1   (MAILBOX13_BASE_ADDR+0x104+0x10*1)
#define MAILBOX_IRQENABLE_SET_U_DSP1   (MAILBOX13_BASE_ADDR+0x108+0x10*1)
#define MAILBOX_IRQENABLE_CLR_U_DSP1   (MAILBOX13_BASE_ADDR+0x10c+0x10*1)

#define MAILBOX_MESSAGE_DSP2   (MAILBOX13_BASE_ADDR+0x40+0x4*2)
#define MAILBOX_FIFOSTATUS_DSP2    (MAILBOX13_BASE_ADDR+0x80+0x4*2)
#define MAILBOX_MSGSTATUS_DSP2   (MAILBOX13_BASE_ADDR+0xc0+0x4*2)
#define MAILBOX_IRQSTATUS_RAW_U_DSP2   (MAILBOX13_BASE_ADDR+0x100+0x10*2)
#define MAILBOX_IRQSTATUS_CLR_U_DSP2   (MAILBOX13_BASE_ADDR+0x104+0x10*2)
#define MAILBOX_IRQENABLE_SET_U_DSP2   (MAILBOX13_BASE_ADDR+0x108+0x10*2)
#define MAILBOX_IRQENABLE_CLR_U_DSP2   (MAILBOX13_BASE_ADDR+0x10c+0x10*2)

#define MAILBOX_MESSAGE_MPU   (MAILBOX5_BASE_ADDR+0x40+0x4*2)
#define MAILBOX_FIFOSTATUS_MPU    (MAILBOX5_BASE_ADDR+0x80+0x4*2)
#define MAILBOX_MSGSTATUS_MPU   (MAILBOX5_BASE_ADDR+0xc0+0x4*2)
#define MAILBOX_IRQSTATUS_RAW_U_MPU   (MAILBOX5_BASE_ADDR+0x100+0x10*2)
#define MAILBOX_IRQSTATUS_CLR_U_MPU   (MAILBOX5_BASE_ADDR+0x104+0x10*2)
#define MAILBOX_IRQENABLE_SET_U_MPU   (MAILBOX5_BASE_ADDR+0x108+0x10*2)
#define MAILBOX_IRQENABLE_CLR_U_MPU   (MAILBOX5_BASE_ADDR+0x10c+0x10*2)

#define CTRL_CORE_DSP1_IRQ_56_57	0x4A002978
#define CTRL_CORE_DSP2_IRQ_56_57	0x4A0029F8

void sendmsg_mpu(int msg)
{
	WR_MEM_32(MAILBOX_IRQENABLE_SET_U_MPU,RD_MEM_32(MAILBOX_IRQENABLE_SET_U_MPU) | (0x1<<4));
	WR_MEM_32(MAILBOX_MESSAGE_MPU,msg);
}
void sendmsg_dsp2(int msg)
{
	WR_MEM_32(MAILBOX_IRQENABLE_SET_U_DSP2,RD_MEM_32(MAILBOX_IRQENABLE_SET_U_DSP2) | (0x1<<4));
	WR_MEM_32(MAILBOX_MESSAGE_DSP2,msg);
}
void sendmsg_dsp1(int msg)
{
	WR_MEM_32(MAILBOX_IRQENABLE_SET_U_DSP1,RD_MEM_32(MAILBOX_IRQENABLE_SET_U_DSP1) | (0x1<<2));
	WR_MEM_32(MAILBOX_MESSAGE_DSP1,msg);
}
/*mailbox10*/
int i = 0;
static void MailBoxIsr(void)
{
    unsigned int temp;
    IntDisable(C674X_MASK_INT5);
    IntEventClear(SYS_INT_MAILBOX);
    if(RD_MEM_32(MAILBOX_IRQSTATUS_CLR_U_DSP2)&(0x1<<4))
    {
    	while(RD_MEM_32(MAILBOX_MSGSTATUS_DSP2))
    	{
    		temp = RD_MEM_32(MAILBOX_MESSAGE_DSP2);
    	}
    	WR_MEM_32(MAILBOX_IRQSTATUS_CLR_U_DSP2,(0x1<<4));
    }
    IntEnable(C674X_MASK_INT5);
  //  if(check_memory(temp))
    sendmsg_mpu(temp);
}
//map IRQ_CROSSBAR_381 to dsp2 irq57
void init_irq_crossbar()
{
	WR_MEM_32(CTRL_CORE_DSP2_IRQ_56_57,(RD_MEM_32(CTRL_CORE_DSP2_IRQ_56_57) & 0xffff)| (381<<16));
}
void main (void)
{

	  /* Initialize the DSP interrupt controller */
	    IntDSPINTCInit();

	    /* Register ISR to vector table */
	    IntRegister(C674X_MASK_INT5, MailBoxIsr);

	    /* Map system interrupt to DSP maskable interrupt */
	    IntEventMap(C674X_MASK_INT5, SYS_INT_MAILBOX);

	    /* Enable DSP maskable interrupt */
	    IntEnable(C674X_MASK_INT5);
	    init_irq_crossbar();
	    /* Enable DSP interrupts */
	    IntGlobalEnable();
	while(1);
}


