#ifndef _MAILBOX_H_
#define _MAILBOX_H_
 
#ifndef MAILBOX_MAJOR
#define MAILBOX_MAJOR 0   
#endif
 
struct mailbox_dev                                     
{                                                        
  char *data;                      
  unsigned long size;       
};
/* Use 'k' as magic number */
#define MAILBOX_IOC_MAGIC  'k'
/* Please use a different 8-bit number in your code */

#define MAILBOX_DSP1_START    _IOWR(MAILBOX_IOC_MAGIC, 0,int)
#define MAILBOX_SENDMSG_DSP1      _IOWR(MAILBOX_IOC_MAGIC,1,int)
#define MAILBOX_RECVMSG      _IOWR(MAILBOX_IOC_MAGIC,2,int)
#define MAILBOX_DSP2_START    _IOWR(MAILBOX_IOC_MAGIC, 3,int)
#define MAILBOX_SENDMSG_DSP2      _IOWR(MAILBOX_IOC_MAGIC,4,int)


#define  MAILBOX_IOC_MAXNR  7


#define MAILBOX5_BASE_ADDR		0x48840000
#define MAILBOX13_BASE_ADDR		0x48802000


#define WR_MEM_32(addr, data)    do {*(volatile unsigned int*)(addr) =(unsigned int)(data);}while(0)
#define RD_MEM_32(addr) 	  	 *(volatile unsigned int*)(addr)
#define REG(x)              (*((volatile uint32_t *)(x)))

unsigned char* v_MAILBOX5_BASE_ADDR = 0;
unsigned char* v_MAILBOX13_BASE_ADDR = 0;

int MAILBOX_MESSAGE_DSP1;
int MAILBOX_FIFOSTATUS_DSP1 ;
int MAILBOX_MSGSTATUS_DSP1 ;
int MAILBOX_IRQSTATUS_RAW_U_DSP1   ;
int MAILBOX_IRQSTATUS_CLR_U_DSP1   ;
int MAILBOX_IRQENABLE_SET_U_DSP1   ;
int MAILBOX_IRQENABLE_CLR_U_DSP1   ;

int MAILBOX_MESSAGE_DSP2   ;
int MAILBOX_FIFOSTATUS_DSP2    ;
int  MAILBOX_MSGSTATUS_DSP2   ;
int MAILBOX_IRQSTATUS_RAW_U_DSP2   ;
int MAILBOX_IRQSTATUS_CLR_U_DSP2   ;
int MAILBOX_IRQENABLE_SET_U_DSP2   ;
int MAILBOX_IRQENABLE_CLR_U_DSP2   ;

int MAILBOX_MESSAGE_MPU   ;
int MAILBOX_FIFOSTATUS_MPU    ;
int MAILBOX_MSGSTATUS_MPU   ;
int MAILBOX_IRQSTATUS_RAW_U_MPU   ;
int MAILBOX_IRQSTATUS_CLR_U_MPU   ;
int MAILBOX_IRQENABLE_SET_U_MPU   ;
int MAILBOX_IRQENABLE_CLR_U_MPU   ;



#define DSP1_L2_SRAM_TARG            0x40800000
#define DSP2_L2_SRAM_TARG            0x41000000
#define L4_CFG_TARG                  0x4A000000
#define L4_WKUP_TARG                 0x4AE00000


/*******************************************************************************
        L4_CFG Registers Map Defines: CortexA15_CPU1 view
*******************************************************************************/
#define CTRL_MODULE_CORE             (L4_CFG_TARG + 0x2000)
#define CM_CORE_AON                  (L4_CFG_TARG + 0x5000)



/*******************************************************************************
        L4_WKUP Registers Map Defines: CortexA15_CPU1 view
*******************************************************************************/
#define PRM                          (L4_WKUP_TARG + 0x6000)

/*******************************************************************************
        PRCM Registers Map Defines: CortexA15_CPU1 view
*******************************************************************************/

#define DSP1_CM_CORE_AON             (CM_CORE_AON + 0x400)
#define DSP2_CM_CORE_AON             (CM_CORE_AON + 0x600)
#define DSP1_PRM                     (PRM + 0x400)
#define DSP2_PRM                     (PRM + 0x1B00)
int v_DSP1_L2_SRAM_TARG = 0;
int v_DSP2_L2_SRAM_TARG = 0;
int v_CTRL_MODULE_CORE = 0;
int v_DSP1_CM_CORE_AON = 0;
int v_DSP2_CM_CORE_AON = 0;
int v_DSP1_PRM = 0;
int v_DSP2_PRM = 0;
/*******************************************************************************
        DSPSS1 Address Map defines: CortexA15_CPU1 view
*******************************************************************************/
int CM_DSP1_CLKSTCTRL           ;
int CM_DSP1_DSP1_CLKCTRL         ;
int RM_DSP1_RSTCTRL             ;
int RM_DSP1_RSTST                ;
int DSPSS1BOOTADDR             ;
int DSPSS1BOOTADDRVALUE       ;

/*******************************************************************************
        DSPSS2 Address Map defines: CortexA15_CPU1 view
*******************************************************************************/
int CM_DSP2_CLKSTCTRL        ;
int CM_DSP2_DSP2_CLKCTRL     ;
int RM_DSP2_RSTCTRL          ;
int RM_DSP2_RSTST            ;
int DSPSS2BOOTADDR            ;
int DSPSS2BOOTADDRVALUE       ;


#endif