;*******************************************************************************
;   MSP430F22x4 Demo - Timer_A, Toggle P1.0-3, Cont. Mode ISR, HF XTAL ACLK
;
;   Description: Use Timer_A CCRx units and overflow to generate four
;   independent timing intervals. For demonstration, TACCR0, TACCR1 and TACCR2
;   output units are optionally selected with port pins P1.1, P1.2 and P1.3
;   in toggle mode. As such, these pins will toggle when respective TACCRx
;   registers match the TAR counter. Interrupts are also enabled with all
;   TACCRx units, software loads offset to next interval only - as long as the
;   interval offset is added to TACCRx, toggle rate is generated in hardware.
;   Timer_A overflow ISR is used to toggle P1.0 with software. Proper use
;   of the TAIV interrupt vector generator is demonstrated.
;   ACLK = MCLK = TACLK = LFXT1 = HF XTAL
;   //* Min Vcc required varies with MCLK frequency - refer to datasheet *//
;
;   As coded with TACLK= HF XTAL and assuming HF XTAL = 8MHz, toggle rates are:
;   P1.1 = TACCR0 = 8MHz/(2*200) = 20kHz
;   P1.2 = TACCR1 = 8MHz/(2*1000) = 4kHz
;   P1.3 = TACCR2 = 8MHz/(2*10000) = 400Hz
;   P1.0 = overflow = 8MHz/(2*65536) = 61Hz
;
;                MSP430F22x4
;             -----------------
;         /|\|              XIN|-
;          | |                 | HF XTAL (3 – 16MHz crystal or resonator)
;          --|RST          XOUT|-
;            |                 |
;            |         P1.1/TA0|--> TACCR0
;            |         P1.2/TA1|--> TACCR1
;            |         P1.3/TA2|--> TACCR2
;            |             P1.0|--> Overflow/software
;
;   A. Dannenberg
;   Texas Instruments Inc.
;   April 2006
;   Built with IAR Embedded Workbench Version: 3.41A
;*******************************************************************************
#include "msp430x22x4.h"
;-------------------------------------------------------------------------------
            RSEG    CSTACK                  ; Define stack segment
;-------------------------------------------------------------------------------
            RSEG    CODE                    ; Assemble to Flash memory
;-------------------------------------------------------------------------------
RESET       mov.w   #SFE(CSTACK),SP         ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP1     bis.b   #00Eh,&P1SEL            ; P1.1 - P1.3 option select
            bis.b   #00Fh,&P1DIR            ; P1.0-3 outputs
SetupBC     bis.b   #XTS,&BCSCTL1           ; LFXT1 = HF XTAL
            mov.b   #LFXT1S1,&BCSCTL3       ; LFXT1S1 = 3-16Mhz
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag
            mov.w   #0FFh,R15               ; R15 = Delay
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set?
            jnz     SetupOsc                ; OSC Fault, clear flag again
            bis.b   #SELM_3,&BCSCTL2        ; MCLK = LFXT1
SetupC0     mov.w   #OUTMOD_4+CCIE,&TACCTL0 ; TACCR0 toggle, interrupt enabled
SetupC1     mov.w   #OUTMOD_4+CCIE,&TACCTL1 ; TACCR1 toggle, interrupt enabled
SetupC2     mov.w   #OUTMOD_4+CCIE,&TACCTL2 ; TACCR2 toggle, interrupt enabled
SetupTA     mov.w   #TASSEL_1+MC_2+TAIE,&TACTL   ; ACLK, contmode, interrupt
                                            ;
Mainloop    bis.w   #LPM3+GIE,SR            ; Enter LPM3, interrupts enabled
            nop                             ; Required for debugger
                                            ;
;-------------------------------------------------------------------------------
TA0_ISR;
;-------------------------------------------------------------------------------
            add.w   #200,&TACCR0            ; Offset until next interrupt
            reti                            ;
                                            ;
;-------------------------------------------------------------------------------
TAX_ISR;    Common ISR for TACCR1-2 and overflow
;-------------------------------------------------------------------------------
            add.w   &TAIV,PC                ; Add Timer_A offset vector
            reti                            ; No interrupt
            jmp     TACCR1_ISR              ; TACCR1
            jmp     TACCR2_ISR              ; TACCR2
            reti                            ; Reserved
            reti                            ; Reserved
TA_over     xor.b   #001h,&P1OUT            ; Toggle P1.0
            reti                            ; Return from overflow ISR
                                            ;
TACCR1_ISR  add.w   #1000,&TACCR1           ; Offset until next interrupt
            reti                            ; Return ISR
                                            ;
TACCR2_ISR  add.w   #10000,&TACCR2          ; Offset until next interrupt
            reti                            ; Return ISR
                                            ;
;-------------------------------------------------------------------------------
            COMMON  INTVEC                  ; Interrupt Vectors
;-------------------------------------------------------------------------------
            ORG     RESET_VECTOR            ; MSP430 RESET Vector
            DW      RESET                   ;
            ORG     TIMERA0_VECTOR          ; Timer_A0 Vector
            DW      TA0_ISR                 ;
            ORG     TIMERA1_VECTOR          ; Timer_AX Vector
            DW      TAX_ISR                 ;
            END