DMA配置
//初始化DMA
	DMAInitialize();
	DMACH1AddrConfig(((volatile Uint16*)&McbspbRegs.DXR1.all),((volatile Uint16*)&dma_data_out));
	DMACH1BurstConfig(0, 0, 0);
	DMACH1TransferConfig(14, 1, 0);
	DMACH1WrapConfig(1000, 0, 1000, 0);
	DMACH1ModeConfig(16, 1, 0, 1, 0, 0, 0, 0, 0, 0);
	StartDMACH1();

	DMACH2AddrConfig(((volatile Uint16*)&dma_data_in),((volatile Uint16*)&McbspbRegs.DRR1.all));
	DMACH2BurstConfig(0, 0, 0);
	DMACH2TransferConfig(14, 0, 1);
	DMACH2WrapConfig(1000, 0, 1000, 0);
	DMACH2ModeConfig(17, 1, 0, 1, 0, 0, 0, 0, 0, 0);
	StartDMACH2();

MCBSPB配置
void InitMcbspb(void)
{

// McBSP-B register settings

    McbspbRegs.SPCR2.all=0x0000;		// Reset FS generator, sample rate generator & transmitter
	McbspbRegs.SPCR1.all=0x0000;		// Reset Receiver, Right justify word
	McbspbRegs.SPCR1.bit.DLB = 0;       // Enable loopback mode for test. Comment out for normal McBSP transfer mode.

	McbspbRegs.MFFINT.all=0x0004;			// 接收中断

    McbspbRegs.RCR2.all=0x0000;			// Single-phase frame, 15 word/frame, No companding	(Receive)
    McbspbRegs.RCR1.all=0x0e20;
	McbspbRegs.RCR2.bit.RFIG=1;

    McbspbRegs.XCR2.all=0x0000;			// Single-phase frame, 15 word/frame, No companding	(Transmit)
    McbspbRegs.XCR1.all=0x0e20;			//16位word
	McbspbRegs.XCR2.bit.XFIG=1;

    McbspbRegs.SRGR2.bit.FSGM=1;
    McbspbRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
	McbspbRegs.SRGR2.bit.FPER = 240;		// FPER = 32 CLKG periods,FSGM==0时不起作用

    McbspbRegs.SRGR1.bit.FWID = 0;              // Frame Width = 1 CLKG period，FSGM==0时不起作用
    McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;	// CLKG frequency = LSPCLK/(CLKGDV+1)

//	McbspbRegs.SPCR1.bit.RINTM=2;

   	McbspbRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
	McbspbRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source
    delay_loop();                // Wait at least 2 SRG clock cycles
    McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
	clkg_delay_loop();           // Wait at least 2 CLKG cycles
	McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
	McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
    McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}