/** @file spi.c * @brief SPI Driver Inmplmentation File * @date 15.March.2011 * @version 1.00.000 * * (c) Texas Instruments 2011, All rights reserved. */ #include "spi.h" /** @fn void spiInit(void) * @brief Initializes the SPI Driver * * This function initializes the SPI module. */ void spiInit(void) { /** @b intalise @b MIBSPI1 */ /** bring SPI out of reset */ spiREG1->GCR0 = 1U; /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ spiREG1->MIBSPIE = 0U; /** MIBSPI1 master mode and clock configuration */ spiREG1->GCR1 = (1 << 1) /* CLOKMOD */ | 1; /* MASTER */ /** MIBSPI1 enable pin configuration */ spiREG1->ENAHIGHZ = 0; /* ENABLE HIGHZ */ /** - Delays */ spiREG1->DELAY = (0 << 24) /* C2TDELAY */ | (0 << 16) /* T2CDELAY */ | (0 << 8) /* T2EDELAY */ | 0; /* C2EDELAY */ /** - Data Format 0 */ spiREG1->FMT0 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 8; /* data word length */ /** - Data Format 1 */ spiREG1->FMT1 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 2 */ spiREG1->FMT2 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 3 */ spiREG1->FMT3 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - wait for buffer inialisation complete before accessing MibSPI registers */ while (spiREG1->BUFINIT) { /* wait */ } /** - inialise transfer groups */ spiREG1->TGCTRL[0] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | (0 << 8); /* start buffer */ spiREG1->TGCTRL[1] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | (8 << 8); /* start buffer */ spiREG1->TGCTRL[2] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0) << 8); /* start buffer */ spiREG1->TGCTRL[3] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[4] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[5] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[6] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[7] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[8] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[9] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[10] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[11] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[12] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[13] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[14] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->TGCTRL[15] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0+0+0+0+0+0+0+0+0) << 8); /* start buffer */ spiREG1->LTGPEND = 8+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0-1; /** - initalise buffer ram */ { int i = 0; if (8 > 0) { while (i < 8-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_0; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_0; /* chip select */ } if (0 > 0) { while (i < 8+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_1; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_1; /* chip select */ } if (0 > 0) { while (i < 8+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_2; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_2; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_3; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_3; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_4; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_4; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_5; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_5; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_6; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_6; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0-1) { spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM1->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } } /** - set interrupt levels */ spiREG1->LVL = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** - clear any pending interrupts */ spiREG1->FLG = 0xFFFFFFFFU; /** - enable interrupts */ spiREG1->INT0 = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** @b initalise @b MIBSPI1 @b Port */ /** - MIBSPI1 Port output values */ spiREG1->PCDOUT = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 4) /* SCS[4] */ | (0 << 5) /* SCS[5] */ | (0 << 6) /* SCS[6] */ | (0 << 7) /* SCS[7] */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI1 Port direction */ spiREG1->PCDIR = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (0 << 4) /* SCS[4] */ | (1 << 5) /* SCS[5] */ | (1 << 6) /* SCS[6] */ | (0 << 7) /* SCS[7] */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI1 Port open drain enable */ spiREG1->PCPDR = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 4) /* SCS[4] */ | (0 << 5) /* SCS[5] */ | (0 << 6) /* SCS[6] */ | (0 << 7) /* SCS[7] */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI1 Port pullup / pulldown selection */ spiREG1->PCPSL = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 4) /* SCS[4] */ | (1 << 5) /* SCS[5] */ | (1 << 6) /* SCS[6] */ | (1 << 7) /* SCS[7] */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - MIBSPI1 Port pullup / pulldown enable*/ spiREG1->PCDIS = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 4) /* SCS[4] */ | (0 << 5) /* SCS[5] */ | (0 << 6) /* SCS[6] */ | (0 << 7) /* SCS[7] */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /* MIBSPI1 set all pins to functional */ spiREG1->PCFUN = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 4) /* SCS[4] */ | (1 << 5) /* SCS[5] */ | (1 << 6) /* SCS[6] */ | (1 << 7) /* SCS[7] */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - Finaly start MIBSPI1 */ spiREG1->ENA = 1U; /** @b intalise @b MIBSPI2 */ /** bring SPI out of reset */ spiREG2->GCR0 = 1U; /** enable MIBSPI2 multibuffered mode and enable buffer RAM */ spiREG2->MIBSPIE = 0U; /** MIBSPI2 master mode and clock configuration */ spiREG2->GCR1 = (1 << 1) /* CLOKMOD */ | 1; /* MASTER */ /** MIBSPI2 enable pin configuration */ spiREG2->ENAHIGHZ = 0; /* ENABLE HIGHZ */ /** - Delays */ spiREG2->DELAY = (7 << 24) /* C2TDELAY */ | (0 << 16) /* T2CDELAY */ | (0 << 8) /* T2EDELAY */ | 0; /* C2EDELAY */ /** - Data Format 0 */ spiREG2->FMT0 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (1 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 8; /* data word length */ /** - Data Format 1 */ spiREG2->FMT1 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 2 */ spiREG2->FMT2 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 3 */ spiREG2->FMT3 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - wait for buffer inialisation complete before accessing MibSPI registers */ while (spiREG2->BUFINIT) { /* wait */ } /** - inialise transfer groups */ spiREG2->TGCTRL[0] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | (0 << 8); /* start buffer */ spiREG2->TGCTRL[1] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | (8 << 8); /* start buffer */ spiREG2->TGCTRL[2] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0) << 8); /* start buffer */ spiREG2->TGCTRL[3] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0) << 8); /* start buffer */ spiREG2->TGCTRL[4] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0) << 8); /* start buffer */ spiREG2->TGCTRL[5] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0) << 8); /* start buffer */ spiREG2->TGCTRL[6] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0) << 8); /* start buffer */ spiREG2->TGCTRL[7] = (1 << 30) /* oneshot */ | (0 << 29) /* pcurrent reset */ | (TRG_ALWAYS << 20) /* trigger event */ | (TRG_DISABLED << 16) /* trigger source */ | ((8+0+0+0+0+0+0) << 8); /* start buffer */ spiREG2->LTGPEND = 8+0+0+0+0+0+0+0-1; /** - initalise buffer ram */ { int i = 0; if (8 > 0) { while (i < 8-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_0; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_0; /* chip select */ } if (0 > 0) { while (i < 8+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_1; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_1; /* chip select */ } if (0 > 0) { while (i < 8+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_2; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_2; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_3; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_3; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_4; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_4; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_5; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_5; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_6; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_6; /* chip select */ } if (0 > 0) { while (i < 8+0+0+0+0+0+0+0-1) { spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (1 << 12) /* hold chip select */ | (0 << 11) /* lock transmission */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } spiRAM2->tx[i++].control = (4 << 13) /* buffer mode */ | (0 << 12) /* chip select hold */ | (0 << 10) /* enable WDELAY */ | (0 << 8) /* data format */ | CS_7; /* chip select */ } } /** - set interrupt levels */ spiREG2->LVL = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** - clear any pending interrupts */ spiREG2->FLG = 0xFFFFFFFFU; /** - enable interrupts */ spiREG2->INT0 = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** @b initalise @b MIBSPI2 @b Port */ /** - MIBSPI2 Port output values */ spiREG2->PCDOUT = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI2 Port direction */ spiREG2->PCDIR = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI2 Port open drain enable */ spiREG2->PCPDR = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - MIBSPI2 Port pullup / pulldown selection */ spiREG2->PCPSL = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - MIBSPI2 Port pullup / pulldown enable*/ spiREG2->PCDIS = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /* MIBSPI2 set all pins to functional */ spiREG2->PCFUN = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - Finaly start MIBSPI2 */ spiREG2->ENA = 1U; /** @b intalise @b SPI3 */ /** bring SPI out of reset */ spiREG3->GCR0 = 1U; /** SPI3 master mode and clock configuration */ spiREG3->GCR1 = (1 << 1) /* CLOKMOD */ | 1; /* MASTER */ /** SPI3 enable pin configuration */ spiREG3->ENAHIGHZ = 0; /* ENABLE HIGHZ */ /** - Delays */ spiREG3->DELAY = (0 << 24) /* C2TDELAY */ | (0 << 16) /* T2CDELAY */ | (0 << 8) /* T2EDELAY */ | 0; /* C2EDELAY */ /** - Data Format 0 */ spiREG3->FMT0 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 1 */ spiREG3->FMT1 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 2 */ spiREG3->FMT2 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - Data Format 3 */ spiREG3->FMT3 = (0 << 24) /* wdelay */ | (0 << 23) /* parity Polarity */ | (0 << 22) /* parity enable */ | (0 << 21) /* wait on enable */ | (0 << 20) /* shift direction */ | (0 << 17) /* clock polarity */ | (0 << 16) /* clock phase */ | (79 << 8) /* baudrate prescale */ | 16; /* data word length */ /** - set interrupt levels */ spiREG3->LVL = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** - clear any pending interrupts */ spiREG3->FLG = 0xFFFFFFFFU; /** - enable interrupts */ spiREG3->INT0 = (0 << 9) /* TXINT */ | (0 << 8) /* RXINT */ | (0 << 6) /* OVRNINT */ | (0 << 4) /* BITERR */ | (0 << 3) /* DESYNC */ | (0 << 2) /* PARERR */ | (0 << 1) /* TIMEOUT */ | (0); /* DLENERR */ /** @b initalise @b SPI3 @b Port */ /** - SPI3 Port output values */ spiREG3->PCDOUT = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - SPI3 Port direction */ spiREG3->PCDIR = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - SPI3 Port open drain enable */ spiREG3->PCPDR = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /** - SPI3 Port pullup / pulldown selection */ spiREG3->PCPSL = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - SPI3 Port pullup / pulldown enable*/ spiREG3->PCDIS = 0 /* SCS[0] */ | (0 << 1) /* SCS[1] */ | (0 << 2) /* SCS[2] */ | (0 << 3) /* SCS[3] */ | (0 << 8) /* ENA */ | (0 << 9) /* CLK */ | (0 << 10) /* SIMO */ | (0 << 11); /* SOMI */ /* SPI3 set all pins to functional */ spiREG3->PCFUN = 1 /* SCS[0] */ | (1 << 1) /* SCS[1] */ | (1 << 2) /* SCS[2] */ | (1 << 3) /* SCS[3] */ | (1 << 8) /* ENA */ | (1 << 9) /* CLK */ | (1 << 10) /* SIMO */ | (1 << 11); /* SOMI */ /** - Finaly start SPI3 */ spiREG3->ENA = 1U; } /** @fn void spiSetFunctional(spiBASE_t *spi, unsigned port) * @brief Change functional behavoiur of pins at runtime. * @param[in] spi - Spi module base address * @param[in] port - Value to write to PCFUN register * * Change the value of the PCFUN register at runtime, this allows to * dynaimcaly change the functionality of the SPI pins between functional * and GIO mode. */ void spiSetFunctional(spiBASE_t *spi, unsigned port) { spi->PCFUN = port; } /** @fn void spiSetData(spiBASE_t *spi, unsigned group, unsigned short data[]) * @brief Set Buffer Data * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * @param[in] data - new data for transfer group * * This function updates the data for the specified transfer group, * the length of the data must match the length of the transfer group. */ void spiSetData(spiBASE_t *spi, unsigned group, unsigned short data[]) { spiRAM_t *ram = spi == spiREG1 ? spiRAM1 : spiRAM2; unsigned start = (spi->TGCTRL[group] >> 8) & 0xFF; unsigned end = group == 7 ? (spi->LTGPEND + 1) : (spi->TGCTRL[group+1] >> 8) & 0xFF; if (end < start) {end = 128;} while (start < end) { ram->tx[start].data = *data++; start++; } } /** @fn void spiGetData(spiBASE_t *spi, unsigned group, unsigned short data[]) * @brief Retrieves Buffer Data fro receive buffer * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * @param[out] data - pointer to data array * * @return error flags from data buffer, if there was a receive error on * one of the buffers this will be rerflected in the return value. * * This function transfers the data from the specified transfer group receve * buffers to the data array, the length of the data must match the length * of the transfer group. */ unsigned spiGetData(spiBASE_t *spi, unsigned group, unsigned short data[]) { spiRAM_t *ram = spi == spiREG1 ? spiRAM1 : spiRAM2; unsigned start = (spi->TGCTRL[group] >> 8) & 0xFF; unsigned end = group == 7 ? (spi->LTGPEND + 1) : (spi->TGCTRL[group+1] >> 8) & 0xFF; unsigned flags = 0; if (end < start) {end = 128;} while (start < end) { flags |= ram->rx[start].flags; *data++ = ram->rx[start].data; start++; } return (flags >> 8) & 0x5F; } /** @fn unsigned spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, unsigned blocksize, unsigned short *destbuff) * @brief Receives Data using polling method * @param[in] spi - Spi module base address * @param[in] dataconfig_t - Spi DAT1 register configuration * @param[in] blocksize - number of data * @param[in] destbuff - Pointer to the destination data (16 bit). * * @return flag register value. * * This function transmits blocksize number of data from source buffer using polling method. */ unsigned spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, unsigned blocksize, unsigned short *destbuff) { do { if(spi->FLG & 0x000000FF) { break; } spi->DAT1 = dataconfig_t->DFSEL << 24 | dataconfig_t->CSNR << 16 | dataconfig_t->WDEL << 26 | dataconfig_t->CS_HOLD << 28 | 0x0000; while((spi->FLG & 0x00000100) != 0x00000100); *destbuff++ = spi->BUF; }while(blocksize-- > 0); return (spi->FLG & 0xFF); } /** @fn unsigned spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, unsigned blocksize, void *srcbuff) * @brief Transmits Data using polling method * @param[in] spi - Spi module base address * @param[in] dataconfig_t - Spi DAT1 register configuration * @param[in] blocksize - number of data * @param[in] srcbuff - Pointer to the source data ( 16 bit). * * @return flag register value. * * This function transmits blocksize number of data from source buffer using polling method. */ unsigned spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, unsigned blocksize, unsigned short *srcbuff) { volatile unsigned SpiBuf; do { if(spi->FLG & 0x000000FF) { break; } spi->DAT1 = dataconfig_t->DFSEL << 24 | dataconfig_t->CSNR << 16 | dataconfig_t->WDEL << 26 | dataconfig_t->CS_HOLD << 28 | *srcbuff++; while((spi->FLG & 0x00000100) != 0x00000100); SpiBuf = spi->BUF; }while(blocksize-- > 0); return (spi->FLG & 0xFF); } /** @fn void spiTransfer(spiBASE_t *spi, unsigned group) * @brief Transmit Transfer Group * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * * Initiates a transfer for the specified transfer group. */ void spiTransfer(spiBASE_t *spi, unsigned group) { spi->TGCTRL[group] |= 0x80000000; } /** @fn int spiIsTransferComplete(spiBASE_t *spi, unsigned group) * @brief Check for Transfer Group Ready * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * * @return 1 is transfer complete, otherwise 0. * * Checks to see if the transfer for the specified transfer group * has finished. */ int spiIsTransferComplete(spiBASE_t *spi, unsigned group) { return (spi->INTFLGRDY >> group) & 1; } /** @fn void spiEnableGroupNotification(spiBASE_t *spi, unsigned group, unsigned level) * @brief Enable Transfer Group interrupt * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * @param[in] level - Interrupt level * * This function enables the transfer group finished interrupt. */ void spiEnableGroupNotification(spiBASE_t *spi, unsigned group, unsigned level) { if (level) { spi->SETINTLVLRDY = 1 << group; } else { spi->CLRINTLVLRDY = 1 << group; } spi->SETINTENARDY = 1 << group; } /** @fn void spiDisableGroupNotification(spiBASE_t *spi, unsigned group) * @brief Disable Transfer Group interrupt * @param[in] spi - Spi module base address * @param[in] group - Transfer group (0..7) * * This function disables the transfer group finished interrupt. */ void spiDisableGroupNotification(spiBASE_t *spi, unsigned group) { spi->CLRINTENARDY = 1 << group; } /** @fn void spi1LowLevelInterrupt(void) * @brief Level0 Interrupt for MIBSPI1 */ #pragma INTERRUPT(spi1LowLevelInterrupt) void spi1LowLevelInterrupt(void) { unsigned vec = spiREG1->INTVECT0; if (vec > 0x100001U) { unsigned flags = spiREG1->FLG & (~spiREG1->LVL & 0x035F); spiREG1->FLG = flags; spiNotification(spiREG1, flags); } else { spiGroupNotification(spiREG1, ((vec & 0x3FU) >> 1U) - 1U); } } /** @fn void spi1HighLevelInterrupt(void) * @brief Level1 Interrupt for MIBSPI1 */ #pragma INTERRUPT(spi1HighLevelInterrupt) void spi1HighLevelInterrupt(void) { unsigned vec = spiREG1->INTVECT1; if (vec > 0x100001U) { unsigned flags = spiREG1->FLG & (spiREG1->LVL & 0x035F); spiREG1->FLG = flags; spiNotification(spiREG1, flags); } else { spiGroupNotification(spiREG1, ((vec & 0x3FU) >> 1U) - 1U); } } /** @fn void spi2LowLevelInterrupt(void) * @brief Level0 Interrupt for MIBSPI2 */ #pragma INTERRUPT(spi2LowLevelInterrupt) void spi2LowLevelInterrupt(void) { unsigned vec = spiREG2->INTVECT0; if (vec > 0x100001U) { unsigned flags = spiREG2->FLG & (~spiREG2->LVL & 0x035F); spiREG2->FLG = flags; spiNotification(spiREG2, flags); } else { spiGroupNotification(spiREG2, ((vec & 0x3FU) >> 1U) - 1U); } } /** @fn void spi2HighLevelInterrupt(void) * @brief Level1 Interrupt for MIBSPI2 */ #pragma INTERRUPT(spi2HighLevelInterrupt) void spi2HighLevelInterrupt(void) { unsigned vec = spiREG2->INTVECT1; if (vec > 0x100001U) { unsigned flags = spiREG2->FLG & (spiREG2->LVL & 0x035F); spiREG2->FLG = flags; spiNotification(spiREG2, flags); } else { spiGroupNotification(spiREG2, ((vec & 0x3FU) >> 1U) - 1U); } } /** @fn void spi3LowLevelInterrupt(void) * @brief Level0 Interrupt for SPI3 */ #pragma INTERRUPT(spi3LowLevelInterrupt) void spi3LowLevelInterrupt(void) { unsigned vec = spiREG3->INTVECT0; if (vec > 0x100001U) { unsigned flags = spiREG3->FLG & (~spiREG3->LVL & 0x035F); spiREG3->FLG = flags; spiNotification(spiREG3, flags); } else { spiGroupNotification(spiREG3, ((vec & 0x3FU) >> 1U) - 1U); } } /** @fn void spi3HighLevelInterrupt(void) * @brief Level1 Interrupt for SPI3 */ #pragma INTERRUPT(spi3HighLevelInterrupt) void spi3HighLevelInterrupt(void) { unsigned vec = spiREG3->INTVECT1; if (vec > 0x100001U) { unsigned flags = spiREG3->FLG & (~spiREG3->LVL & 0x035F); spiREG3->FLG = flags; spiNotification(spiREG3, flags); } else { spiGroupNotification(spiREG3, ((vec & 0x3FU) >> 1U) - 1U); } } void spiGroupNotification(spiBASE_t *spi, unsigned group) { } void spiNotification(spiBASE_t *spi, unsigned flags) { } void spi_write(unsigned short data) { unsigned int a = 0; //spiREG2->INT0 |= 0x300; spiREG2->DAT1 = 0xff & data; //while(!(spiREG2->FLG & (1 << 9))); }