main()
{
  _DINT(); 
  WDTCTL = WDTPW | WDTHOLD;

  PortInit();  
  
  Ucs_Init_16M();
//  Ucs_Init_1M();
  
  TimerA0CounterSetup();

while(1)  
  {
    __bis_SR_register(LPM3_bits | GIE);     // Enter LPM3

    WDTCTL = WDTPW | WDTCNTCL | WDTSSEL0_L | WDTIS_2;

    UCA1IE |= UCRXIE;    
    
    APP_RTCPro_Delay_ms(2);


    uiTranceiver=TA0R;
    do
    {
      __bis_SR_register(LPM3_bits | GIE);     // Enter LPM3

      if(TA0R>=uiTranceiver)uiTemp=TA0R;
      else uiTemp=TA0R+0x8000;
      if((uiTemp-uiTranceiver)> T50ms) //400ms
      {
        P1OUT |= BIT3;
       P3OUT |=BIT3;;
        break;
      }
    }while((uiTemp-uiTranceiver)<(T200ms+T200ms));
    
    P1OUT |= BIT3;
    UCA1IE &= ~UCRXIE; 
  }
}


void Ucs_Init_16M(void)
{
  FRCTL0 = FRCTLPW | NWAITS_1;
  P2SEL0 |= BIT0 | BIT1; 
  do
  {
    CSCTL7 &= ~(XT1OFFG | DCOFFG);           // Clear XT1 and DCO fault flag
    SFRIFG1 &= ~OFIFG;
   } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

  __bis_SR_register(SCG0);                           // disable FLL

  CSCTL3 |= SELREF__XT1CLK;
  CSCTL0 = 0;                                        // clear DCO and MOD registers
  CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
  CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz

  CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz

  __delay_cycles(3);
  __bic_SR_register(SCG0);                           // enable FLL
  while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked

  CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;  // MCLK=SMCLK=DCO; ACLK=XT1

  PM5CTL0 &= ~LOCKLPM5;
}


void TimerA0CounterSetup(void)
{
  TA0CCTL0 |= CCIE;     // CCR0 interrupt enabled
  TA0CCR0 = 0x8000;
  TA0CTL = TASSEL_1 | TACLR | ID_3 | MC_1;            // ACLK, clear TAR,8·ÖƵ£¬Up to CCR0
}