请问adc11c125配置成为差分时钟输入的时候, 差分输入的电平标准是什么样的?LVPECL Output标准可以吗?
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请问adc11c125配置成为差分时钟输入的时候, 差分输入的电平标准是什么样的?LVPECL Output标准可以吗?
CLK INPUT CHARACTERISTICS
VIN(1) Logical “1” Input Voltage VD = 3.6V 2.0 V (min)
VIN(0) Logical “0” Input Voltage VD = 3.0V 0.8 V (max)
when CLK_SEL/DF Input Voltage=(2/3) * VA, The clock input pins can be configured to a differential clock input signal. Input Common-Mode Voltage? clk+ -clk- = Differential Input Voltage ?