TDC7201的SPI从模式下DOUT无输出响应。片选csb1为0,csb2为1,sclk为11.0592MHz。主读时序 dout1均无输出,dout2未测试,应该一样。急
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TDC7201的SPI从模式下DOUT无输出响应。片选csb1为0,csb2为1,sclk为11.0592MHz。主读时序 dout1均无输出,dout2未测试,应该一样。急
测试的指令是读00h、03h、08h。均无miso 示波器测量mosi正常 sck正常
spi总线采用FPGA桥接,仅仅是柔性连接一下。设计原为8路tdc7201 即16路spi,测试中仅仅挂接一路 且同一芯片的另外一路spi从 保持 csb为1