TLV320ADC6140时钟源

您好， datasheet中有这样的描述： The device also supports an option to use BCLK, GPIO1, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to reduce power consumption. However, the ADC performance may degrade based on jitter from the external clock source, and
some processing features may not be supported if the external audio clock source frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications.
可以看到，使用外部时钟源可以减少功耗，但同时也降低了ADC的性能。 TI推荐的是当高性能音频应用的时候，使用内部PLL产生时钟。

芯片内部有个时钟产生模块PLL and clock generation， PDMCLK的时钟可通过PLL产生，频率范围可通过寄存器0X1F PDMCLK_DIV[1:0] 这两位，
PDMCLK divider value.
0d = PDMCLK is 2.8224 MHz or 3.072 MHz
1d = PDMCLK is 1.4112 MHz or 1.536 MHz
2d = PDMCLK is 705.6 kHz or 768 kHz
3d = PDMCLK is 5.6448 MHz or 6.144 MHz

您好，BCLK和fsclk是I2S接口引脚，而ADC6140这款ADC支持数字microphone输入，PDMCLK指的是PDM  digital microphone 接口的主时钟。

是不能将I2S的bclk和fsclk和PDMCLK关联的，GPIO1或GPIOx是可以配置为I2S的MCLK或者PDMCLK的，可以参考Configuring and Operating TLV320ADCx140 as Audio Bus Maste应用手册提到的，使用GPIO1 配置为I2S的MCLK。