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CDCI6214时钟输出不对 感觉PLL配置不对

输入时钟为xin 25mhz时钟,输出Y1 LVDS 200MHZ,输出Y2 LVDS 125MHZ,输出Y3 LVDS 125MHZ,输出Y4 LVDS 125MHZ,S设置PSA和PSB,输出信号不对,设置成REF可以输出时钟。