Lmk04828的疑问如下：
（1）第1页中说，Multi-mode: Dual PLL, single PLL, and Clock
Distribution，该芯片有双PLL、单PLL和时钟分配功能。
疑问：想使用时钟分配模式，则该芯片如何设置？
（2）第28页中The LMK0482x family has up to three reference clock inputs for PLL1. They are CLKin0, CLKin1, and CLKin2，
疑问：CLKin0 CLKin1 CLKin2只是PLL1的时钟输入么？如果不用PLL1，则时钟输入只能从oscin输入么？
（3）第30页中，The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.
The analog delay allows a nominal 25 ps step size and range from 0 to 575 ps of total delay.
The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles
疑问：digital delay延时可以关掉么？我们的需求是输出时钟和输入时钟要同相位。
（4）
第31页中，The LMK0482x family supports two types of 0-delay.
1. Cascaded 0-delay
2. Nested 0-delay
疑问：
0-delay是指输出和输入没有相位差么？
