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关于TPS53632G的用法疑问

user5015634
Intellectual 440 points
Other Parts Discussed in Thread: TPS53632G

目前在想一个使用氮化镓FET的DC-DC变换器方案，想使用半桥拓扑，输出28V10A，看到TI的TPS53632G这款控制器，目前存在的疑问是：

1、其控制半桥变换器的话输出电压最大只能到1.52V 吗？输出电流最大只能到60A？（官网看到的）。如果是这样，原因是什么？

2、只能用于半桥控制吗？

  • 0
    TI__Guru**** 308311 points
    Hi
    到1.52是芯片内部DAC基准范围，在外部反馈，是可以通过调节反馈电阻使得输出电压超过1.52V输出。
  • 0 回复 Johnsin Tao
    Intellectual 440 points
    在DC-DC变换器应用中，输入36-75V DC，那么我可以通过设置反馈分压比使其输出28V，是这样吗？另外，其两路PWM输出是相差180度导通还是同时导通的？
  • 0 回复 Johnsin Tao
    Intellectual 440 points
    补充一下，我说的情况是使用半桥拓扑，次级采用全波整流。这种情况下，是不是数据手册所说的单相的情况，这个时候两路PWM是如何输出呢，相位关系是怎样的？
  • 0 回复 Johnsin Tao
    Intellectual 440 points
    最大占空比是多少呢？
  • 0 回复 Johnsin Tao
    Intellectual 440 points

    你好，我现在正在使用TPS53632G设计一个半桥电源。参数：VIN=36-75V DC，VOUT=28V，IO=10A。设计过程中查看数据手册（A版次）有几个疑问向您请教一下。

    1、7.4.1和7.5.7中关于单相和多相的论述，如何理解多相的问题？CSP3是哪个引脚？

    During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, ISUM
    voltage corresponds to a single-phase inductor current only.
    During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.
    Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives
    the required interleaving of 360/n, where n is the number of phases.——7.4.1

    7.5.7 Active Phases
    Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to
    a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V
    supply and tie the CSN2 and CSN3 pins to GND.——7.5.7

    2、输出过压保护。

    在7.3.7中，7.3.7 Overvoltage Protection
    An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than VDAC.
    VOUT > + VPGDH greater than VDAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for
    the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or
    VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the
    processor 100% of the time, there is a second OVP level fixed at VOVPH which is always active. If the fixed OVP
    condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter
    remains in this state until the V5A, VDD or VINTF pin is reset.——7.3.7

    文中提到的VPGDH、VOVPH是指的什么？过压保护是如何检测到并且起作用的？

    在6.5 Electrical characteristic表格中：

    PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
    VOVPH Fixed OVP voltage VCSN1 > VOVPH for 1 µs 1.60 1.70 1.80 V
    VPGDH PGOOD high threshold Measured at the VFB pin w/r/t VID code, device
    latches OFF    		 190 245 mV
    VPGDL PGOOD low threshold Measured at the VFB pin w/r/t VID code, device
    latches OFF    		 -348 -280


    如何理解这些参数？过压保护是由CSN1脚检测吗》当其电压大于1.7V（VOVPH电压？）时发生过压保护？如果是这样，在本次设计中如何检测电流？因为CSN1脚连接的是VO，而VO=28V，应该如何配置电流检测呢？

    3、输出电流检测。

    如果使用电阻检测，是在输出滤波电感后面直接串联一个小电阻取检测而不需要温度补偿？

    如果次级使用全波整流，电流采样该如何配置？如何使用CSP1、CSN1与CSP2、CSN2？

    4、在8.2.1.2.7中，公式14中，RLL是什么参数？

    8.2.1.2.7 Step 7: Set the Load-Line Slope
    The load-line slope is set by resistor, RDROOP (between the DROOP pin and the COMP pin) and resistor RCOMP
    (between the COMP pin and the VREF pin). The gain of the DROOP amplifier (ADROOP) is calculated in
    Equation 14.
    (14)