对于raw capture mode,要求:The raw capture mode requires the same input clock for VPIF channel 0 and channel 1 (clock skew has to be aligned). A single clock signal should be connected to both VP_CLKIN0 and VP_CLKIN1。但我们目前硬件上,时钟只连接了VP_CLKIN0,VP_CLKIN1悬空。VPIF接口使用的D0~D9,共10bit数据,请问,在VP_CLKIN1悬空的情况下,为使raw capture mode正常工作,有没有什么方法或措施?