When the periodic service sequence is not met, the timer counter increments
until it matches the period and times out. During a time out, a pulse will be
asserted on the timer output pin, and an internal maskable interrupt (TINTLO)
will be triggered. The timer output pin can be externally connected to the NMI
(non-maskable interrupt) pin of the device. Note that the timer pulse width
must be configured to generate an active low pulse long enough for the CPU
to recognize it as a NMI pulse. The pulse width is configured using the PWID
bits of the timer control register (TCR).