请问当dsp-C6455的pll1模块的div4设置改变后clk4的输出频率为啥不变?输入晶振时钟50MHz,prediv为一,20倍频,div4是6分频,为啥输出频率为60MHz?
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请问当dsp-C6455的pll1模块的div4设置改变后clk4的输出频率为啥不变?输入晶振时钟50MHz,prediv为一,20倍频,div4是6分频,为啥输出频率为60MHz?