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TMS320C6678 如何去配置DDR3的模式寄存器(MRS)

Other Parts Discussed in Thread: TMS320C6678

在调试TMS320C6678的单板时出现了一个关于DDR3的问题

配置:DDR3型号为micron的MT41K1G8SN-107  (micron   DDR3-1866速率  8bit 位宽),6678挂了1个rank,由8片MT41K1G8SN-107颗粒组成64bit位宽;

write leveling的参数是按照TI的工具表自动生成的,目前我们是跑的1333的速率,运行DDR3测试会随机在某一片的某一byte出现错误(写进去的值和读出来的值不同),运行1000M的速率不会出错。

后来我们想去看DDR3颗粒的MRS是否配置,没有找到方法如何通过6678去配置DDR3的模式寄存器(MRS)。

问题:

6678是否能配置DDR3 的模式寄存器,能配置的话如何去配?

  • c6678中是可以去配置MRS的,详情请参考DDR3 user guide,配置程序可以参考下置顶帖中DDR3例程

    2.4.1 Mode Register Set (MRS or EMRS)
    DDR3 SDRAM contains mode and extended mode registers that configure the DDR3 memory for
    operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, etc.
    The DDR3 memory controller programs the mode and extended mode registers of the DDR3 memory by
    issuing MRS and EMRS commands. MRS and EMRS commands can be issued during DDR3 initialization
    as well as during normal operation as long as the external SDRAM is in idle state. When the MRS or
    EMRS command is executed, the value on DDRBA [1:0] selects the mode register to be written and the
    data on DDRA [12:0] is loaded into the register. DDRA [15:13] and DDRBA [2] are reserved and are
    programmed to 0 during MRS (or EMRS).
    Each mode register allows programming of different sets of DDR3 SDRAM parameters. The DDR3
    memory controller programs the mode registers in compliance with the JEDEC JESD79-3C spec. For
    more information about mode registers and how they are programmed, see the JEDEC spec.

  • jason chen11,你好,请问你们问题最终定位到原因了吗?

    我们有类似现象,我们用的4个16位MT41K256M16,跑的1250速率,固定在某一个芯片的低8位读写异常。(写进去的值和读出来的值不同)。

    想请教下你们排查的方法

  • Thomas Yang1

    请问C6678外挂的DDR3芯片,在DSP软件这边可以配置为非burst操作吗?

  • 问题定位到了,是异常DDR芯片的DQS, DQS#信号线原理图接反了,导致burst最后一个64bit出错

  • Hello 您好,

    能否共享一下您 MT41K1G8SN-107 DDR3的 参数配置,非常感谢!邮箱:32147272@qq.com
  • 我们遇到了同样的问题,请问您的解决了吗?